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Code Issues Releases Activity

Added BIOS-v1.41 ACPI Dump

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This commit is contained in:
Tyler Nguyen 2019-10-03 00:58:26 -07:00
parent dec08faf6d
commit fa598135eb
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GPG key ID: DB5B102B914991DA
61 changed files with 50837 additions and 0 deletions
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35385
ACPI/Disassembled ACPI/BIOS-v1.41/DSDT.dsl Normal file
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5650
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-0-DptfTabl.dsl Normal file
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File diff suppressed because it is too large Load diff

2842
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-1-SaSsdt.dsl Normal file
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117
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-10-Wwan.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-10-Wwan.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000002D1 (721)
* Revision 0x02
* Checksum 0x26
* OEM ID "LENOVO"
* OEM Table ID "Wwan"
* OEM Revision 0x00000001 (1)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "Wwan", 0x00000001)
{
External (_SB_.GPC0, MethodObj) // 1 Arguments
External (_SB_.PCI0.GPCB, MethodObj) // 0 Arguments
External (_SB_.PCI0.RP03, DeviceObj)
External (_SB_.PCI0.RP03._ADR, MethodObj) // 0 Arguments
External (_SB_.PCI0.RP03.PXSX, DeviceObj)
External (_SB_.PCI0.RP03.PXSX._ADR, IntObj)
External (_SB_.SPC0, MethodObj) // 2 Arguments
External (NEXP, IntObj)
External (WDC2, IntObj)
External (WDCT, IntObj)
External (WGUR, IntObj)
External (WLCT, IntObj)
External (WMNS, IntObj)
External (WMXS, IntObj)
Name (RSTP, Package (0x04)
{
Zero,
Zero,
Zero,
Zero
})
Scope (\_SB.PCI0.RP03)
{
Method (M2PC, 1, Serialized)
{
Store (\_SB.PCI0.GPCB (), Local0)
Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
Return (Local0)
}
Method (GMIO, 1, Serialized)
{
OperationRegion (PXCS, SystemMemory, M2PC (\_SB.PCI0.RP03._ADR ()), 0x20)
Field (PXCS, AnyAcc, NoLock, Preserve)
{
Offset (0x18),
PBUS, 8,
SBUS, 8
}
Store (\_SB.PCI0.GPCB (), Local0)
Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
Add (Local0, ShiftLeft (SBUS, 0x14), Local0)
Return (Local0)
}
Scope (PXSX)
{
Method (_RST, 0, Serialized) // _RST: Device Reset
{
OperationRegion (PXCS, SystemMemory, GMIO (\_SB.PCI0.RP03.PXSX._ADR), 0x0480)
Field (PXCS, AnyAcc, NoLock, Preserve)
{
VDID, 16,
DVID, 16,
Offset (0x78),
DCTL, 16,
DSTS, 16,
Offset (0x80),
LCTL, 16,
LSTS, 16,
Offset (0x98),
DCT2, 16,
Offset (0x148),
Offset (0x14C),
MXSL, 16,
MNSL, 16
}
Store (\_SB.GPC0 (\WGUR), Local0)
And (Local0, 0xFFFFFFFFFFFFFEFF, Local0)
\_SB.SPC0 (\WGUR, Local0)
Sleep (0xC8)
Notify (\_SB.PCI0.RP03.PXSX, One) // Device Check
Or (Local0, 0x0100, Local0)
\_SB.SPC0 (\WGUR, Local0)
Sleep (0xC8)
If (LEqual (NEXP, Zero))
{
Store (\WDCT, DCTL) /* \_SB_.PCI0.RP03.PXSX._RST.DCTL */
Store (\WLCT, LCTL) /* \_SB_.PCI0.RP03.PXSX._RST.LCTL */
Store (\WDC2, DCT2) /* \_SB_.PCI0.RP03.PXSX._RST.DCT2 */
Store (\WMXS, MXSL) /* \_SB_.PCI0.RP03.PXSX._RST.MXSL */
Store (\WMNS, MNSL) /* \_SB_.PCI0.RP03.PXSX._RST.MNSL */
}
Notify (\_SB.PCI0.RP03.PXSX, One) // Device Check
}
}
}
}

344
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-2-PerfTune.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-2-PerfTune.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000005C6 (1478)
* Revision 0x02
* Checksum 0x9F
* OEM ID "LENOVO"
* OEM Table ID "PerfTune"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "PerfTune", 0x00001000)
{
External (_SB_.PCI0.LPCB.H_EC.CFSP, UnknownObj)
External (_SB_.PCI0.LPCB.H_EC.DIM0, UnknownObj)
External (_SB_.PCI0.LPCB.H_EC.DIM1, UnknownObj)
External (_SB_.PCI0.LPCB.H_EC.ECRD, MethodObj) // 1 Arguments
External (_TZ_.TZ01._TMP, MethodObj) // 0 Arguments
External (ADBG, MethodObj) // 1 Arguments
External (DDRF, UnknownObj)
External (ECON, IntObj)
External (TSOD, IntObj)
External (XMPB, UnknownObj)
External (XSMI, UnknownObj)
External (XTUB, UnknownObj)
External (XTUS, UnknownObj)
Scope (\_SB)
{
Device (PTMD)
{
Name (_HID, EisaId ("INT3394") /* ACPI System Fan */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _CID: Compatible ID
Name (IVER, 0x00010000)
Name (SIZE, 0x055C)
Method (GACI, 0, NotSerialized)
{
Name (RPKG, Package (0x02){})
Store (Zero, Index (RPKG, Zero))
If (LNotEqual (XTUB, Zero))
{
ADBG ("XTUB")
ADBG (XTUB)
ADBG ("XTUS")
ADBG (XTUS)
OperationRegion (XNVS, SystemMemory, XTUB, SIZE)
Field (XNVS, ByteAcc, NoLock, Preserve)
{
XBUF, 10976
}
Name (TEMP, Buffer (XTUS){})
Store (XBUF, TEMP) /* \_SB_.PTMD.GACI.TEMP */
Store (TEMP, Index (RPKG, One))
}
Else
{
ADBG ("XTUB ZERO")
Store (Zero, Index (RPKG, One))
}
Return (RPKG) /* \_SB_.PTMD.GACI.RPKG */
}
Method (GDSV, 1, Serialized)
{
If (LEqual (Arg0, 0x05))
{
Return (Package (0x02)
{
Zero,
Buffer (0x68)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x4C, 0x04, 0x00, 0x00, // ....L...
/* 0010 */ 0x02, 0x00, 0x00, 0x00, 0x7E, 0x04, 0x00, 0x00, // ....~...
/* 0018 */ 0x03, 0x00, 0x00, 0x00, 0xB0, 0x04, 0x00, 0x00, // ........
/* 0020 */ 0x04, 0x00, 0x00, 0x00, 0xE2, 0x04, 0x00, 0x00, // ........
/* 0028 */ 0x05, 0x00, 0x00, 0x00, 0x14, 0x05, 0x00, 0x00, // ........
/* 0030 */ 0x06, 0x00, 0x00, 0x00, 0x46, 0x05, 0x00, 0x00, // ....F...
/* 0038 */ 0x07, 0x00, 0x00, 0x00, 0x78, 0x05, 0x00, 0x00, // ....x...
/* 0040 */ 0x08, 0x00, 0x00, 0x00, 0xAA, 0x05, 0x00, 0x00, // ........
/* 0048 */ 0x09, 0x00, 0x00, 0x00, 0xDC, 0x05, 0x00, 0x00, // ........
/* 0050 */ 0x0A, 0x00, 0x00, 0x00, 0x0E, 0x06, 0x00, 0x00, // ........
/* 0058 */ 0x0B, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00, // ....@...
/* 0060 */ 0x0C, 0x00, 0x00, 0x00, 0x72, 0x06, 0x00, 0x00 // ....r...
}
})
}
If (LEqual (Arg0, 0x13))
{
ADBG ("DDR MULT")
If (LEqual (DDRF, One))
{
ADBG ("DDR 1")
Return (Package (0x02)
{
Zero,
Buffer (0x50)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x04, 0x00, 0x00, 0x00, 0x2B, 0x04, 0x00, 0x00, // ....+...
/* 0010 */ 0x05, 0x00, 0x00, 0x00, 0x35, 0x05, 0x00, 0x00, // ....5...
/* 0018 */ 0x06, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00, // ....@...
/* 0020 */ 0x07, 0x00, 0x00, 0x00, 0x4B, 0x07, 0x00, 0x00, // ....K...
/* 0028 */ 0x08, 0x00, 0x00, 0x00, 0x55, 0x08, 0x00, 0x00, // ....U...
/* 0030 */ 0x09, 0x00, 0x00, 0x00, 0x60, 0x09, 0x00, 0x00, // ....`...
/* 0038 */ 0x0A, 0x00, 0x00, 0x00, 0x6B, 0x0A, 0x00, 0x00, // ....k...
/* 0040 */ 0x0B, 0x00, 0x00, 0x00, 0x75, 0x0B, 0x00, 0x00, // ....u...
/* 0048 */ 0x0C, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00 // ........
}
})
}
Else
{
ADBG ("DDR ELSE")
Return (Package (0x02)
{
Zero,
Buffer (0x68)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x05, 0x00, 0x00, 0x00, 0x2B, 0x04, 0x00, 0x00, // ....+...
/* 0010 */ 0x06, 0x00, 0x00, 0x00, 0xB0, 0x04, 0x00, 0x00, // ........
/* 0018 */ 0x07, 0x00, 0x00, 0x00, 0x78, 0x05, 0x00, 0x00, // ....x...
/* 0020 */ 0x08, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00, // ....@...
/* 0028 */ 0x09, 0x00, 0x00, 0x00, 0x08, 0x07, 0x00, 0x00, // ........
/* 0030 */ 0x0A, 0x00, 0x00, 0x00, 0xD0, 0x07, 0x00, 0x00, // ........
/* 0038 */ 0x0B, 0x00, 0x00, 0x00, 0x98, 0x08, 0x00, 0x00, // ........
/* 0040 */ 0x0C, 0x00, 0x00, 0x00, 0x60, 0x09, 0x00, 0x00, // ....`...
/* 0048 */ 0x0D, 0x00, 0x00, 0x00, 0x28, 0x0A, 0x00, 0x00, // ....(...
/* 0050 */ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x0A, 0x00, 0x00, // ........
/* 0058 */ 0x0F, 0x00, 0x00, 0x00, 0xB8, 0x0B, 0x00, 0x00, // ........
/* 0060 */ 0x10, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00 // ........
}
})
}
ADBG ("DDR EXIT")
}
If (LEqual (Arg0, 0x0B))
{
Return (Package (0x02)
{
Zero,
Buffer (0x60)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, // ........
/* 0010 */ 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, // ........
/* 0018 */ 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, // ........
/* 0020 */ 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, // ........
/* 0028 */ 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, // ........
/* 0030 */ 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, // ........
/* 0038 */ 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, // ........
/* 0040 */ 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, // ........
/* 0048 */ 0x12, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, // ........
/* 0050 */ 0x14, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, // ........
/* 0058 */ 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00 // ........
}
})
}
If (LEqual (Arg0, 0x49))
{
Return (Package (0x02)
{
Zero,
Buffer (0x18)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00, // ........
/* 0010 */ 0x02, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00 // ....d...
}
})
}
Return (Package (0x01)
{
One
})
}
Method (GXDV, 1, Serialized)
{
If (LNotEqual (XMPB, Zero))
{
OperationRegion (XMPN, SystemMemory, XMPB, SIZE)
Field (XMPN, ByteAcc, NoLock, Preserve)
{
XMP1, 576,
XMP2, 576
}
If (LEqual (Arg0, One))
{
Name (XP_1, Package (0x02){})
Store (Zero, Index (XP_1, Zero))
Store (XMP1, Index (XP_1, One))
Return (XP_1) /* \_SB_.PTMD.GXDV.XP_1 */
}
If (LEqual (Arg0, 0x02))
{
Name (XP_2, Package (0x02){})
Store (Zero, Index (XP_2, Zero))
Store (XMP2, Index (XP_2, One))
Return (XP_2) /* \_SB_.PTMD.GXDV.XP_2 */
}
}
Return (Package (0x01)
{
One
})
}
Method (GSCV, 0, NotSerialized)
{
Return (Package (0x01)
{
0x72
})
}
Method (GSCB, 0, NotSerialized)
{
Return (XSMI) /* External reference */
}
Method (CDRD, 1, Serialized)
{
Return (Package (0x01)
{
One
})
}
Method (CDWR, 2, Serialized)
{
Return (One)
}
Name (RPMV, Package (0x04)
{
One,
0x07,
Zero,
Zero
})
Name (TMP1, Package (0x0C)
{
One,
0x02,
Zero,
Zero,
0x05,
0x04,
Zero,
Zero,
0x06,
0x05,
Zero,
Zero
})
Name (TMP2, Package (0x08)
{
One,
0x02,
Zero,
Zero,
0x05,
0x04,
Zero,
Zero
})
Name (TMP3, Package (0x04)
{
One,
0x02,
Zero,
Zero
})
Method (TSDD, 0, NotSerialized)
{
If (LEqual (XTUS, Zero))
{
Return (Zero)
}
If (\ECON)
{
If (\TSOD)
{
Store (\_TZ.TZ01._TMP (), Index (TMP1, 0x02))
Return (TMP1) /* \_SB_.PTMD.TMP1 */
}
Else
{
Store (\_TZ.TZ01._TMP (), Index (TMP2, 0x02))
Return (TMP2) /* \_SB_.PTMD.TMP2 */
}
}
Else
{
Store (\_TZ.TZ01._TMP (), Index (TMP3, 0x02))
Return (TMP3) /* \_SB_.PTMD.TMP3 */
}
}
Method (FSDD, 0, NotSerialized)
{
If (LEqual (XTUS, Zero))
{
Return (Zero)
}
If (\ECON)
{
Store (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.CFSP)), Index (RPMV, 0x02))
}
Return (RPMV) /* \_SB_.PTMD.RPMV */
}
Method (SDSP, 0, NotSerialized)
{
Return (0x0A)
}
}
}
}

804
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-3-RVP7Rtd3.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-3-RVP7Rtd3.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00001D1D (7453)
* Revision 0x02
* Checksum 0x3D
* OEM ID "LENOVO"
* OEM Table ID "RVP7Rtd3"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "RVP7Rtd3", 0x00001000)
{
External (_SB_.GGOV, MethodObj) // 1 Arguments
External (_SB_.GPC0, MethodObj) // 1 Arguments
External (_SB_.OSCO, UnknownObj)
External (_SB_.PCI0, DeviceObj)
External (_SB_.PCI0.GEXP, DeviceObj)
External (_SB_.PCI0.GEXP.GEPS, MethodObj) // 2 Arguments
External (_SB_.PCI0.GEXP.SGEP, MethodObj) // 3 Arguments
External (_SB_.PCI0.GLAN, DeviceObj)
External (_SB_.PCI0.I2C0, DeviceObj)
External (_SB_.PCI0.I2C0.TPD0, DeviceObj)
External (_SB_.PCI0.I2C1, DeviceObj)
External (_SB_.PCI0.I2C1.TPL1, DeviceObj)
External (_SB_.PCI0.LPCB.H_EC.ECAV, IntObj)
External (_SB_.PCI0.LPCB.H_EC.SPT2, UnknownObj)
External (_SB_.PCI0.RP01, DeviceObj)
External (_SB_.PCI0.RP01.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP01.DPGE, UnknownObj)
External (_SB_.PCI0.RP01.L23E, UnknownObj)
External (_SB_.PCI0.RP01.L23R, UnknownObj)
External (_SB_.PCI0.RP01.LASX, UnknownObj)
External (_SB_.PCI0.RP01.LDIS, UnknownObj)
External (_SB_.PCI0.RP01.LEDM, UnknownObj)
External (_SB_.PCI0.RP01.VDID, UnknownObj)
External (_SB_.PCI0.RP02, DeviceObj)
External (_SB_.PCI0.RP02.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP02.DPGE, UnknownObj)
External (_SB_.PCI0.RP02.L23E, UnknownObj)
External (_SB_.PCI0.RP02.L23R, UnknownObj)
External (_SB_.PCI0.RP02.LASX, UnknownObj)
External (_SB_.PCI0.RP02.LDIS, UnknownObj)
External (_SB_.PCI0.RP02.LEDM, UnknownObj)
External (_SB_.PCI0.RP02.VDID, UnknownObj)
External (_SB_.PCI0.RP03, DeviceObj)
External (_SB_.PCI0.RP03.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP03.DPGE, UnknownObj)
External (_SB_.PCI0.RP03.L23E, UnknownObj)
External (_SB_.PCI0.RP03.L23R, UnknownObj)
External (_SB_.PCI0.RP03.LASX, UnknownObj)
External (_SB_.PCI0.RP03.LDIS, UnknownObj)
External (_SB_.PCI0.RP03.LEDM, UnknownObj)
External (_SB_.PCI0.RP03.VDID, UnknownObj)
External (_SB_.PCI0.RP04, DeviceObj)
External (_SB_.PCI0.RP04.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP04.DPGE, UnknownObj)
External (_SB_.PCI0.RP04.L23E, UnknownObj)
External (_SB_.PCI0.RP04.L23R, UnknownObj)
External (_SB_.PCI0.RP04.LASX, UnknownObj)
External (_SB_.PCI0.RP04.LDIS, UnknownObj)
External (_SB_.PCI0.RP04.LEDM, UnknownObj)
External (_SB_.PCI0.RP04.VDID, UnknownObj)
External (_SB_.PCI0.RP05, DeviceObj)
External (_SB_.PCI0.RP05.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP05.DPGE, UnknownObj)
External (_SB_.PCI0.RP05.L23E, UnknownObj)
External (_SB_.PCI0.RP05.L23R, UnknownObj)
External (_SB_.PCI0.RP05.LASX, UnknownObj)
External (_SB_.PCI0.RP05.LDIS, UnknownObj)
External (_SB_.PCI0.RP05.LEDM, UnknownObj)
External (_SB_.PCI0.RP05.VDID, UnknownObj)
External (_SB_.PCI0.RP06, DeviceObj)
External (_SB_.PCI0.RP06.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP06.DPGE, UnknownObj)
External (_SB_.PCI0.RP06.L23E, UnknownObj)
External (_SB_.PCI0.RP06.L23R, UnknownObj)
External (_SB_.PCI0.RP06.LASX, UnknownObj)
External (_SB_.PCI0.RP06.LDIS, UnknownObj)
External (_SB_.PCI0.RP06.LEDM, UnknownObj)
External (_SB_.PCI0.RP06.VDID, UnknownObj)
External (_SB_.PCI0.RP07, DeviceObj)
External (_SB_.PCI0.RP07.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP07.DPGE, UnknownObj)
External (_SB_.PCI0.RP07.L23E, UnknownObj)
External (_SB_.PCI0.RP07.L23R, UnknownObj)
External (_SB_.PCI0.RP07.LASX, UnknownObj)
External (_SB_.PCI0.RP07.LDIS, UnknownObj)
External (_SB_.PCI0.RP07.LEDM, UnknownObj)
External (_SB_.PCI0.RP07.VDID, UnknownObj)
External (_SB_.PCI0.RP08, DeviceObj)
External (_SB_.PCI0.RP08.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP08.DPGE, UnknownObj)
External (_SB_.PCI0.RP08.L23E, UnknownObj)
External (_SB_.PCI0.RP08.L23R, UnknownObj)
External (_SB_.PCI0.RP08.LASX, UnknownObj)
External (_SB_.PCI0.RP08.LDIS, UnknownObj)
External (_SB_.PCI0.RP08.LEDM, UnknownObj)
External (_SB_.PCI0.RP08.VDID, UnknownObj)
External (_SB_.PCI0.RP09, DeviceObj)
External (_SB_.PCI0.RP09.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP09.DPGE, UnknownObj)
External (_SB_.PCI0.RP09.L23E, UnknownObj)
External (_SB_.PCI0.RP09.L23R, UnknownObj)
External (_SB_.PCI0.RP09.LASX, UnknownObj)
External (_SB_.PCI0.RP09.LDIS, UnknownObj)
External (_SB_.PCI0.RP09.LEDM, UnknownObj)
External (_SB_.PCI0.RP09.PCRA, MethodObj) // 3 Arguments
External (_SB_.PCI0.RP09.PCRO, MethodObj) // 3 Arguments
External (_SB_.PCI0.RP09.VDID, UnknownObj)
External (_SB_.PCI0.RP10, DeviceObj)
External (_SB_.PCI0.RP10.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP10.DPGE, UnknownObj)
External (_SB_.PCI0.RP10.L23E, UnknownObj)
External (_SB_.PCI0.RP10.L23R, UnknownObj)
External (_SB_.PCI0.RP10.LASX, UnknownObj)
External (_SB_.PCI0.RP10.LDIS, UnknownObj)
External (_SB_.PCI0.RP10.LEDM, UnknownObj)
External (_SB_.PCI0.RP10.VDID, UnknownObj)
External (_SB_.PCI0.RP11, DeviceObj)
External (_SB_.PCI0.RP11.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP11.DPGE, UnknownObj)
External (_SB_.PCI0.RP11.L23E, UnknownObj)
External (_SB_.PCI0.RP11.L23R, UnknownObj)
External (_SB_.PCI0.RP11.LASX, UnknownObj)
External (_SB_.PCI0.RP11.LDIS, UnknownObj)
External (_SB_.PCI0.RP11.LEDM, UnknownObj)
External (_SB_.PCI0.RP11.VDID, UnknownObj)
External (_SB_.PCI0.RP12, DeviceObj)
External (_SB_.PCI0.RP12.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP12.DPGE, UnknownObj)
External (_SB_.PCI0.RP12.L23E, UnknownObj)
External (_SB_.PCI0.RP12.L23R, UnknownObj)
External (_SB_.PCI0.RP12.LASX, UnknownObj)
External (_SB_.PCI0.RP12.LDIS, UnknownObj)
External (_SB_.PCI0.RP12.LEDM, UnknownObj)
External (_SB_.PCI0.RP12.VDID, UnknownObj)
External (_SB_.PCI0.RP13, DeviceObj)
External (_SB_.PCI0.RP13.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP13.DPGE, UnknownObj)
External (_SB_.PCI0.RP13.L23E, UnknownObj)
External (_SB_.PCI0.RP13.L23R, UnknownObj)
External (_SB_.PCI0.RP13.LASX, UnknownObj)
External (_SB_.PCI0.RP13.LDIS, UnknownObj)
External (_SB_.PCI0.RP13.LEDM, UnknownObj)
External (_SB_.PCI0.RP13.VDID, UnknownObj)
External (_SB_.PCI0.RP14, DeviceObj)
External (_SB_.PCI0.RP14.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP14.DPGE, UnknownObj)
External (_SB_.PCI0.RP14.L23E, UnknownObj)
External (_SB_.PCI0.RP14.L23R, UnknownObj)
External (_SB_.PCI0.RP14.LASX, UnknownObj)
External (_SB_.PCI0.RP14.LDIS, UnknownObj)
External (_SB_.PCI0.RP14.LEDM, UnknownObj)
External (_SB_.PCI0.RP14.VDID, UnknownObj)
External (_SB_.PCI0.RP15, DeviceObj)
External (_SB_.PCI0.RP15.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP15.DPGE, UnknownObj)
External (_SB_.PCI0.RP15.L23E, UnknownObj)
External (_SB_.PCI0.RP15.L23R, UnknownObj)
External (_SB_.PCI0.RP15.LASX, UnknownObj)
External (_SB_.PCI0.RP15.LDIS, UnknownObj)
External (_SB_.PCI0.RP15.LEDM, UnknownObj)
External (_SB_.PCI0.RP15.VDID, UnknownObj)
External (_SB_.PCI0.RP16, DeviceObj)
External (_SB_.PCI0.RP16.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP16.DPGE, UnknownObj)
External (_SB_.PCI0.RP16.L23E, UnknownObj)
External (_SB_.PCI0.RP16.L23R, UnknownObj)
External (_SB_.PCI0.RP16.LASX, UnknownObj)
External (_SB_.PCI0.RP16.LDIS, UnknownObj)
External (_SB_.PCI0.RP16.LEDM, UnknownObj)
External (_SB_.PCI0.RP16.VDID, UnknownObj)
External (_SB_.PCI0.RP17, DeviceObj)
External (_SB_.PCI0.RP17.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP17.DPGE, UnknownObj)
External (_SB_.PCI0.RP17.L23E, UnknownObj)
External (_SB_.PCI0.RP17.L23R, UnknownObj)
External (_SB_.PCI0.RP17.LASX, UnknownObj)
External (_SB_.PCI0.RP17.LDIS, UnknownObj)
External (_SB_.PCI0.RP17.LEDM, UnknownObj)
External (_SB_.PCI0.RP17.VDID, UnknownObj)
External (_SB_.PCI0.RP18, DeviceObj)
External (_SB_.PCI0.RP18.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP18.DPGE, UnknownObj)
External (_SB_.PCI0.RP18.L23E, UnknownObj)
External (_SB_.PCI0.RP18.L23R, UnknownObj)
External (_SB_.PCI0.RP18.LASX, UnknownObj)
External (_SB_.PCI0.RP18.LDIS, UnknownObj)
External (_SB_.PCI0.RP18.LEDM, UnknownObj)
External (_SB_.PCI0.RP18.VDID, UnknownObj)
External (_SB_.PCI0.RP19, DeviceObj)
External (_SB_.PCI0.RP19.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP19.DPGE, UnknownObj)
External (_SB_.PCI0.RP19.L23E, UnknownObj)
External (_SB_.PCI0.RP19.L23R, UnknownObj)
External (_SB_.PCI0.RP19.LASX, UnknownObj)
External (_SB_.PCI0.RP19.LDIS, UnknownObj)
External (_SB_.PCI0.RP19.LEDM, UnknownObj)
External (_SB_.PCI0.RP19.VDID, UnknownObj)
External (_SB_.PCI0.RP20, DeviceObj)
External (_SB_.PCI0.RP20.D3HT, FieldUnitObj)
External (_SB_.PCI0.RP20.DPGE, UnknownObj)
External (_SB_.PCI0.RP20.L23E, UnknownObj)
External (_SB_.PCI0.RP20.L23R, UnknownObj)
External (_SB_.PCI0.RP20.LASX, UnknownObj)
External (_SB_.PCI0.RP20.LDIS, UnknownObj)
External (_SB_.PCI0.RP20.LEDM, UnknownObj)
External (_SB_.PCI0.RP20.VDID, UnknownObj)
External (_SB_.PCI0.SAT0, DeviceObj)
External (_SB_.PCI0.SAT0.PRT0, DeviceObj)
External (_SB_.PCI0.SAT0.PRT1, DeviceObj)
External (_SB_.PCI0.SAT0.PRT2, DeviceObj)
External (_SB_.PCI0.SAT0.PRT3, DeviceObj)
External (_SB_.PCI0.SAT0.PRT4, DeviceObj)
External (_SB_.PCI0.SAT0.PRT5, DeviceObj)
External (_SB_.PCI0.XDCI, DeviceObj)
External (_SB_.PCI0.XDCI.D0I3, UnknownObj)
External (_SB_.PCI0.XDCI.XDCB, UnknownObj)
External (_SB_.PCI0.XHC_, DeviceObj)
External (_SB_.PCI0.XHC_.MEMB, UnknownObj)
External (_SB_.PCI0.XHC_.PMEE, UnknownObj)
External (_SB_.PCI0.XHC_.PMES, UnknownObj)
External (_SB_.PCI0.XHC_.RHUB, DeviceObj)
External (_SB_.PCI0.XHC_.RHUB.HS01, DeviceObj)
External (_SB_.PCI0.XHC_.RHUB.HS02, DeviceObj)
External (_SB_.PCI0.XHC_.RHUB.SS01, DeviceObj)
External (_SB_.PCI0.XHC_.RHUB.SS02, DeviceObj)
External (_SB_.SGOV, MethodObj) // 2 Arguments
External (_SB_.SHPO, MethodObj) // 2 Arguments
External (_SB_.SPC0, MethodObj) // 2 Arguments
External (ADBG, MethodObj) // 1 Arguments
External (AUDD, FieldUnitObj)
External (DVID, UnknownObj)
External (ECON, IntObj)
External (GBEP, UnknownObj)
External (I20D, FieldUnitObj)
External (I21D, FieldUnitObj)
External (IC0D, FieldUnitObj)
External (IC1D, FieldUnitObj)
External (IC1S, FieldUnitObj)
External (MMRP, MethodObj) // 1 Arguments
External (MMTB, MethodObj) // 1 Arguments
External (OSYS, UnknownObj)
External (PCHG, UnknownObj)
External (PCHS, UnknownObj)
External (PEP0, UnknownObj)
External (PEP3, UnknownObj)
External (PWRM, UnknownObj)
External (RCG0, IntObj)
External (RCG1, IntObj)
External (RIC0, FieldUnitObj)
External (RTBC, IntObj)
External (RTBT, IntObj)
External (RTD3, IntObj)
External (S0ID, UnknownObj)
External (SDS0, FieldUnitObj)
External (SDS1, FieldUnitObj)
External (SGMD, UnknownObj)
External (SHSB, FieldUnitObj)
External (SPST, IntObj)
External (TBCD, IntObj)
External (TBHR, IntObj)
External (TBOD, IntObj)
External (TBPE, IntObj)
External (TBRP, IntObj)
External (TBSE, IntObj)
External (TBTS, IntObj)
External (TOFF, IntObj)
External (TRD3, IntObj)
External (TRDO, IntObj)
External (UAMS, UnknownObj)
External (VRRD, FieldUnitObj)
External (VRSD, FieldUnitObj)
External (XDST, IntObj)
External (XHPR, UnknownObj)
If (LAnd (LEqual (\RTBT, 0x01), LEqual (\TBTS, 0x01)))
{
Scope (\_SB.PCI0.RP09)
{
Name (SLOT, 0x09)
ADBG ("Rvp7Rtd3:Slot:")
ADBG (SLOT)
Name (RSTG, Package (0x04)
{
0x01,
0x00,
0x02060006,
0x01
})
Name (PWRG, Package (0x04)
{
0x01,
0x00,
0x02060004,
0x01
})
Name (WAKG, Package (0x04)
{
0x01,
0x00,
0x02060007,
0x00
})
Name (SCLK, Package (0x03)
{
0x01,
0x20,
0x00
})
Name (G2SD, 0x00)
Name (WKEN, 0x00)
Method (_PS0, 0, Serialized) // _PS0: Power State 0
{
OperationRegion (PLTR, SystemMemory, PWRM, 0x0800)
Field (PLTR, AnyAcc, NoLock, Preserve)
{
Offset (0x3EC),
Offset (0x3EE),
BI16, 1,
Offset (0x3EF),
BI24, 1
}
Store (0x01, BI16) /* \_SB_.PCI0.RP09._PS0.BI16 */
Store (0x00, BI24) /* \_SB_.PCI0.RP09._PS0.BI24 */
}
Method (_PS3, 0, Serialized) // _PS3: Power State 3
{
OperationRegion (PLTR, SystemMemory, PWRM, 0x0800)
Field (PLTR, AnyAcc, NoLock, Preserve)
{
Offset (0x3EC),
Offset (0x3EE),
BI16, 1,
Offset (0x3EF),
BI24, 1
}
Store (0x00, BI16) /* \_SB_.PCI0.RP09._PS3.BI16 */
Store (0x00, BI24) /* \_SB_.PCI0.RP09._PS3.BI24 */
}
Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State
{
Return (0x04)
}
Method (_DSD, 0, NotSerialized) // _DSD: Device-Specific Data
{
ADBG ("Tbt:_DSD")
Return (Package (0x02)
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
0x01
}
}
})
}
Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
{
ADBG ("Tbt:_DSW")
ADBG (Arg0)
ADBG (Arg1)
ADBG (Arg2)
If (LGreaterEqual (Arg1, 0x01))
{
Store (0x00, WKEN) /* \_SB_.PCI0.RP09.WKEN */
Store (0x02, TOFF) /* External reference */
}
ElseIf (LAnd (Arg0, Arg2))
{
Store (0x01, WKEN) /* \_SB_.PCI0.RP09.WKEN */
Store (0x01, TOFF) /* External reference */
}
Else
{
Store (0x00, WKEN) /* \_SB_.PCI0.RP09.WKEN */
Store (0x00, TOFF) /* External reference */
}
}
PowerResource (PXP, 0x00, 0x0000)
{
ADBG ("TBT:PXP")
Method (_STA, 0, NotSerialized) // _STA: Status
{
ADBG ("PSTA")
Return (PSTA ())
}
Method (_ON, 0, NotSerialized) // _ON_: Power On
{
ADBG ("S_ON")
Store (0x01, TRDO) /* External reference */
PON ()
Store (0x00, TRDO) /* External reference */
ADBG ("E_ON")
}
Method (_OFF, 0, NotSerialized) // _OFF: Power Off
{
ADBG ("S_OFF")
Store (0x01, TRD3) /* External reference */
POFF ()
Store (0x00, TRD3) /* External reference */
ADBG ("E_OFF")
}
}
Method (PSTA, 0, NotSerialized)
{
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
{
If (LEqual (\_SB.GGOV (DerefOf (Index (PWRG, 0x02))), DerefOf (Index (PWRG, 0x03
))))
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
{
If (LEqual (\_SB.PCI0.GEXP.GEPS (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02
))), DerefOf (Index (PWRG, 0x03))))
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
}
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
{
If (LEqual (\_SB.GGOV (DerefOf (Index (RSTG, 0x02))), DerefOf (Index (RSTG, 0x03
))))
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
{
If (LEqual (\_SB.PCI0.GEXP.GEPS (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02
))), DerefOf (Index (RSTG, 0x03))))
{
Return (0x01)
}
Else
{
Return (0x00)
}
}
}
Return (0x00)
}
Method (SXEX, 0, Serialized)
{
Store (\MMTB (TBSE), Local7)
OperationRegion (TBDI, SystemMemory, Local7, 0x0550)
Field (TBDI, DWordAcc, NoLock, Preserve)
{
DIVI, 32,
CMDR, 32,
Offset (0x548),
TB2P, 32,
P2TB, 32
}
Store (0x64, Local1)
Store (0x09, P2TB) /* \_SB_.PCI0.RP09.SXEX.P2TB */
While (LGreater (Local1, 0x00))
{
Store (Subtract (Local1, 0x01), Local1)
Store (TB2P, Local2)
If (LEqual (Local2, 0xFFFFFFFF))
{
Return (Zero)
}
If (And (Local2, 0x01))
{
Break
}
Sleep (0x05)
}
Store (0x00, P2TB) /* \_SB_.PCI0.RP09.SXEX.P2TB */
Store (0x01F4, Local1)
While (LGreater (Local1, 0x00))
{
Store (Subtract (Local1, 0x01), Local1)
Store (TB2P, Local2)
If (LEqual (Local2, 0xFFFFFFFF))
{
Return (Zero)
}
If (LNotEqual (DIVI, 0xFFFFFFFF))
{
Break
}
Sleep (0x0A)
}
}
Method (PON, 0, NotSerialized)
{
Store (\MMRP (\TBSE), Local7)
OperationRegion (L23P, SystemMemory, Local7, 0xE4)
Field (L23P, WordAcc, NoLock, Preserve)
{
Offset (0xA4),
PSD0, 2,
Offset (0xE2),
, 2,
L2TE, 1,
L2TR, 1
}
Store (\MMTB (\TBSE), Local6)
OperationRegion (TBDI, SystemMemory, Local6, 0x0550)
Field (TBDI, DWordAcc, NoLock, Preserve)
{
DIVI, 32,
CMDR, 32,
Offset (0xA4),
TBPS, 2,
Offset (0x548),
TB2P, 32,
P2TB, 32
}
If (TBPE)
{
Return (Zero)
}
Store (0x00, TOFF) /* External reference */
Store (0x00, G2SD) /* \_SB_.PCI0.RP09.G2SD */
If (\RTBC)
{
If (LNotEqual (DerefOf (Index (SCLK, 0x00)), 0x00))
{
PCRA (0xDC, 0x100C, Not (DerefOf (Index (SCLK, 0x01))))
}
Sleep (\TBCD)
}
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
{
\_SB.SGOV (DerefOf (Index (PWRG, 0x02)), DerefOf (Index (PWRG, 0x03)))
Store (0x01, TBPE) /* External reference */
Sleep (0x0A)
}
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
{
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02)), DerefOf (
Index (PWRG, 0x03)))
Store (0x01, TBPE) /* External reference */
Sleep (0x0A)
}
}
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
{
\_SB.SPC0 (DerefOf (Index (RSTG, 0x02)), Or (\_SB.GPC0 (DerefOf (Index (RSTG, 0x02
))), 0x0100))
}
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
{
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02)), DerefOf (
Index (RSTG, 0x03)))
}
}
Store (0x00, DPGE) /* External reference */
Store (0x01, L2TR) /* \_SB_.PCI0.RP09.PON_.L2TR */
Sleep (0x10)
Store (0x00, Local0)
While (L2TR)
{
If (LGreater (Local0, 0x04))
{
Break
}
Sleep (0x10)
Increment (Local0)
}
Store (0x01, DPGE) /* External reference */
Store (0x00, Local0)
While (LEqual (LASX, 0x00))
{
If (LGreater (Local0, 0x08))
{
Break
}
Sleep (0x10)
Increment (Local0)
}
Store (0x00, LEDM) /* External reference */
Store (PSD0, Local1)
Store (0x00, PSD0) /* \_SB_.PCI0.RP09.PON_.PSD0 */
Store (0x14, Local2)
While (LGreater (Local2, 0x00))
{
Store (Subtract (Local2, 0x01), Local2)
Store (TB2P, Local3)
If (LNotEqual (Local3, 0xFFFFFFFF))
{
Break
}
Sleep (0x0A)
}
If (LLessEqual (Local2, 0x00)){}
SXEX ()
Store (Local1, PSD0) /* \_SB_.PCI0.RP09.PON_.PSD0 */
}
Method (POFF, 0, NotSerialized)
{
If (LEqual (TOFF, 0x00))
{
Return (Zero)
}
Store (\MMRP (\TBSE), Local7)
OperationRegion (L23P, SystemMemory, Local7, 0xE4)
Field (L23P, WordAcc, NoLock, Preserve)
{
Offset (0xA4),
PSD0, 2,
Offset (0xE2),
, 2,
L2TE, 1,
L2TR, 1
}
Store (\MMTB (TBSE), Local6)
OperationRegion (TBDI, SystemMemory, Local6, 0x0550)
Field (TBDI, DWordAcc, NoLock, Preserve)
{
DIVI, 32,
CMDR, 32,
Offset (0xA4),
TBPS, 2,
Offset (0x548),
TB2P, 32,
P2TB, 32
}
Store (PSD0, Local1)
Store (0x00, PSD0) /* \_SB_.PCI0.RP09.POFF.PSD0 */
Store (P2TB, Local3)
If (LGreater (TOFF, 0x01))
{
Sleep (0x0A)
Store (Local1, PSD0) /* \_SB_.PCI0.RP09.POFF.PSD0 */
Return (Zero)
}
Store (0x00, TOFF) /* External reference */
Store (Local1, PSD0) /* \_SB_.PCI0.RP09.POFF.PSD0 */
Store (0x01, L2TE) /* \_SB_.PCI0.RP09.POFF.L2TE */
Sleep (0x10)
Store (0x00, Local0)
While (L2TE)
{
If (LGreater (Local0, 0x04))
{
Break
}
Sleep (0x10)
Increment (Local0)
}
Store (0x01, LEDM) /* External reference */
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
{
\_SB.SPC0 (DerefOf (Index (RSTG, 0x02)), And (\_SB.GPC0 (DerefOf (Index (RSTG, 0x02
))), 0xFFFFFEFF, Local4))
Sleep (0x0A)
}
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
{
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02)), XOr (
DerefOf (Index (RSTG, 0x03)), 0x01))
Sleep (0x0A)
}
}
If (\RTBC)
{
If (LNotEqual (DerefOf (Index (SCLK, 0x00)), 0x00))
{
PCRO (0xDC, 0x100C, DerefOf (Index (SCLK, 0x01)))
Sleep (0x10)
}
}
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
{
\_SB.SGOV (DerefOf (Index (PWRG, 0x02)), XOr (DerefOf (Index (PWRG, 0x03)),
0x01))
}
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
{
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02)), XOr (
DerefOf (Index (PWRG, 0x03)), 0x01))
}
}
Store (0x00, TBPE) /* External reference */
Store (0x01, LDIS) /* External reference */
Store (0x00, LDIS) /* External reference */
If (WKEN)
{
If (LNotEqual (DerefOf (Index (WAKG, 0x00)), 0x00))
{
If (LEqual (DerefOf (Index (WAKG, 0x00)), 0x01))
{
\_SB.SGOV (DerefOf (Index (WAKG, 0x02)), DerefOf (Index (WAKG, 0x03)))
\_SB.SHPO (DerefOf (Index (WAKG, 0x02)), 0x00)
}
If (LEqual (DerefOf (Index (WAKG, 0x00)), 0x02))
{
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (WAKG, 0x01)), DerefOf (Index (WAKG, 0x02)), DerefOf (
Index (WAKG, 0x03)))
}
}
}
Sleep (\TBOD)
}
Name (_PR0, Package (0x01) // _PR0: Power Resources for D0
{
PXP
})
Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot
{
PXP
})
}
}
}

1223
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-4-ProjSsdt.dsl Normal file
View file

File diff suppressed because it is too large Load diff

1134
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-5-CpuSsdt.dsl Normal file
View file

File diff suppressed because it is too large Load diff

253
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-6-CtdpB.dsl Normal file
View file

@ -0,0 +1,253 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-6-CtdpB.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000056D (1389)
* Revision 0x02
* Checksum 0x55
* OEM ID "LENOVO"
* OEM Table ID "CtdpB"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "CtdpB", 0x00001000)
{
External (_PR_.CPPC, IntObj)
External (_PR_.PR00, DeviceObj)
External (_PR_.PR00.LPSS, PkgObj)
External (_PR_.PR00.TPSS, PkgObj)
External (_PR_.PR01, DeviceObj)
External (_PR_.PR02, DeviceObj)
External (_PR_.PR03, DeviceObj)
External (_PR_.PR04, DeviceObj)
External (_PR_.PR05, DeviceObj)
External (_PR_.PR06, DeviceObj)
External (_PR_.PR07, DeviceObj)
External (_PR_.PR08, DeviceObj)
External (_PR_.PR09, DeviceObj)
External (_PR_.PR10, DeviceObj)
External (_PR_.PR11, DeviceObj)
External (_PR_.PR12, DeviceObj)
External (_PR_.PR13, DeviceObj)
External (_PR_.PR14, DeviceObj)
External (_PR_.PR15, DeviceObj)
External (_SB_.OSCP, IntObj)
External (_SB_.PCI0, DeviceObj)
External (CTPC, UnknownObj)
External (CTPR, UnknownObj)
External (FTPS, UnknownObj)
External (PNHM, FieldUnitObj)
External (PNTF, MethodObj) // 1 Arguments
External (PT0D, UnknownObj)
External (PT1D, UnknownObj)
External (PT2D, UnknownObj)
External (TCNT, FieldUnitObj)
Scope (\_SB.PCI0)
{
OperationRegion (MBAR, SystemMemory, 0xFED15000, 0x1000)
Field (MBAR, ByteAcc, NoLock, Preserve)
{
Offset (0x930),
PTDP, 15,
Offset (0x932),
PMIN, 15,
Offset (0x934),
PMAX, 15,
Offset (0x936),
TMAX, 7,
Offset (0x938),
PWRU, 4,
Offset (0x939),
EGYU, 5,
Offset (0x93A),
TIMU, 4,
Offset (0x958),
Offset (0x95C),
LPMS, 1,
CTNL, 2,
Offset (0x9A0),
PPL1, 15,
PL1E, 1,
, 1,
PL1T, 7,
Offset (0x9A4),
PPL2, 15,
PL2E, 1,
, 1,
PL2T, 7,
Offset (0xF3C),
TARN, 8,
Offset (0xF40),
PTD1, 15,
Offset (0xF42),
TAR1, 8,
Offset (0xF44),
PMX1, 15,
Offset (0xF46),
PMN1, 15,
Offset (0xF48),
PTD2, 15,
Offset (0xF4A),
TAR2, 8,
Offset (0xF4C),
PMX2, 15,
Offset (0xF4E),
PMN2, 15,
Offset (0xF50),
CTCL, 2,
, 29,
CLCK, 1,
TAR, 8
}
Method (CTCU, 0, NotSerialized)
{
Store (PT2D, PPL1) /* \_SB_.PCI0.PPL1 */
Store (One, PL1E) /* \_SB_.PCI0.PL1E */
Store (One, \CTPC) /* External reference */
If (LEqual (Zero, \FTPS))
{
Store (\CTPC, \CTPR) /* External reference */
}
ElseIf (LEqual (\CTPR, \FTPS))
{
Store (\CTPC, \CTPR) /* External reference */
Store (\CTPC, \FTPS) /* External reference */
}
Else
{
Store (\CTPC, \CTPR) /* External reference */
Store (\CTPC, \FTPS) /* External reference */
Increment (\FTPS)
}
\PNTF (0x80)
Subtract (TAR2, One, TAR) /* \_SB_.PCI0.TAR_ */
Store (0x02, CTCL) /* \_SB_.PCI0.CTCL */
}
Method (CTCN, 0, NotSerialized)
{
If (LEqual (CTCL, One))
{
Store (PT0D, PPL1) /* \_SB_.PCI0.PPL1 */
Store (One, PL1E) /* \_SB_.PCI0.PL1E */
NPPC (TARN)
Subtract (TARN, One, TAR) /* \_SB_.PCI0.TAR_ */
Store (Zero, CTCL) /* \_SB_.PCI0.CTCL */
}
ElseIf (LEqual (CTCL, 0x02))
{
Store (Zero, CTCL) /* \_SB_.PCI0.CTCL */
Subtract (TARN, One, TAR) /* \_SB_.PCI0.TAR_ */
NPPC (TARN)
Store (PT0D, PPL1) /* \_SB_.PCI0.PPL1 */
Store (One, PL1E) /* \_SB_.PCI0.PL1E */
}
Else
{
Store (Zero, CTCL) /* \_SB_.PCI0.CTCL */
Subtract (TARN, One, TAR) /* \_SB_.PCI0.TAR_ */
NPPC (TARN)
Store (PT0D, PPL1) /* \_SB_.PCI0.PPL1 */
Store (One, PL1E) /* \_SB_.PCI0.PL1E */
}
}
Method (CTCD, 0, NotSerialized)
{
Store (One, CTCL) /* \_SB_.PCI0.CTCL */
Subtract (TAR1, One, TAR) /* \_SB_.PCI0.TAR_ */
NPPC (TAR1)
Store (PT1D, PPL1) /* \_SB_.PCI0.PPL1 */
Store (One, PL1E) /* \_SB_.PCI0.PL1E */
}
Name (TRAT, Zero)
Name (PRAT, Zero)
Name (TMPI, Zero)
Method (NPPC, 1, Serialized)
{
Store (Arg0, TRAT) /* \_SB_.PCI0.TRAT */
If (CondRefOf (\_PR.PR00._PSS))
{
If (And (\_SB.OSCP, 0x0400))
{
Store (SizeOf (\_PR.PR00.TPSS), TMPI) /* \_SB_.PCI0.TMPI */
}
Else
{
Store (SizeOf (\_PR.PR00.LPSS), TMPI) /* \_SB_.PCI0.TMPI */
}
While (LNotEqual (TMPI, Zero))
{
Decrement (TMPI)
If (And (\_SB.OSCP, 0x0400))
{
Store (DerefOf (Index (DerefOf (Index (\_PR.PR00.TPSS, TMPI)), 0x04)), PRAT) /* \_SB_.PCI0.PRAT */
}
Else
{
Store (DerefOf (Index (DerefOf (Index (\_PR.PR00.LPSS, TMPI)), 0x04)), PRAT) /* \_SB_.PCI0.PRAT */
}
ShiftRight (PRAT, 0x08, PRAT) /* \_SB_.PCI0.PRAT */
If (LGreaterEqual (PRAT, TRAT))
{
Store (TMPI, \CTPC) /* External reference */
If (LEqual (Zero, \FTPS))
{
Store (\CTPC, \CTPR) /* External reference */
}
ElseIf (LEqual (\CTPR, \FTPS))
{
Store (\CTPC, \CTPR) /* External reference */
Store (\CTPC, \FTPS) /* External reference */
}
Else
{
Store (\CTPC, \CTPR) /* External reference */
Store (\CTPC, \FTPS) /* External reference */
Increment (\FTPS)
}
\PNTF (0x80)
Break
}
}
}
}
Method (CLC2, 1, Serialized)
{
And (PNHM, 0x0FFF0FF0, Local0)
Switch (ToInteger (Local0))
{
Case (0x000306C0)
{
Return (Divide (Multiply (Arg0, 0x05), 0x04, ))
}
Case (0x00040650)
{
Return (0xC8)
}
Default
{
Return (Divide (Multiply (Arg0, 0x05), 0x04, ))
}
}
}
}
}

280
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-7-UsbCTabl.dsl Normal file
View file

@ -0,0 +1,280 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-7-UsbCTabl.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000006BF (1727)
* Revision 0x02
* Checksum 0xBC
* OEM ID "LENOVO"
* OEM Table ID "UsbCTabl"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "UsbCTabl", 0x00001000)
{
External (_SB_.PCI0.LPCB.EC__.HKEY.MHPF, MethodObj) // 1 Arguments
External (_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD, MethodObj) // 2 Arguments
External (_SB_.PCI0.XHC_.RHUB, DeviceObj)
External (ADBG, MethodObj) // 1 Arguments
External (OSYS, UnknownObj)
External (TBTS, UnknownObj)
External (UBCB, UnknownObj)
External (USTC, UnknownObj)
External (UTCM, UnknownObj)
External (XDCE, UnknownObj)
Scope (\_SB)
{
Device (UBTC)
{
Name (_HID, EisaId ("USBC000")) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0CA0")) // _CID: Compatible ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "USB Type C") // _DDN: DOS Device Name
Name (_ADR, Zero) // _ADR: Address
Name (CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0x00000000, // Address Base
0x00001000, // Address Length
_Y48)
})
Device (CR01)
{
Name (_ADR, Zero) // _ADR: Address
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USTC, One))
{
Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, One))
}
}
}
Device (CR02)
{
Name (_ADR, One) // _ADR: Address
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USTC, One))
{
Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, 0x02))
}
}
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
CreateDWordField (CRS, \_SB.UBTC._Y48._BAS, CBAS) // _BAS: Base Address
Store (UBCB, CBAS) /* \_SB_.UBTC._CRS.CBAS */
Return (CRS) /* \_SB_.UBTC.CRS_ */
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
If (LAnd (LGreaterEqual (OSYS, 0x07DF), LEqual (TBTS, One)))
{
If (LEqual (USTC, One))
{
Return (0x0F)
}
}
Return (Zero)
}
OperationRegion (USBC, SystemMemory, UBCB, 0x38)
Field (USBC, ByteAcc, Lock, Preserve)
{
VER1, 8,
VER2, 8,
RSV1, 8,
RSV2, 8,
CCI0, 8,
CCI1, 8,
CCI2, 8,
CCI3, 8,
CTL0, 8,
CTL1, 8,
CTL2, 8,
CTL3, 8,
CTL4, 8,
CTL5, 8,
CTL6, 8,
CTL7, 8,
MGI0, 8,
MGI1, 8,
MGI2, 8,
MGI3, 8,
MGI4, 8,
MGI5, 8,
MGI6, 8,
MGI7, 8,
MGI8, 8,
MGI9, 8,
MGIA, 8,
MGIB, 8,
MGIC, 8,
MGID, 8,
MGIE, 8,
MGIF, 8,
MGO0, 8,
MGO1, 8,
MGO2, 8,
MGO3, 8,
MGO4, 8,
MGO5, 8,
MGO6, 8,
MGO7, 8,
MGO8, 8,
MGO9, 8,
MGOA, 8,
MGOB, 8,
MGOC, 8,
MGOD, 8,
MGOE, 8,
MGOF, 8
}
Mutex (UBSY, 0x00)
Method (ECWR, 0, Serialized)
{
ADBG ("ECWR")
Acquire (UBSY, 0xFFFF)
Store (Buffer (0x25){}, Local0)
Store (0x0A, Index (Local0, Zero))
Store (Zero, Index (Local0, One))
Store (0x02, Index (Local0, 0x02))
Store (0x06, Index (Local0, 0x03))
Store (MGO0, Index (Local0, 0x04))
Store (MGO1, Index (Local0, 0x05))
Store (MGO2, Index (Local0, 0x06))
Store (MGO3, Index (Local0, 0x07))
Store (MGO4, Index (Local0, 0x08))
Store (MGO5, Index (Local0, 0x09))
Store (MGO6, Index (Local0, 0x0A))
Store (MGO7, Index (Local0, 0x0B))
Store (MGO8, Index (Local0, 0x0C))
Store (MGO9, Index (Local0, 0x0D))
Store (MGOA, Index (Local0, 0x0E))
Store (MGOB, Index (Local0, 0x0F))
Store (MGOC, Index (Local0, 0x10))
Store (MGOD, Index (Local0, 0x11))
Store (MGOE, Index (Local0, 0x12))
Store (MGOF, Index (Local0, 0x13))
Store (0x10, Index (Local0, 0x24))
\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0)
Store (0x0A, Index (Local0, Zero))
Store (Zero, Index (Local0, One))
Store (0x02, Index (Local0, 0x02))
Store (0x04, Index (Local0, 0x03))
Store (CTL0, Index (Local0, 0x04))
Store (CTL1, Index (Local0, 0x05))
Store (CTL2, Index (Local0, 0x06))
Store (CTL3, Index (Local0, 0x07))
Store (CTL4, Index (Local0, 0x08))
Store (CTL5, Index (Local0, 0x09))
Store (CTL6, Index (Local0, 0x0A))
Store (CTL7, Index (Local0, 0x0B))
Store (0x08, Index (Local0, 0x24))
\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0)
Release (UBSY)
}
Method (ECRD, 0, Serialized)
{
ADBG ("ECRD")
Acquire (UBSY, 0xFFFF)
Store (Buffer (0x25){}, Local0)
Store (0x0B, Index (Local0, Zero))
Store (Zero, Index (Local0, One))
Store (0x02, Index (Local0, 0x02))
Store (0x05, Index (Local0, 0x03))
Store (0x10, Index (Local0, 0x24))
Store (\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0), Local1)
Store (DerefOf (Index (Local1, 0x04)), MGI0) /* \_SB_.UBTC.MGI0 */
Store (DerefOf (Index (Local1, 0x05)), MGI1) /* \_SB_.UBTC.MGI1 */
Store (DerefOf (Index (Local1, 0x06)), MGI2) /* \_SB_.UBTC.MGI2 */
Store (DerefOf (Index (Local1, 0x07)), MGI3) /* \_SB_.UBTC.MGI3 */
Store (DerefOf (Index (Local1, 0x08)), MGI4) /* \_SB_.UBTC.MGI4 */
Store (DerefOf (Index (Local1, 0x09)), MGI5) /* \_SB_.UBTC.MGI5 */
Store (DerefOf (Index (Local1, 0x0A)), MGI6) /* \_SB_.UBTC.MGI6 */
Store (DerefOf (Index (Local1, 0x0B)), MGI7) /* \_SB_.UBTC.MGI7 */
Store (DerefOf (Index (Local1, 0x0C)), MGI8) /* \_SB_.UBTC.MGI8 */
Store (DerefOf (Index (Local1, 0x0D)), MGI9) /* \_SB_.UBTC.MGI9 */
Store (DerefOf (Index (Local1, 0x0E)), MGIA) /* \_SB_.UBTC.MGIA */
Store (DerefOf (Index (Local1, 0x0F)), MGIB) /* \_SB_.UBTC.MGIB */
Store (DerefOf (Index (Local1, 0x10)), MGIC) /* \_SB_.UBTC.MGIC */
Store (DerefOf (Index (Local1, 0x11)), MGID) /* \_SB_.UBTC.MGID */
Store (DerefOf (Index (Local1, 0x12)), MGIE) /* \_SB_.UBTC.MGIE */
Store (DerefOf (Index (Local1, 0x13)), MGIF) /* \_SB_.UBTC.MGIF */
Store (0x0B, Index (Local0, Zero))
Store (Zero, Index (Local0, One))
Store (0x02, Index (Local0, 0x02))
Store (0x03, Index (Local0, 0x03))
Store (0x04, Index (Local0, 0x24))
Store (\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0), Local1)
Store (DerefOf (Index (Local1, 0x04)), CCI0) /* \_SB_.UBTC.CCI0 */
Store (DerefOf (Index (Local1, 0x05)), CCI1) /* \_SB_.UBTC.CCI1 */
Store (DerefOf (Index (Local1, 0x06)), CCI2) /* \_SB_.UBTC.CCI2 */
Store (DerefOf (Index (Local1, 0x07)), CCI3) /* \_SB_.UBTC.CCI3 */
Release (UBSY)
}
Method (NTFY, 0, Serialized)
{
ADBG ("NTFY_EC")
ECRD ()
Sleep (One)
Notify (\_SB.UBTC, 0x80) // Status Change
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If (LEqual (Arg0, ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f")))
{
ADBG (Concatenate ("S_UCSI=", ToHexString (Arg2)))
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x0F // .
})
}
Case (One)
{
ECWR ()
}
Case (0x02)
{
ECRD ()
}
Case (0x03)
{
Return (XDCE) /* External reference */
}
}
ADBG ("E_UCSI")
}
Return (Buffer (One)
{
0x00 // .
})
}
}
}
}

95
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-8-HdaDsp.dsl Normal file
View file

@ -0,0 +1,95 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-8-HdaDsp.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000001D8 (472)
* Revision 0x02
* Checksum 0xFF
* OEM ID "LENOVO"
* OEM Table ID "HdaDsp"
* OEM Revision 0x00000000 (0)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "HdaDsp", 0x00000000)
{
External (_SB_.PCI0.HDAS, DeviceObj)
External (ADBG, MethodObj) // 1 Arguments
External (ADPM, IntObj)
External (AG1H, IntObj)
External (AG1L, IntObj)
External (AG2H, IntObj)
External (AG2L, IntObj)
External (AG3H, IntObj)
External (AG3L, IntObj)
Scope (\_SB.PCI0.HDAS)
{
Method (PPMS, 1, Serialized)
{
If (LEqual (Arg0, ToUUID ("7111001f-d35f-44d9-81d2-7ac685bed3d7")))
{
Store (And (ADPM, 0x2000), Local0)
ADBG ("RkSA:")
ADBG (Local0)
Return (Local0)
}
If (LEqual (Arg0, ToUUID ("7c708106-3aff-40fe-88be-8c999b3f7445")))
{
Store (And (ADPM, 0x04), Local0)
ADBG ("iSSP:")
ADBG (Local0)
Return (Local0)
}
If (LEqual (Arg0, ToUUID ("ec774fa9-28d3-424a-90e4-69f984f1eeb7")))
{
Store (And (ADPM, 0x0100), Local0)
ADBG ("WoV:")
ADBG (Local0)
Return (Local0)
}
If (LEqual (Arg0, ToUUID ("849f0d73-1678-4d57-8c78-61c548253993")))
{
Store (And (ADPM, 0x08), Local0)
ADBG ("Dolby:")
ADBG (Local0)
Return (Local0)
}
If (LEqual (Arg0, ACCG (AG1L, AG1H)))
{
Return (And (ADPM, 0x20000000))
}
If (LEqual (Arg0, ACCG (AG2L, AG2H)))
{
Return (And (ADPM, 0x40000000))
}
If (LEqual (Arg0, ACCG (AG3L, AG3H)))
{
Return (And (ADPM, 0x80000000))
}
Return (Zero)
}
Method (ACCG, 2, NotSerialized)
{
Name (GBUF, Buffer (0x10){})
Concatenate (Arg0, Arg1, GBUF) /* \_SB_.PCI0.HDAS.ACCG.GBUF */
Return (GBUF) /* \_SB_.PCI0.HDAS.ACCG.GBUF */
}
}
}

391
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-9-TbtTypeC.dsl Normal file
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@ -0,0 +1,391 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-9-TbtTypeC.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000590 (1424)
* Revision 0x02
* Checksum 0x32
* OEM ID "LENOVO"
* OEM Table ID "TbtTypeC"
* OEM Revision 0x00000000 (0)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "LENOVO", "TbtTypeC", 0x00000000)
{
External (_SB_.PCI0.RP01.PXSX, DeviceObj)
External (_SB_.PCI0.RP09.PXSX, DeviceObj)
External (TBSE, IntObj)
External (TBTS, IntObj)
External (UPT1, IntObj)
External (UPT2, IntObj)
External (USME, IntObj)
If (LAnd (LEqual (TBTS, One), LEqual (TBSE, One)))
{
Scope (\_SB.PCI0.RP01.PXSX)
{
Name (TUSB, Package (0x02)
{
One,
0x04
})
Device (TBDU)
{
Name (_ADR, 0x00020000) // _ADR: Address
Device (XHC)
{
Name (_ADR, Zero) // _ADR: Address
Method (_PS0, 0, Serialized) // _PS0: Power State 0
{
Sleep (0xC8)
}
Method (_PS3, 0, Serialized) // _PS3: Power State 3
{
Sleep (0xC8)
}
Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Method (TPLD, 2, Serialized)
{
Name (PCKG, Package (0x01)
{
Buffer (0x10){}
})
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
Store (One, REV) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.REV_ */
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
Store (Arg0, VISI) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.VISI */
CreateField (DerefOf (Index (PCKG, Zero)), 0x57, 0x08, GPOS)
Store (Arg1, GPOS) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.GPOS */
CreateField (DerefOf (Index (PCKG, Zero)), 0x4A, 0x04, SHAP)
Store (One, SHAP) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.SHAP */
CreateField (DerefOf (Index (PCKG, Zero)), 0x20, 0x10, WID)
Store (0x08, WID) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.WID_ */
CreateField (DerefOf (Index (PCKG, Zero)), 0x30, 0x10, HGT)
Store (0x03, HGT) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.HGT_ */
Return (PCKG) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TPLD.PCKG */
}
Method (TUPC, 2, Serialized)
{
Name (PCKG, Package (0x04)
{
One,
Zero,
Zero,
Zero
})
Store (Arg0, Index (PCKG, Zero))
Store (Arg1, Index (PCKG, One))
Return (PCKG) /* \_SB_.PCI0.RP01.PXSX.TBDU.XHC_.RHUB.TUPC.PCKG */
}
Device (HS01)
{
Name (_ADR, One) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x08))
}
Else
{
Return (TUPC (Zero, Zero))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, One))
}
Else
{
Return (TPLD (Zero, Zero))
}
}
}
Device (HS02)
{
Name (_ADR, 0x02) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x08))
}
Else
{
Return (TUPC (Zero, Zero))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, 0x02))
}
Else
{
Return (TPLD (Zero, Zero))
}
}
}
Device (SS01)
{
Name (_ADR, 0x03) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x09))
}
Else
{
Return (TUPC (One, 0x0A))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, One))
}
Else
{
Return (TPLD (One, UPT1))
}
}
}
Device (SS02)
{
Name (_ADR, 0x04) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x09))
}
Else
{
Return (TUPC (One, 0x0A))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, 0x02))
}
Else
{
Return (TPLD (One, UPT2))
}
}
}
}
}
}
}
}
If (LAnd (LEqual (TBTS, One), LEqual (TBSE, 0x09)))
{
Scope (\_SB.PCI0.RP09.PXSX)
{
Name (TUSB, Package (0x02)
{
0x03,
0x04
})
Device (TBDU)
{
Name (_ADR, 0x00020000) // _ADR: Address
Device (XHC)
{
Name (_ADR, Zero) // _ADR: Address
Method (_PS0, 0, Serialized) // _PS0: Power State 0
{
Sleep (0xC8)
}
Method (_PS3, 0, Serialized) // _PS3: Power State 3
{
Sleep (0xC8)
}
Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Method (TPLD, 2, Serialized)
{
Name (PCKG, Package (0x01)
{
Buffer (0x10){}
})
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
Store (One, REV) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.REV_ */
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
Store (Arg0, VISI) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.VISI */
CreateField (DerefOf (Index (PCKG, Zero)), 0x57, 0x08, GPOS)
Store (Arg1, GPOS) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.GPOS */
CreateField (DerefOf (Index (PCKG, Zero)), 0x4A, 0x04, SHAP)
Store (One, SHAP) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.SHAP */
CreateField (DerefOf (Index (PCKG, Zero)), 0x20, 0x10, WID)
Store (0x08, WID) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.WID_ */
CreateField (DerefOf (Index (PCKG, Zero)), 0x30, 0x10, HGT)
Store (0x03, HGT) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.HGT_ */
Return (PCKG) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD.PCKG */
}
Method (TUPC, 2, Serialized)
{
Name (PCKG, Package (0x04)
{
One,
Zero,
Zero,
Zero
})
Store (Arg0, Index (PCKG, Zero))
Store (Arg1, Index (PCKG, One))
Return (PCKG) /* \_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TUPC.PCKG */
}
Device (HS01)
{
Name (_ADR, One) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x08))
}
Else
{
Return (TUPC (Zero, Zero))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, One))
}
Else
{
Return (TPLD (Zero, Zero))
}
}
}
Device (HS02)
{
Name (_ADR, 0x02) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x08))
}
Else
{
Return (TUPC (Zero, Zero))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, 0x02))
}
Else
{
Return (TPLD (Zero, Zero))
}
}
}
Device (SS01)
{
Name (_ADR, 0x03) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x09))
}
Else
{
Return (TUPC (One, 0x0A))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, One))
}
Else
{
Return (TPLD (One, UPT1))
}
}
}
Device (SS02)
{
Name (_ADR, 0x04) // _ADR: Address
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
{
If (LEqual (USME, Zero))
{
Return (TUPC (One, 0x09))
}
Else
{
Return (TUPC (One, 0x0A))
}
}
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
{
If (LEqual (USME, Zero))
{
Return (TPLD (One, 0x02))
}
Else
{
Return (TPLD (One, UPT2))
}
}
}
}
}
}
}
}
}

465
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_0-Cpu0Ist.dsl Normal file
View file

@ -0,0 +1,465 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_0-Cpu0Ist.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000005EE (1518)
* Revision 0x02
* Checksum 0x8C
* OEM ID "PmRef"
* OEM Table ID "Cpu0Ist"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Ist", 0x00003000)
{
External (_PR_.CFGD, FieldUnitObj)
External (_PR_.CPPC, FieldUnitObj)
External (_PR_.PR00, DeviceObj)
External (_SB_.OSCP, IntObj)
External (PC00, IntObj)
External (TCNT, FieldUnitObj)
Scope (\_PR.PR00)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.CPPC) /* External reference */
}
Name (_PCT, Package (0x02) // _PCT: Performance Control
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
}
})
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
If (And (\_SB.OSCP, 0x0400))
{
Return (TPSS) /* \_PR_.PR00.TPSS */
}
Else
{
Return (LPSS) /* \_PR_.PR00.LPSS */
}
}
Name (LPSS, Package (0x10)
{
Package (0x06)
{
0x00000835,
0x00003A98,
0x0000000A,
0x0000000A,
0x00002A00,
0x00002A00
},
Package (0x06)
{
0x00000834,
0x00003A98,
0x0000000A,
0x0000000A,
0x00001500,
0x00001500
},
Package (0x06)
{
0x0000076C,
0x00003389,
0x0000000A,
0x0000000A,
0x00001300,
0x00001300
},
Package (0x06)
{
0x00000708,
0x0000301D,
0x0000000A,
0x0000000A,
0x00001200,
0x00001200
},
Package (0x06)
{
0x000006A4,
0x00002CC3,
0x0000000A,
0x0000000A,
0x00001100,
0x00001100
},
Package (0x06)
{
0x00000640,
0x00002A07,
0x0000000A,
0x0000000A,
0x00001000,
0x00001000
},
Package (0x06)
{
0x000005DC,
0x000026D0,
0x0000000A,
0x0000000A,
0x00000F00,
0x00000F00
},
Package (0x06)
{
0x00000578,
0x000023A7,
0x0000000A,
0x0000000A,
0x00000E00,
0x00000E00
},
Package (0x06)
{
0x000004B0,
0x00001E10,
0x0000000A,
0x0000000A,
0x00000C00,
0x00000C00
},
Package (0x06)
{
0x0000044C,
0x00001B19,
0x0000000A,
0x0000000A,
0x00000B00,
0x00000B00
},
Package (0x06)
{
0x000003E8,
0x00001834,
0x0000000A,
0x0000000A,
0x00000A00,
0x00000A00
},
Package (0x06)
{
0x00000320,
0x00001318,
0x0000000A,
0x0000000A,
0x00000800,
0x00000800
},
Package (0x06)
{
0x000002BC,
0x00001061,
0x0000000A,
0x0000000A,
0x00000700,
0x00000700
},
Package (0x06)
{
0x00000258,
0x00000DBA,
0x0000000A,
0x0000000A,
0x00000600,
0x00000600
},
Package (0x06)
{
0x000001F4,
0x00000B22,
0x0000000A,
0x0000000A,
0x00000500,
0x00000500
},
Package (0x06)
{
0x00000190,
0x00000915,
0x0000000A,
0x0000000A,
0x00000400,
0x00000400
}
})
Name (TPSS, Package (0x13)
{
Package (0x06)
{
0x00000835,
0x00003A98,
0x0000000A,
0x0000000A,
0x00002A00,
0x00002A00
},
Package (0x06)
{
0x00000834,
0x00003A98,
0x0000000A,
0x0000000A,
0x00001500,
0x00001500
},
Package (0x06)
{
0x000007D0,
0x00003708,
0x0000000A,
0x0000000A,
0x00001400,
0x00001400
},
Package (0x06)
{
0x0000076C,
0x00003389,
0x0000000A,
0x0000000A,
0x00001300,
0x00001300
},
Package (0x06)
{
0x00000708,
0x0000301D,
0x0000000A,
0x0000000A,
0x00001200,
0x00001200
},
Package (0x06)
{
0x000006A4,
0x00002CC3,
0x0000000A,
0x0000000A,
0x00001100,
0x00001100
},
Package (0x06)
{
0x00000640,
0x00002A07,
0x0000000A,
0x0000000A,
0x00001000,
0x00001000
},
Package (0x06)
{
0x000005DC,
0x000026D0,
0x0000000A,
0x0000000A,
0x00000F00,
0x00000F00
},
Package (0x06)
{
0x00000578,
0x000023A7,
0x0000000A,
0x0000000A,
0x00000E00,
0x00000E00
},
Package (0x06)
{
0x00000514,
0x00002090,
0x0000000A,
0x0000000A,
0x00000D00,
0x00000D00
},
Package (0x06)
{
0x000004B0,
0x00001E10,
0x0000000A,
0x0000000A,
0x00000C00,
0x00000C00
},
Package (0x06)
{
0x0000044C,
0x00001B19,
0x0000000A,
0x0000000A,
0x00000B00,
0x00000B00
},
Package (0x06)
{
0x000003E8,
0x00001834,
0x0000000A,
0x0000000A,
0x00000A00,
0x00000A00
},
Package (0x06)
{
0x00000384,
0x0000155D,
0x0000000A,
0x0000000A,
0x00000900,
0x00000900
},
Package (0x06)
{
0x00000320,
0x00001318,
0x0000000A,
0x0000000A,
0x00000800,
0x00000800
},
Package (0x06)
{
0x000002BC,
0x00001061,
0x0000000A,
0x0000000A,
0x00000700,
0x00000700
},
Package (0x06)
{
0x00000258,
0x00000DBA,
0x0000000A,
0x0000000A,
0x00000600,
0x00000600
},
Package (0x06)
{
0x000001F4,
0x00000B22,
0x0000000A,
0x0000000A,
0x00000500,
0x00000500
},
Package (0x06)
{
0x00000190,
0x00000915,
0x0000000A,
0x0000000A,
0x00000400,
0x00000400
}
})
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR00.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR00.HPSD */
}
Return (SPSD) /* \_PR_.PR00.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
}

930
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_1-ApIst.dsl Normal file
View file

@ -0,0 +1,930 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_1-ApIst.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000D14 (3348)
* Revision 0x02
* Checksum 0x2A
* OEM ID "PmRef"
* OEM Table ID "ApIst"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApIst", 0x00003000)
{
External (_PR_.PR00, DeviceObj)
External (_PR_.PR00._PCT, MethodObj) // 0 Arguments
External (_PR_.PR00._PPC, MethodObj) // 0 Arguments
External (_PR_.PR00._PSS, MethodObj) // 0 Arguments
External (_PR_.PR01, DeviceObj)
External (_PR_.PR02, DeviceObj)
External (_PR_.PR03, DeviceObj)
External (_PR_.PR04, DeviceObj)
External (_PR_.PR05, DeviceObj)
External (_PR_.PR06, DeviceObj)
External (_PR_.PR07, DeviceObj)
External (_PR_.PR08, DeviceObj)
External (_PR_.PR09, DeviceObj)
External (_PR_.PR10, DeviceObj)
External (_PR_.PR11, DeviceObj)
External (_PR_.PR12, DeviceObj)
External (_PR_.PR13, DeviceObj)
External (_PR_.PR14, DeviceObj)
External (_PR_.PR15, DeviceObj)
External (PC00, IntObj)
External (TCNT, FieldUnitObj)
Scope (\_PR.PR01)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR01.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR01.HPSD */
}
Return (SPSD) /* \_PR_.PR01.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR02)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR02.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR02.HPSD */
}
Return (SPSD) /* \_PR_.PR02.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR03)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR03.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR03.HPSD */
}
Return (SPSD) /* \_PR_.PR03.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR04)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR04.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR04.HPSD */
}
Return (SPSD) /* \_PR_.PR04.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR05)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR05.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR05.HPSD */
}
Return (SPSD) /* \_PR_.PR05.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR06)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR06.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR06.HPSD */
}
Return (SPSD) /* \_PR_.PR06.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR07)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR07.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR07.HPSD */
}
Return (SPSD) /* \_PR_.PR07.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR08)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR08.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR08.HPSD */
}
Return (SPSD) /* \_PR_.PR08.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR09)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR09.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR09.HPSD */
}
Return (SPSD) /* \_PR_.PR09.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR10)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR10.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR10.HPSD */
}
Return (SPSD) /* \_PR_.PR10.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR11)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR11.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR11.HPSD */
}
Return (SPSD) /* \_PR_.PR11.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR12)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR12.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR12.HPSD */
}
Return (SPSD) /* \_PR_.PR12.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR13)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR13.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR13.HPSD */
}
Return (SPSD) /* \_PR_.PR13.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR14)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR14.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR14.HPSD */
}
Return (SPSD) /* \_PR_.PR14.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
Scope (\_PR.PR15)
{
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
{
Return (\_PR.PR00._PPC ())
}
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
{
Return (\_PR.PR00._PCT ())
}
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
{
Return (\_PR.PR00._PSS ())
}
Name (PSDF, Zero)
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
{
If (LNot (PSDF))
{
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
Store (Ones, PSDF) /* \_PR_.PR15.PSDF */
}
If (And (PC00, 0x0800))
{
Return (HPSD) /* \_PR_.PR15.HPSD */
}
Return (SPSD) /* \_PR_.PR15.SPSD */
}
Name (HPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFE,
0x80
}
})
Name (SPSD, Package (0x01)
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFC,
0x80
}
})
}
}

259
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_2-Cpu0Cst.dsl Normal file
View file

@ -0,0 +1,259 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_2-Cpu0Cst.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000003FF (1023)
* Revision 0x02
* Checksum 0x11
* OEM ID "PmRef"
* OEM Table ID "Cpu0Cst"
* OEM Revision 0x00003001 (12289)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Cst", 0x00003001)
{
External (_PR_.C3LT, FieldUnitObj)
External (_PR_.C3MW, FieldUnitObj)
External (_PR_.C6LT, FieldUnitObj)
External (_PR_.C6MW, FieldUnitObj)
External (_PR_.C7LT, FieldUnitObj)
External (_PR_.C7MW, FieldUnitObj)
External (_PR_.CDLT, FieldUnitObj)
External (_PR_.CDLV, FieldUnitObj)
External (_PR_.CDMW, FieldUnitObj)
External (_PR_.CDPW, FieldUnitObj)
External (_PR_.CFGD, UnknownObj)
External (_PR_.PR00, DeviceObj)
External (C3LT, UnknownObj)
External (C3MW, UnknownObj)
External (C6LT, UnknownObj)
External (C6MW, UnknownObj)
External (C7LT, UnknownObj)
External (C7MW, UnknownObj)
External (CDLT, UnknownObj)
External (CDLV, UnknownObj)
External (CDMW, UnknownObj)
External (CDPW, UnknownObj)
External (CFGD, UnknownObj)
External (FEMD, UnknownObj)
External (FMBL, UnknownObj)
External (PC00, UnknownObj)
External (PFLV, UnknownObj)
Scope (\_PR.PR00)
{
Name (C1TM, Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
One,
One,
0x03E8
})
Name (C3TM, Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001814, // Address
,)
},
0x02,
Zero,
0x01F4
})
Name (C6TM, Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001815, // Address
,)
},
0x02,
Zero,
0x015E
})
Name (C7TM, Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001816, // Address
,)
},
0x02,
Zero,
0xC8
})
Name (CDTM, Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001816, // Address
,)
},
0x03,
Zero,
Zero
})
Name (MWES, ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
})
Name (AC2V, Zero)
Name (AC3V, Zero)
Name (C3ST, Package (0x04)
{
0x03,
Package (0x01)
{
Zero
},
Package (0x01)
{
Zero
},
Package (0x01)
{
Zero
}
})
Name (C2ST, Package (0x03)
{
0x02,
Package (0x01)
{
Zero
},
Package (0x01)
{
Zero
}
})
Name (C1ST, Package (0x02)
{
One,
Package (0x01)
{
Zero
}
})
Name (CSTF, Zero)
Method (_CST, 0, Serialized) // _CST: C-States
{
If (LNot (CSTF))
{
Store (C3LT, Index (C3TM, 0x02))
Store (C6LT, Index (C6TM, 0x02))
Store (C7LT, Index (C7TM, 0x02))
Store (CDLT, Index (CDTM, 0x02))
Store (CDPW, Index (CDTM, 0x03))
Store (CDLV, Index (DerefOf (Index (CDTM, Zero)), 0x07))
If (LAnd (And (CFGD, 0x0800), And (PC00, 0x0200)))
{
Store (MWES, Index (C1TM, Zero))
Store (MWES, Index (C3TM, Zero))
Store (MWES, Index (C6TM, Zero))
Store (MWES, Index (C7TM, Zero))
Store (MWES, Index (CDTM, Zero))
Store (C3MW, Index (DerefOf (Index (C3TM, Zero)), 0x07))
Store (C6MW, Index (DerefOf (Index (C6TM, Zero)), 0x07))
Store (C7MW, Index (DerefOf (Index (C7TM, Zero)), 0x07))
Store (CDMW, Index (DerefOf (Index (CDTM, Zero)), 0x07))
}
ElseIf (LAnd (And (CFGD, 0x0800), And (PC00, 0x0100)))
{
Store (MWES, Index (C1TM, Zero))
}
Store (Ones, CSTF) /* \_PR_.PR00.CSTF */
}
Store (Zero, AC2V) /* \_PR_.PR00.AC2V */
Store (Zero, AC3V) /* \_PR_.PR00.AC3V */
Store (C1TM, Index (C3ST, One))
If (And (CFGD, 0x20))
{
Store (C7TM, Index (C3ST, 0x02))
Store (Ones, AC2V) /* \_PR_.PR00.AC2V */
}
ElseIf (And (CFGD, 0x10))
{
Store (C6TM, Index (C3ST, 0x02))
Store (Ones, AC2V) /* \_PR_.PR00.AC2V */
}
ElseIf (And (CFGD, 0x08))
{
Store (C3TM, Index (C3ST, 0x02))
Store (Ones, AC2V) /* \_PR_.PR00.AC2V */
}
If (And (CFGD, 0x4000))
{
Store (CDTM, Index (C3ST, 0x03))
Store (Ones, AC3V) /* \_PR_.PR00.AC3V */
}
If (LAnd (AC2V, AC3V))
{
Return (C3ST) /* \_PR_.PR00.C3ST */
}
ElseIf (AC2V)
{
Store (DerefOf (Index (C3ST, One)), Index (C2ST, One))
Store (DerefOf (Index (C3ST, 0x02)), Index (C2ST, 0x02))
Return (C2ST) /* \_PR_.PR00.C2ST */
}
ElseIf (AC3V)
{
Store (DerefOf (Index (C3ST, One)), Index (C2ST, One))
Store (DerefOf (Index (C3ST, 0x03)), Index (C2ST, 0x02))
Store (0x02, Index (DerefOf (Index (C2ST, 0x02)), One))
Return (C2ST) /* \_PR_.PR00.C2ST */
}
Else
{
Store (DerefOf (Index (C3ST, One)), Index (C1ST, One))
Return (C1ST) /* \_PR_.PR00.C1ST */
}
}
}
}

160
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_3-ApCst.dsl Normal file
View file

@ -0,0 +1,160 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_3-ApCst.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000030A (778)
* Revision 0x02
* Checksum 0x93
* OEM ID "PmRef"
* OEM Table ID "ApCst"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApCst", 0x00003000)
{
External (_PR_.PR00._CST, UnknownObj)
External (_PR_.PR01, DeviceObj)
External (_PR_.PR02, DeviceObj)
External (_PR_.PR03, DeviceObj)
External (_PR_.PR04, DeviceObj)
External (_PR_.PR05, DeviceObj)
External (_PR_.PR06, DeviceObj)
External (_PR_.PR07, DeviceObj)
External (_PR_.PR08, DeviceObj)
External (_PR_.PR09, DeviceObj)
External (_PR_.PR10, DeviceObj)
External (_PR_.PR11, DeviceObj)
External (_PR_.PR12, DeviceObj)
External (_PR_.PR13, DeviceObj)
External (_PR_.PR14, DeviceObj)
External (_PR_.PR15, DeviceObj)
Scope (\_PR.PR01)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR02)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR03)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR04)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR05)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR06)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR07)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR08)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR09)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR10)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR11)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR12)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR13)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR14)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
Scope (\_PR.PR15)
{
Method (_CST, 0, NotSerialized) // _CST: C-States
{
Return (\_PR.PR00._CST) /* External reference */
}
}
}

48
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_4-Cpu0Hwp.dsl Normal file
View file

@ -0,0 +1,48 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_4-Cpu0Hwp.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000000BA (186)
* Revision 0x02
* Checksum 0x7D
* OEM ID "PmRef"
* OEM Table ID "Cpu0Hwp"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Hwp", 0x00003000)
{
External (_PR_.CFGD, IntObj)
External (_PR_.HWPA, FieldUnitObj)
External (_PR_.HWPV, IntObj)
External (_PR_.PR00, DeviceObj)
External (_PR_.PR00.CPC2, PkgObj)
External (_PR_.PR00.CPOC, PkgObj)
External (CPC2, IntObj)
External (CPOC, IntObj)
External (TCNT, FieldUnitObj)
Scope (\_PR.PR00)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
If (And (\_PR.CFGD, 0x01000000))
{
Return (CPOC) /* External reference */
}
Else
{
Return (CPC2) /* External reference */
}
}
}
}

161
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_5-ApHwp.dsl Normal file
View file

@ -0,0 +1,161 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_5-ApHwp.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000317 (791)
* Revision 0x02
* Checksum 0x80
* OEM ID "PmRef"
* OEM Table ID "ApHwp"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApHwp", 0x00003000)
{
External (_PR_.PR00, ProcessorObj)
External (_PR_.PR00._CPC, MethodObj) // 0 Arguments
External (_PR_.PR01, ProcessorObj)
External (_PR_.PR02, ProcessorObj)
External (_PR_.PR03, ProcessorObj)
External (_PR_.PR04, ProcessorObj)
External (_PR_.PR05, ProcessorObj)
External (_PR_.PR06, ProcessorObj)
External (_PR_.PR07, ProcessorObj)
External (_PR_.PR08, ProcessorObj)
External (_PR_.PR09, ProcessorObj)
External (_PR_.PR10, ProcessorObj)
External (_PR_.PR11, ProcessorObj)
External (_PR_.PR12, ProcessorObj)
External (_PR_.PR13, ProcessorObj)
External (_PR_.PR14, ProcessorObj)
External (_PR_.PR15, ProcessorObj)
Scope (\_PR.PR01)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR02)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR03)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR04)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR05)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR06)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR07)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR08)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR09)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR10)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR11)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR12)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR13)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR14)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
Scope (\_PR.PR15)
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (\_PR.PR00._CPC ())
}
}
}

176
ACPI/Disassembled ACPI/BIOS-v1.41/SSDT-x5_6-HwpLvt.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190509 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of SSDT-x5_6-HwpLvt.aml, Thu Oct 3 00:56:10 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000628 (1576)
* Revision 0x02
* Checksum 0x85
* OEM ID "PmRef"
* OEM Table ID "HwpLvt"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160527 (538314023)
*/
DefinitionBlock ("", "SSDT", 2, "PmRef", "HwpLvt", 0x00003000)
{
External (_PR_.PR00, DeviceObj)
External (_PR_.PR01, ProcessorObj)
External (_PR_.PR02, ProcessorObj)
External (_PR_.PR03, ProcessorObj)
External (_PR_.PR04, ProcessorObj)
External (_PR_.PR05, ProcessorObj)
External (_PR_.PR06, ProcessorObj)
External (_PR_.PR07, ProcessorObj)
External (_PR_.PR08, ProcessorObj)
External (_PR_.PR09, ProcessorObj)
External (_PR_.PR10, ProcessorObj)
External (_PR_.PR11, ProcessorObj)
External (_PR_.PR12, ProcessorObj)
External (_PR_.PR13, ProcessorObj)
External (_PR_.PR14, ProcessorObj)
External (_PR_.PR15, ProcessorObj)
External (TCNT, FieldUnitObj)
Scope (\_GPE)
{
Method (HLVT, 0, Serialized)
{
Switch (ToInteger (TCNT))
{
Case (0x10)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
Notify (\_PR.PR07, 0x83) // Device-Specific Change
Notify (\_PR.PR08, 0x83) // Device-Specific Change
Notify (\_PR.PR09, 0x83) // Device-Specific Change
Notify (\_PR.PR10, 0x83) // Device-Specific Change
Notify (\_PR.PR11, 0x83) // Device-Specific Change
Notify (\_PR.PR12, 0x83) // Device-Specific Change
Notify (\_PR.PR13, 0x83) // Device-Specific Change
Notify (\_PR.PR14, 0x83) // Device-Specific Change
Notify (\_PR.PR15, 0x83) // Device-Specific Change
}
Case (0x0E)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
Notify (\_PR.PR07, 0x83) // Device-Specific Change
Notify (\_PR.PR08, 0x83) // Device-Specific Change
Notify (\_PR.PR09, 0x83) // Device-Specific Change
Notify (\_PR.PR10, 0x83) // Device-Specific Change
Notify (\_PR.PR11, 0x83) // Device-Specific Change
Notify (\_PR.PR12, 0x83) // Device-Specific Change
Notify (\_PR.PR13, 0x83) // Device-Specific Change
}
Case (0x0C)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
Notify (\_PR.PR07, 0x83) // Device-Specific Change
Notify (\_PR.PR08, 0x83) // Device-Specific Change
Notify (\_PR.PR09, 0x83) // Device-Specific Change
Notify (\_PR.PR10, 0x83) // Device-Specific Change
Notify (\_PR.PR11, 0x83) // Device-Specific Change
}
Case (0x0A)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
Notify (\_PR.PR07, 0x83) // Device-Specific Change
Notify (\_PR.PR08, 0x83) // Device-Specific Change
Notify (\_PR.PR09, 0x83) // Device-Specific Change
}
Case (0x08)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
Notify (\_PR.PR07, 0x83) // Device-Specific Change
}
Case (0x07)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
Notify (\_PR.PR06, 0x83) // Device-Specific Change
}
Case (0x06)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
Notify (\_PR.PR05, 0x83) // Device-Specific Change
}
Case (0x05)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
Notify (\_PR.PR04, 0x83) // Device-Specific Change
}
Case (0x04)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
Notify (\_PR.PR03, 0x83) // Device-Specific Change
}
Case (0x03)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
Notify (\_PR.PR02, 0x83) // Device-Specific Change
}
Case (0x02)
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
Notify (\_PR.PR01, 0x83) // Device-Specific Change
}
Default
{
Notify (\_PR.PR00, 0x83) // Device-Specific Change
}
}
}
}
}

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ACPI/Stock ACPI/BIOS-v1.41/APIC.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/ASF!.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/BATB.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/BGRT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/BOOT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/DBG2.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/DBGP.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/DSDT.aml Executable file
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120
ACPI/Stock ACPI/BIOS-v1.41/DumpLog.txt Executable file
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4:133 2:511 Found UEFI Acpi 2.0 RSDP at 5B5FE014
4:133 0:000 Saving ACPI tables from RSDP 5B5FE014 to EFI\CLOVER\ACPI\origin ...
4:133 0:000 5B5FE014: 'RSD PTR ', Rev: 2 (Acpi 2.0 or newer), Len: 36 -> RSDP.aml
4:141 0:008 (Xsdt: 5B5B2188, Rsdt: 5B5B20C4)
4:141 0:000 5B5B2188: 'XSDT', 'TP-N23', Rev: 1, Len: 276 -> XSDT.aml
4:149 0:008 5B5B20C4: 'RSDT', 'TP-N23', Rev: 1, Len: 156 -> RSDT.aml
4:158 0:009 Tables in Xsdt: 30
4:158 0:000 0. 5B5ED000: 'FACP', 'TP-N23', Rev: 5, Len: 244 -> FACP.aml
4:166 0:007 (Dsdt: 5B5C2000, Facs: 5B546000, XDsdt: 5B5C2000, XFacs: 0)
4:166 0:000 5B5C2000: 'DSDT', 'SKL', Rev: 2, Len: 159172 -> DSDT.aml
4:179 0:013 5B546000: 'FACS', Ver: 2, Len: 64 -> FACS.aml
4:187 0:008 1. 5B5F3000: 'SSDT', 'DptfTabl', Rev: 2, Len: 39346 -> SSDT-0-DptfTabl.aml
4:197 0:009 2. 5B55C000: 'UEFI', 'TP-N23', Rev: 1, Len: 66 -> UEFI.aml
4:205 0:007 3. 5B5EF000: 'SSDT', 'SaSsdt', Rev: 2, Len: 12506 -> SSDT-1-SaSsdt.aml
4:214 0:008 4. 5B5EE000: 'SSDT', 'PerfTune', Rev: 2, Len: 1478 -> SSDT-2-PerfTune.aml
4:223 0:009 5. 5B5EC000: 'HPET', 'TP-N23', Rev: 1, Len: 56 -> HPET.aml
4:231 0:008 6. 5B5EB000: 'APIC', 'TP-N23', Rev: 3, Len: 300 -> APIC.aml
4:239 0:008 7. 5B5EA000: 'MCFG', 'TP-N23', Rev: 1, Len: 60 -> MCFG.aml
4:248 0:008 8. 5B5E9000: 'ECDT', 'TP-N23', Rev: 1, Len: 83 -> ECDT.aml
4:256 0:008 9. 5B5C0000: 'SSDT', 'RVP7Rtd3', Rev: 2, Len: 7453 -> SSDT-3-RVP7Rtd3.aml
4:264 0:008 10. 5B5BE000: 'SSDT', 'ProjSsdt', Rev: 2, Len: 6103 -> SSDT-4-ProjSsdt.aml
4:272 0:008 11. 5B5BD000: 'BOOT', 'TP-N23', Rev: 1, Len: 40 -> BOOT.aml
4:281 0:008 12. 5B5BC000: 'BATB', 'TP-N23', Rev: 2, Len: 74 -> BATB.aml
4:290 0:008 13. 5B5BB000: 'SLIC', 'TP-N23', Rev: 1, Len: 374 -> SLIC.aml
4:298 0:008 14. 5B5B9000: 'SSDT', 'CpuSsdt', Rev: 2, Len: 6062 -> SSDT-5-CpuSsdt.aml (Found hidden SSDT 7 pcs)
4:307 0:009 * 5B51B098: 'SSDT', 'Cpu0Ist', Rev: 2, Len: 1518 53 53 44 54 EE 05 00 00 02 8C 50 6D 52 65 66 00 Internal length = 1518 -> SSDT-x5_0-Cpu0Ist.aml
4:316 0:008 * 5B4A1018: 'SSDT', 'ApIst', Rev: 2, Len: 3348 53 53 44 54 14 0D 00 00 02 2A 50 6D 52 65 66 00 Internal length = 3348 -> SSDT-x5_1-ApIst.aml
4:324 0:008 * 5B4A2698: 'SSDT', 'Cpu0Cst', Rev: 2, Len: 1023 53 53 44 54 FF 03 00 00 02 11 50 6D 52 65 66 00 Internal length = 1023 -> SSDT-x5_2-Cpu0Cst.aml
4:332 0:008 * 5B51B718: 'SSDT', 'ApCst', Rev: 2, Len: 778 53 53 44 54 0A 03 00 00 02 93 50 6D 52 65 66 00 Internal length = 778 -> SSDT-x5_3-ApCst.aml
4:341 0:008 * 5B51BE18: 'SSDT', 'Cpu0Hwp', Rev: 2, Len: 186 53 53 44 54 BA 00 00 00 02 7D 50 6D 52 65 66 00 Internal length = 186 -> SSDT-x5_4-Cpu0Hwp.aml
4:350 0:008 * 5B4A0018: 'SSDT', 'ApHwp', Rev: 2, Len: 791 53 53 44 54 17 03 00 00 02 80 50 6D 52 65 66 00 Internal length = 791 -> SSDT-x5_5-ApHwp.aml
4:358 0:008 * 5B4A2018: 'SSDT', 'HwpLvt', Rev: 2, Len: 1576 53 53 44 54 28 06 00 00 02 85 50 6D 52 65 66 00 Internal length = 1576 -> SSDT-x5_6-HwpLvt.aml
4:366 0:008
4:366 0:000 15. 5B5B8000: 'SSDT', 'CtdpB', Rev: 2, Len: 1389 -> SSDT-6-CtdpB.aml
4:374 0:008 16. 5B5B7000: 'SSDT', 'UsbCTabl', Rev: 2, Len: 1727 -> SSDT-7-UsbCTabl.aml
4:383 0:008 17. 5B5B6000: 'LPIT', 'TP-N23', Rev: 1, Len: 148 -> LPIT.aml
4:391 0:008 18. 5B5B5000: 'WSMT', 'TP-N23', Rev: 1, Len: 40 -> WSMT.aml
4:399 0:008 19. 5B5B4000: 'SSDT', 'HdaDsp', Rev: 2, Len: 472 -> SSDT-8-HdaDsp.aml
4:415 0:015 20. 5B5B3000: 'SSDT', 'TbtTypeC', Rev: 2, Len: 1424 -> SSDT-9-TbtTypeC.aml
4:423 0:007 21. 5B5FD000: 'SSDT', 'Wwan', Rev: 2, Len: 721 -> SSDT-10-Wwan.aml
4:431 0:008 22. 5B5B1000: 'DBGP', 'TP-N23', Rev: 1, Len: 52 -> DBGP.aml
4:439 0:008 23. 5B5B0000: 'DBG2', 'TP-N23', Rev: 0, Len: 84 -> DBG2.aml
4:448 0:008 24. 5B5AF000: 'MSDM', 'TP-N23', Rev: 3, Len: 85 -> MSDM.aml
4:456 0:008 25. 5B5AE000: 'NHLT', 'TP-N23', Rev: 0, Len: 45 -> NHLT.aml
4:464 0:008 26. 5B5AD000: 'ASF!', 'TP-N23', Rev: 32, Len: 160 -> ASF!.aml
4:472 0:008 27. 5B5AC000: 'FPDT', 'TP-N23', Rev: 1, Len: 68 -> FPDT.aml
4:480 0:008 28. 5B534000: 'UEFI', 'TP-N23', Rev: 1, Len: 318 -> UEFI.aml
4:500 0:019 29. 5B5AB000: 'BGRT', 'TP-N23', Rev: 1, Len: 56 -> BGRT.aml
4:508 0:008 Tables in Rsdt: 30
4:508 0:000 0. 5B5ED000: 'FACP', 'TP-N23', Rev: 5, Len: 244
4:508 0:000 (Dsdt: 5B5C2000, Facs: 5B546000, XDsdt: 5B5C2000, XFacs: 0)
4:508 0:000 5B5C2000: 'DSDT', 'SKL', Rev: 2, Len: 159172
4:513 0:005 5B546000: 'FACS', Ver: 2, Len: 64
4:513 0:000 1. 5B5F3000: 'SSDT', 'DptfTabl', Rev: 2, Len: 39346
4:513 0:000 2. 5B55C000: 'UEFI', 'TP-N23', Rev: 1, Len: 66
4:513 0:000 3. 5B5EF000: 'SSDT', 'SaSsdt', Rev: 2, Len: 12506
4:513 0:000 4. 5B5EE000: 'SSDT', 'PerfTune', Rev: 2, Len: 1478
4:513 0:000 5. 5B5EC000: 'HPET', 'TP-N23', Rev: 1, Len: 56
4:513 0:000 6. 5B5EB000: 'APIC', 'TP-N23', Rev: 3, Len: 300
4:513 0:000 7. 5B5EA000: 'MCFG', 'TP-N23', Rev: 1, Len: 60
4:513 0:000 8. 5B5E9000: 'ECDT', 'TP-N23', Rev: 1, Len: 83
4:513 0:000 9. 5B5C0000: 'SSDT', 'RVP7Rtd3', Rev: 2, Len: 7453
4:513 0:000 10. 5B5BE000: 'SSDT', 'ProjSsdt', Rev: 2, Len: 6103
4:513 0:000 11. 5B5BD000: 'BOOT', 'TP-N23', Rev: 1, Len: 40
4:513 0:000 12. 5B5BC000: 'BATB', 'TP-N23', Rev: 2, Len: 74
4:513 0:000 13. 5B5BB000: 'SLIC', 'TP-N23', Rev: 1, Len: 374
4:513 0:000 14. 5B5B9000: 'SSDT', 'CpuSsdt', Rev: 2, Len: 6062
4:513 0:000 15. 5B5B8000: 'SSDT', 'CtdpB', Rev: 2, Len: 1389
4:513 0:000 16. 5B5B7000: 'SSDT', 'UsbCTabl', Rev: 2, Len: 1727
4:513 0:000 17. 5B5B6000: 'LPIT', 'TP-N23', Rev: 1, Len: 148
4:513 0:000 18. 5B5B5000: 'WSMT', 'TP-N23', Rev: 1, Len: 40
4:513 0:000 19. 5B5B4000: 'SSDT', 'HdaDsp', Rev: 2, Len: 472
4:513 0:000 20. 5B5B3000: 'SSDT', 'TbtTypeC', Rev: 2, Len: 1424
4:513 0:000 21. 5B5FD000: 'SSDT', 'Wwan', Rev: 2, Len: 721
4:513 0:000 22. 5B5B1000: 'DBGP', 'TP-N23', Rev: 1, Len: 52
4:513 0:000 23. 5B5B0000: 'DBG2', 'TP-N23', Rev: 0, Len: 84
4:513 0:000 24. 5B5AF000: 'MSDM', 'TP-N23', Rev: 3, Len: 85
4:513 0:000 25. 5B5AE000: 'NHLT', 'TP-N23', Rev: 0, Len: 45
4:513 0:000 26. 5B5AD000: 'ASF!', 'TP-N23', Rev: 32, Len: 160
4:513 0:000 27. 5B5AC000: 'FPDT', 'TP-N23', Rev: 1, Len: 68
4:513 0:000 28. 5B534000: 'UEFI', 'TP-N23', Rev: 1, Len: 318
4:513 0:000 29. 5B5AB000: 'BGRT', 'TP-N23', Rev: 1, Len: 56
4:513 0:000 Found UEFI Acpi 1.0 RSDP at 5B5FE000
4:513 0:000 Printing ACPI tables from RSDP 5B5FE000 ...
4:513 0:000 5B5FE000: 'RSD PTR ', Rev: 0 (Acpi 1.0), Len: 20
4:513 0:000 (Rsdt: 5B5B2000)
4:513 0:000 5B5B2000: 'RSDT', 'TP-N23', Rev: 1, Len: 152
4:513 0:000 Tables in Rsdt: 29
4:513 0:000 0. 5B5ED000: 'FACP', 'TP-N23', Rev: 5, Len: 244
4:513 0:000 (Dsdt: 5B5C2000, Facs: 5B546000, XDsdt: 5B5C2000, XFacs: 0)
4:513 0:000 5B5C2000: 'DSDT', 'SKL', Rev: 2, Len: 159172
4:518 0:005 5B546000: 'FACS', Ver: 2, Len: 64
4:519 0:000 1. 5B5F3000: 'SSDT', 'DptfTabl', Rev: 2, Len: 39346
4:519 0:000 2. 5B55C000: 'UEFI', 'TP-N23', Rev: 1, Len: 66
4:519 0:000 3. 5B5EF000: 'SSDT', 'SaSsdt', Rev: 2, Len: 12506
4:519 0:000 4. 5B5EE000: 'SSDT', 'PerfTune', Rev: 2, Len: 1478
4:519 0:000 5. 5B5EC000: 'HPET', 'TP-N23', Rev: 1, Len: 56
4:519 0:000 6. 5B5EB000: 'APIC', 'TP-N23', Rev: 3, Len: 300
4:519 0:000 7. 5B5EA000: 'MCFG', 'TP-N23', Rev: 1, Len: 60
4:519 0:000 8. 5B5E9000: 'ECDT', 'TP-N23', Rev: 1, Len: 83
4:519 0:000 9. 5B5C0000: 'SSDT', 'RVP7Rtd3', Rev: 2, Len: 7453
4:519 0:000 10. 5B5BE000: 'SSDT', 'ProjSsdt', Rev: 2, Len: 6103
4:519 0:000 11. 5B5BD000: 'BOOT', 'TP-N23', Rev: 1, Len: 40
4:519 0:000 12. 5B5BC000: 'BATB', 'TP-N23', Rev: 2, Len: 74
4:519 0:000 13. 5B5B9000: 'SSDT', 'CpuSsdt', Rev: 2, Len: 6062
4:519 0:000 14. 5B5B8000: 'SSDT', 'CtdpB', Rev: 2, Len: 1389
4:519 0:000 15. 5B5B7000: 'SSDT', 'UsbCTabl', Rev: 2, Len: 1727
4:519 0:000 16. 5B5B6000: 'LPIT', 'TP-N23', Rev: 1, Len: 148
4:519 0:000 17. 5B5B5000: 'WSMT', 'TP-N23', Rev: 1, Len: 40
4:519 0:000 18. 5B5B4000: 'SSDT', 'HdaDsp', Rev: 2, Len: 472
4:519 0:000 19. 5B5B3000: 'SSDT', 'TbtTypeC', Rev: 2, Len: 1424
4:519 0:000 20. 5B5FD000: 'SSDT', 'Wwan', Rev: 2, Len: 721
4:519 0:000 21. 5B5B1000: 'DBGP', 'TP-N23', Rev: 1, Len: 52
4:519 0:000 22. 5B5B0000: 'DBG2', 'TP-N23', Rev: 0, Len: 84
4:519 0:000 23. 5B5AF000: 'MSDM', 'TP-N23', Rev: 3, Len: 85
4:519 0:000 24. 5B5AE000: 'NHLT', 'TP-N23', Rev: 0, Len: 45
4:519 0:000 25. 5B5AD000: 'ASF!', 'TP-N23', Rev: 32, Len: 160
4:519 0:000 26. 5B5AC000: 'FPDT', 'TP-N23', Rev: 1, Len: 68
4:519 0:000 27. 5B534000: 'UEFI', 'TP-N23', Rev: 1, Len: 318
4:519 0:000 28. 5B5AB000: 'BGRT', 'TP-N23', Rev: 1, Len: 56

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ACPI/Stock ACPI/BIOS-v1.41/HPET.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/LPIT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/MCFG.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/MSDM.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/NHLT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/RSDP.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/RSDT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SLIC.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-0-DptfTabl.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-1-SaSsdt.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-10-Wwan.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-2-PerfTune.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-3-RVP7Rtd3.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-4-ProjSsdt.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-5-CpuSsdt.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-6-CtdpB.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-7-UsbCTabl.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-8-HdaDsp.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-9-TbtTypeC.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_0-Cpu0Ist.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_1-ApIst.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_2-Cpu0Cst.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_3-ApCst.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_4-Cpu0Hwp.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_5-ApHwp.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/SSDT-x5_6-HwpLvt.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/UEFI.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/WSMT.aml Executable file
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ACPI/Stock ACPI/BIOS-v1.41/XSDT.aml Executable file
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