mirror of
https://github.com/tylernguyen/x1c6-hackintosh.git
synced 2025-02-05 01:23:14 -06:00
New ACPI Dump, BIOS 1.30
This commit is contained in:
Tyler Nguyen
parent
bd76f50da5
commit
b536dbd128
38 changed files with 50024 additions and 0 deletions
34767
ACPI/Disassembled ACPI files/September - BIOS 1.30/DSDT.dsl
Normal file
34767
ACPI/Disassembled ACPI files/September - BIOS 1.30/DSDT.dsl
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
2832
ACPI/Disassembled ACPI files/September - BIOS 1.30/SSDT-1-SaSsdt.dsl
Normal file
2832
ACPI/Disassembled ACPI files/September - BIOS 1.30/SSDT-1-SaSsdt.dsl
Normal file
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,117 @@
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
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* Copyright (c) 2000 - 2018 Intel Corporation
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*
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* Disassembling to non-symbolic legacy ASL operators
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*
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* Disassembly of SSDT-10-Wwan.aml, Wed Sep 12 21:34:44 2018
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*
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* Original Table Header:
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* Signature "SSDT"
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* Length 0x000002D1 (721)
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* Revision 0x02
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* Checksum 0x26
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* OEM ID "LENOVO"
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* OEM Table ID "Wwan"
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* OEM Revision 0x00000001 (1)
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* Compiler ID "INTL"
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* Compiler Version 0x20160527 (538314023)
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*/
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DefinitionBlock ("", "SSDT", 2, "LENOVO", "Wwan", 0x00000001)
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{
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External (_SB_.GPC0, MethodObj) // 1 Arguments (from opcode)
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External (_SB_.PCI0.GPCB, MethodObj) // 0 Arguments (from opcode)
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External (_SB_.PCI0.RP03, DeviceObj) // (from opcode)
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External (_SB_.PCI0.RP03._ADR, MethodObj) // 0 Arguments (from opcode)
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External (_SB_.PCI0.RP03.PXSX, DeviceObj) // (from opcode)
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External (_SB_.PCI0.RP03.PXSX._ADR, IntObj) // (from opcode)
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External (_SB_.SPC0, MethodObj) // 2 Arguments (from opcode)
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External (NEXP, IntObj) // (from opcode)
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External (WDC2, IntObj) // (from opcode)
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External (WDCT, IntObj) // (from opcode)
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External (WGUR, IntObj) // (from opcode)
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External (WLCT, IntObj) // (from opcode)
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External (WMNS, IntObj) // (from opcode)
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External (WMXS, IntObj) // (from opcode)
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Name (RSTP, Package (0x04)
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{
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Zero,
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Zero,
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Zero,
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Zero
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})
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Scope (\_SB.PCI0.RP03)
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{
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Method (M2PC, 1, Serialized)
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{
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Store (\_SB.PCI0.GPCB (), Local0)
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Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
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Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
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Return (Local0)
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}
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Method (GMIO, 1, Serialized)
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{
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OperationRegion (PXCS, SystemMemory, M2PC (\_SB.PCI0.RP03._ADR ()), 0x20)
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Field (PXCS, AnyAcc, NoLock, Preserve)
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{
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Offset (0x18),
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PBUS, 8,
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SBUS, 8
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}
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Store (\_SB.PCI0.GPCB (), Local0)
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Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
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Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
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Add (Local0, ShiftLeft (SBUS, 0x14), Local0)
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Return (Local0)
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}
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Scope (PXSX)
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{
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Method (_RST, 0, Serialized) // _RST: Device Reset
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{
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OperationRegion (PXCS, SystemMemory, GMIO (\_SB.PCI0.RP03.PXSX._ADR), 0x0480)
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Field (PXCS, AnyAcc, NoLock, Preserve)
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{
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VDID, 16,
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DVID, 16,
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Offset (0x78),
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DCTL, 16,
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DSTS, 16,
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Offset (0x80),
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LCTL, 16,
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LSTS, 16,
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Offset (0x98),
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DCT2, 16,
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Offset (0x148),
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Offset (0x14C),
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MXSL, 16,
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MNSL, 16
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}
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Store (\_SB.GPC0 (\WGUR), Local0)
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And (Local0, 0xFFFFFFFFFFFFFEFF, Local0)
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\_SB.SPC0 (\WGUR, Local0)
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Sleep (0xC8)
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Notify (\_SB.PCI0.RP03.PXSX, One)
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Or (Local0, 0x0100, Local0)
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\_SB.SPC0 (\WGUR, Local0)
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Sleep (0xC8)
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If (LEqual (NEXP, Zero))
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{
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Store (\WDCT, DCTL)
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Store (\WLCT, LCTL)
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Store (\WDC2, DCT2)
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Store (\WMXS, MXSL)
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Store (\WMNS, MNSL)
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}
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Notify (\_SB.PCI0.RP03.PXSX, One)
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}
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}
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}
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}
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@ -0,0 +1,344 @@
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
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* Copyright (c) 2000 - 2018 Intel Corporation
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*
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* Disassembling to non-symbolic legacy ASL operators
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*
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* Disassembly of SSDT-2-PerfTune.aml, Wed Sep 12 21:34:44 2018
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*
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* Original Table Header:
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* Signature "SSDT"
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* Length 0x000005C6 (1478)
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* Revision 0x02
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* Checksum 0x9F
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* OEM ID "LENOVO"
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* OEM Table ID "PerfTune"
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* OEM Revision 0x00001000 (4096)
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* Compiler ID "INTL"
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* Compiler Version 0x20160527 (538314023)
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*/
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DefinitionBlock ("", "SSDT", 2, "LENOVO", "PerfTune", 0x00001000)
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{
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External (_SB_.PCI0.LPCB.H_EC.CFSP, UnknownObj) // (from opcode)
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External (_SB_.PCI0.LPCB.H_EC.DIM0, UnknownObj) // (from opcode)
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External (_SB_.PCI0.LPCB.H_EC.DIM1, UnknownObj) // (from opcode)
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External (_SB_.PCI0.LPCB.H_EC.ECRD, MethodObj) // 1 Arguments (from opcode)
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External (_TZ_.TZ01._TMP, MethodObj) // 0 Arguments (from opcode)
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External (ADBG, MethodObj) // 1 Arguments (from opcode)
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External (DDRF, UnknownObj) // (from opcode)
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External (ECON, IntObj) // (from opcode)
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External (TSOD, IntObj) // (from opcode)
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External (XMPB, UnknownObj) // (from opcode)
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External (XSMI, UnknownObj) // (from opcode)
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External (XTUB, UnknownObj) // (from opcode)
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External (XTUS, UnknownObj) // (from opcode)
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Scope (\_SB)
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{
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Device (PTMD)
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{
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Name (_HID, EisaId ("INT3394")) // _HID: Hardware ID
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Name (_CID, EisaId ("PNP0C02")) // _CID: Compatible ID
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Name (IVER, 0x00010000)
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Name (SIZE, 0x055C)
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Method (GACI, 0, NotSerialized)
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{
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Name (RPKG, Package (0x02){})
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Store (Zero, Index (RPKG, Zero))
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If (LNotEqual (XTUB, Zero))
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{
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ADBG ("XTUB")
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ADBG (XTUB)
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ADBG ("XTUS")
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ADBG (XTUS)
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OperationRegion (XNVS, SystemMemory, XTUB, SIZE)
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Field (XNVS, ByteAcc, NoLock, Preserve)
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{
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XBUF, 10976
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}
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Name (TEMP, Buffer (XTUS){})
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Store (XBUF, TEMP)
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Store (TEMP, Index (RPKG, One))
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}
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Else
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{
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ADBG ("XTUB ZERO")
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Store (Zero, Index (RPKG, One))
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}
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Return (RPKG)
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}
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Method (GDSV, 1, Serialized)
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{
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If (LEqual (Arg0, 0x05))
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{
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Return (Package (0x02)
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{
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Zero,
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Buffer (0x68)
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{
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/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x4C, 0x04, 0x00, 0x00,
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/* 0010 */ 0x02, 0x00, 0x00, 0x00, 0x7E, 0x04, 0x00, 0x00,
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/* 0018 */ 0x03, 0x00, 0x00, 0x00, 0xB0, 0x04, 0x00, 0x00,
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/* 0020 */ 0x04, 0x00, 0x00, 0x00, 0xE2, 0x04, 0x00, 0x00,
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/* 0028 */ 0x05, 0x00, 0x00, 0x00, 0x14, 0x05, 0x00, 0x00,
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/* 0030 */ 0x06, 0x00, 0x00, 0x00, 0x46, 0x05, 0x00, 0x00,
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/* 0038 */ 0x07, 0x00, 0x00, 0x00, 0x78, 0x05, 0x00, 0x00,
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/* 0040 */ 0x08, 0x00, 0x00, 0x00, 0xAA, 0x05, 0x00, 0x00,
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/* 0048 */ 0x09, 0x00, 0x00, 0x00, 0xDC, 0x05, 0x00, 0x00,
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/* 0050 */ 0x0A, 0x00, 0x00, 0x00, 0x0E, 0x06, 0x00, 0x00,
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/* 0058 */ 0x0B, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00,
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/* 0060 */ 0x0C, 0x00, 0x00, 0x00, 0x72, 0x06, 0x00, 0x00
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}
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})
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}
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If (LEqual (Arg0, 0x13))
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{
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ADBG ("DDR MULT")
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If (LEqual (DDRF, One))
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{
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ADBG ("DDR 1")
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Return (Package (0x02)
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{
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Zero,
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Buffer (0x50)
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{
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/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 0008 */ 0x04, 0x00, 0x00, 0x00, 0x2B, 0x04, 0x00, 0x00,
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/* 0010 */ 0x05, 0x00, 0x00, 0x00, 0x35, 0x05, 0x00, 0x00,
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/* 0018 */ 0x06, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00,
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/* 0020 */ 0x07, 0x00, 0x00, 0x00, 0x4B, 0x07, 0x00, 0x00,
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/* 0028 */ 0x08, 0x00, 0x00, 0x00, 0x55, 0x08, 0x00, 0x00,
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/* 0030 */ 0x09, 0x00, 0x00, 0x00, 0x60, 0x09, 0x00, 0x00,
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/* 0038 */ 0x0A, 0x00, 0x00, 0x00, 0x6B, 0x0A, 0x00, 0x00,
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/* 0040 */ 0x0B, 0x00, 0x00, 0x00, 0x75, 0x0B, 0x00, 0x00,
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/* 0048 */ 0x0C, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00
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}
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})
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}
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Else
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{
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ADBG ("DDR ELSE")
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Return (Package (0x02)
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{
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Zero,
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Buffer (0x68)
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{
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/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 0008 */ 0x05, 0x00, 0x00, 0x00, 0x2B, 0x04, 0x00, 0x00,
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/* 0010 */ 0x06, 0x00, 0x00, 0x00, 0xB0, 0x04, 0x00, 0x00,
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/* 0018 */ 0x07, 0x00, 0x00, 0x00, 0x78, 0x05, 0x00, 0x00,
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/* 0020 */ 0x08, 0x00, 0x00, 0x00, 0x40, 0x06, 0x00, 0x00,
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/* 0028 */ 0x09, 0x00, 0x00, 0x00, 0x08, 0x07, 0x00, 0x00,
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/* 0030 */ 0x0A, 0x00, 0x00, 0x00, 0xD0, 0x07, 0x00, 0x00,
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/* 0038 */ 0x0B, 0x00, 0x00, 0x00, 0x98, 0x08, 0x00, 0x00,
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/* 0040 */ 0x0C, 0x00, 0x00, 0x00, 0x60, 0x09, 0x00, 0x00,
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/* 0048 */ 0x0D, 0x00, 0x00, 0x00, 0x28, 0x0A, 0x00, 0x00,
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/* 0050 */ 0x0E, 0x00, 0x00, 0x00, 0xF0, 0x0A, 0x00, 0x00,
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/* 0058 */ 0x0F, 0x00, 0x00, 0x00, 0xB8, 0x0B, 0x00, 0x00,
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/* 0060 */ 0x10, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00
|
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}
|
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})
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}
|
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|
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ADBG ("DDR EXIT")
|
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}
|
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|
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If (LEqual (Arg0, 0x0B))
|
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{
|
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Return (Package (0x02)
|
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{
|
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Zero,
|
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Buffer (0x60)
|
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{
|
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/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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/* 0008 */ 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
|
||||
/* 0010 */ 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00,
|
||||
/* 0018 */ 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00,
|
||||
/* 0020 */ 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
/* 0028 */ 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00,
|
||||
/* 0030 */ 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
|
||||
/* 0038 */ 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,
|
||||
/* 0040 */ 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
|
||||
/* 0048 */ 0x12, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
/* 0050 */ 0x14, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00,
|
||||
/* 0058 */ 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x49))
|
||||
{
|
||||
Return (Package (0x02)
|
||||
{
|
||||
Zero,
|
||||
Buffer (0x18)
|
||||
{
|
||||
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00,
|
||||
/* 0010 */ 0x02, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Return (Package (0x01)
|
||||
{
|
||||
One
|
||||
})
|
||||
}
|
||||
|
||||
Method (GXDV, 1, Serialized)
|
||||
{
|
||||
If (LNotEqual (XMPB, Zero))
|
||||
{
|
||||
OperationRegion (XMPN, SystemMemory, XMPB, SIZE)
|
||||
Field (XMPN, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
XMP1, 576,
|
||||
XMP2, 576
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, One))
|
||||
{
|
||||
Name (XP_1, Package (0x02){})
|
||||
Store (Zero, Index (XP_1, Zero))
|
||||
Store (XMP1, Index (XP_1, One))
|
||||
Return (XP_1)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x02))
|
||||
{
|
||||
Name (XP_2, Package (0x02){})
|
||||
Store (Zero, Index (XP_2, Zero))
|
||||
Store (XMP2, Index (XP_2, One))
|
||||
Return (XP_2)
|
||||
}
|
||||
}
|
||||
|
||||
Return (Package (0x01)
|
||||
{
|
||||
One
|
||||
})
|
||||
}
|
||||
|
||||
Method (GSCV, 0, NotSerialized)
|
||||
{
|
||||
Return (Package (0x01)
|
||||
{
|
||||
0x72
|
||||
})
|
||||
}
|
||||
|
||||
Method (GSCB, 0, NotSerialized)
|
||||
{
|
||||
Return (XSMI)
|
||||
}
|
||||
|
||||
Method (CDRD, 1, Serialized)
|
||||
{
|
||||
Return (Package (0x01)
|
||||
{
|
||||
One
|
||||
})
|
||||
}
|
||||
|
||||
Method (CDWR, 2, Serialized)
|
||||
{
|
||||
Return (One)
|
||||
}
|
||||
|
||||
Name (RPMV, Package (0x04)
|
||||
{
|
||||
One,
|
||||
0x07,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Name (TMP1, Package (0x0C)
|
||||
{
|
||||
One,
|
||||
0x02,
|
||||
Zero,
|
||||
Zero,
|
||||
0x05,
|
||||
0x04,
|
||||
Zero,
|
||||
Zero,
|
||||
0x06,
|
||||
0x05,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Name (TMP2, Package (0x08)
|
||||
{
|
||||
One,
|
||||
0x02,
|
||||
Zero,
|
||||
Zero,
|
||||
0x05,
|
||||
0x04,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Name (TMP3, Package (0x04)
|
||||
{
|
||||
One,
|
||||
0x02,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Method (TSDD, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (XTUS, Zero))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
If (\ECON)
|
||||
{
|
||||
If (\TSOD)
|
||||
{
|
||||
Store (\_TZ.TZ01._TMP (), Index (TMP1, 0x02))
|
||||
Return (TMP1)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (\_TZ.TZ01._TMP (), Index (TMP2, 0x02))
|
||||
Return (TMP2)
|
||||
}
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (\_TZ.TZ01._TMP (), Index (TMP3, 0x02))
|
||||
Return (TMP3)
|
||||
}
|
||||
}
|
||||
|
||||
Method (FSDD, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (XTUS, Zero))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
If (\ECON)
|
||||
{
|
||||
Store (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.CFSP)), Index (RPMV, 0x02))
|
||||
}
|
||||
|
||||
Return (RPMV)
|
||||
}
|
||||
|
||||
Method (SDSP, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0A)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,759 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-3-RVP7Rtd3.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x00001C9C (7324)
|
||||
* Revision 0x02
|
||||
* Checksum 0x38
|
||||
* OEM ID "LENOVO"
|
||||
* OEM Table ID "RVP7Rtd3"
|
||||
* OEM Revision 0x00001000 (4096)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "LENOVO", "RVP7Rtd3", 0x00001000)
|
||||
{
|
||||
External (_SB_.GGOV, MethodObj) // 1 Arguments (from opcode)
|
||||
External (_SB_.GPC0, MethodObj) // 1 Arguments (from opcode)
|
||||
External (_SB_.OSCO, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.GEXP, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.GEXP.GEPS, MethodObj) // 2 Arguments (from opcode)
|
||||
External (_SB_.PCI0.GEXP.SGEP, MethodObj) // 3 Arguments (from opcode)
|
||||
External (_SB_.PCI0.GLAN, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.I2C0, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.I2C0.TPD0, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.I2C1, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.I2C1.TPL1, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.LPCB.H_EC.ECAV, IntObj) // (from opcode)
|
||||
External (_SB_.PCI0.LPCB.H_EC.SPT2, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP01.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP02.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP03.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP04.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP05.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP06.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP07.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP08.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.PCRA, MethodObj) // 3 Arguments (from opcode)
|
||||
External (_SB_.PCI0.RP09.PCRO, MethodObj) // 3 Arguments (from opcode)
|
||||
External (_SB_.PCI0.RP09.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP10.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP11.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP12.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP13.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP14.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP15.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP16.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP17.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP18.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP19.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.D3HT, FieldUnitObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.DPGE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.L23E, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.L23R, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.LASX, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.LDIS, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.LEDM, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP20.VDID, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT0, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT1, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT2, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT3, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT4, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.SAT0.PRT5, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XDCI, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XDCI.D0I3, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.XDCI.XDCB, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.MEMB, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.PMEE, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.PMES, UnknownObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB.HS01, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB.HS02, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB.SS01, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB.SS02, DeviceObj) // (from opcode)
|
||||
External (_SB_.SGOV, MethodObj) // 2 Arguments (from opcode)
|
||||
External (_SB_.SHPO, MethodObj) // 2 Arguments (from opcode)
|
||||
External (_SB_.SPC0, MethodObj) // 2 Arguments (from opcode)
|
||||
External (ADBG, MethodObj) // 1 Arguments (from opcode)
|
||||
External (AUDD, FieldUnitObj) // (from opcode)
|
||||
External (DVID, UnknownObj) // (from opcode)
|
||||
External (ECON, IntObj) // (from opcode)
|
||||
External (GBEP, UnknownObj) // (from opcode)
|
||||
External (I20D, FieldUnitObj) // (from opcode)
|
||||
External (I21D, FieldUnitObj) // (from opcode)
|
||||
External (IC0D, FieldUnitObj) // (from opcode)
|
||||
External (IC1D, FieldUnitObj) // (from opcode)
|
||||
External (IC1S, FieldUnitObj) // (from opcode)
|
||||
External (MMRP, MethodObj) // 1 Arguments (from opcode)
|
||||
External (MMTB, MethodObj) // 1 Arguments (from opcode)
|
||||
External (OSYS, UnknownObj) // (from opcode)
|
||||
External (PCHG, UnknownObj) // (from opcode)
|
||||
External (PCHS, UnknownObj) // (from opcode)
|
||||
External (PEP0, UnknownObj) // (from opcode)
|
||||
External (PEP3, UnknownObj) // (from opcode)
|
||||
External (RCG0, IntObj) // (from opcode)
|
||||
External (RCG1, IntObj) // (from opcode)
|
||||
External (RIC0, FieldUnitObj) // (from opcode)
|
||||
External (RTBC, IntObj) // (from opcode)
|
||||
External (RTBT, IntObj) // (from opcode)
|
||||
External (RTD3, IntObj) // (from opcode)
|
||||
External (S0ID, UnknownObj) // (from opcode)
|
||||
External (SDS0, FieldUnitObj) // (from opcode)
|
||||
External (SDS1, FieldUnitObj) // (from opcode)
|
||||
External (SGMD, UnknownObj) // (from opcode)
|
||||
External (SHSB, FieldUnitObj) // (from opcode)
|
||||
External (SPST, IntObj) // (from opcode)
|
||||
External (TBCD, IntObj) // (from opcode)
|
||||
External (TBHR, IntObj) // (from opcode)
|
||||
External (TBOD, IntObj) // (from opcode)
|
||||
External (TBPE, IntObj) // (from opcode)
|
||||
External (TBRP, IntObj) // (from opcode)
|
||||
External (TBSE, IntObj) // (from opcode)
|
||||
External (TBTS, IntObj) // (from opcode)
|
||||
External (TOFF, IntObj) // (from opcode)
|
||||
External (TRD3, IntObj) // (from opcode)
|
||||
External (TRDO, IntObj) // (from opcode)
|
||||
External (UAMS, UnknownObj) // (from opcode)
|
||||
External (VRRD, FieldUnitObj) // (from opcode)
|
||||
External (VRSD, FieldUnitObj) // (from opcode)
|
||||
External (XDST, IntObj) // (from opcode)
|
||||
External (XHPR, UnknownObj) // (from opcode)
|
||||
|
||||
If (LAnd (LEqual (\RTBT, 0x01), LEqual (\TBTS, 0x01)))
|
||||
{
|
||||
Scope (\_SB.PCI0.RP09)
|
||||
{
|
||||
Name (SLOT, 0x09)
|
||||
ADBG ("Rvp7Rtd3:Slot:")
|
||||
ADBG (SLOT)
|
||||
Name (RSTG, Package (0x04)
|
||||
{
|
||||
0x01,
|
||||
0x00,
|
||||
0x02060006,
|
||||
0x01
|
||||
})
|
||||
Name (PWRG, Package (0x04)
|
||||
{
|
||||
0x01,
|
||||
0x00,
|
||||
0x02060004,
|
||||
0x01
|
||||
})
|
||||
Name (WAKG, Package (0x04)
|
||||
{
|
||||
0x01,
|
||||
0x00,
|
||||
0x02060007,
|
||||
0x00
|
||||
})
|
||||
Name (SCLK, Package (0x03)
|
||||
{
|
||||
0x01,
|
||||
0x20,
|
||||
0x00
|
||||
})
|
||||
Name (G2SD, 0x00)
|
||||
Name (WKEN, 0x00)
|
||||
Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State
|
||||
{
|
||||
Return (0x04)
|
||||
}
|
||||
|
||||
Method (_DSD, 0, NotSerialized) // _DSD: Device-Specific Data
|
||||
{
|
||||
ADBG ("Tbt:_DSD")
|
||||
Return (Package (0x02)
|
||||
{
|
||||
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
|
||||
Package (0x01)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"HotPlugSupportInD3",
|
||||
0x01
|
||||
}
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
|
||||
{
|
||||
ADBG ("Tbt:_DSW")
|
||||
ADBG (Arg0)
|
||||
ADBG (Arg1)
|
||||
ADBG (Arg2)
|
||||
If (LGreaterEqual (Arg1, 0x01))
|
||||
{
|
||||
Store (0x00, WKEN)
|
||||
Store (0x02, TOFF)
|
||||
}
|
||||
ElseIf (LAnd (Arg0, Arg2))
|
||||
{
|
||||
Store (0x01, WKEN)
|
||||
Store (0x01, TOFF)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (0x00, WKEN)
|
||||
Store (0x00, TOFF)
|
||||
}
|
||||
}
|
||||
|
||||
PowerResource (PXP, 0x00, 0x0000)
|
||||
{
|
||||
ADBG ("TBT:PXP")
|
||||
Method (_STA, 0, NotSerialized) // _STA: Status
|
||||
{
|
||||
ADBG ("PSTA")
|
||||
Return (PSTA ())
|
||||
}
|
||||
|
||||
Method (_ON, 0, NotSerialized) // _ON_: Power On
|
||||
{
|
||||
ADBG ("S_ON")
|
||||
Store (0x01, TRDO)
|
||||
PON ()
|
||||
Store (0x00, TRDO)
|
||||
ADBG ("E_ON")
|
||||
}
|
||||
|
||||
Method (_OFF, 0, NotSerialized) // _OFF: Power Off
|
||||
{
|
||||
ADBG ("S_OFF")
|
||||
Store (0x01, TRD3)
|
||||
POFF ()
|
||||
Store (0x00, TRD3)
|
||||
ADBG ("E_OFF")
|
||||
}
|
||||
}
|
||||
|
||||
Method (PSTA, 0, NotSerialized)
|
||||
{
|
||||
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
|
||||
{
|
||||
If (LEqual (\_SB.GGOV (DerefOf (Index (PWRG, 0x02))), DerefOf (Index (PWRG, 0x03))))
|
||||
{
|
||||
Return (0x01)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
|
||||
{
|
||||
If (LEqual (\_SB.PCI0.GEXP.GEPS (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02))), DerefOf (Index (PWRG, 0x03))))
|
||||
{
|
||||
Return (0x01)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
|
||||
{
|
||||
If (LEqual (\_SB.GGOV (DerefOf (Index (RSTG, 0x02))), DerefOf (Index (RSTG, 0x03))))
|
||||
{
|
||||
Return (0x01)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
|
||||
{
|
||||
If (LEqual (\_SB.PCI0.GEXP.GEPS (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02))), DerefOf (Index (RSTG, 0x03))))
|
||||
{
|
||||
Return (0x01)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Return (0x00)
|
||||
}
|
||||
|
||||
Method (SXEX, 0, Serialized)
|
||||
{
|
||||
Store (\MMTB (TBSE), Local7)
|
||||
OperationRegion (TBDI, SystemMemory, Local7, 0x0550)
|
||||
Field (TBDI, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
DIVI, 32,
|
||||
CMDR, 32,
|
||||
Offset (0x548),
|
||||
TB2P, 32,
|
||||
P2TB, 32
|
||||
}
|
||||
|
||||
Store (0x64, Local1)
|
||||
Store (0x09, P2TB)
|
||||
While (LGreater (Local1, 0x00))
|
||||
{
|
||||
Store (Subtract (Local1, 0x01), Local1)
|
||||
Store (TB2P, Local2)
|
||||
If (LEqual (Local2, 0xFFFFFFFF))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
If (And (Local2, 0x01))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x05)
|
||||
}
|
||||
|
||||
Store (0x00, P2TB)
|
||||
Store (0x01F4, Local1)
|
||||
While (LGreater (Local1, 0x00))
|
||||
{
|
||||
Store (Subtract (Local1, 0x01), Local1)
|
||||
Store (TB2P, Local2)
|
||||
If (LEqual (Local2, 0xFFFFFFFF))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
If (LNotEqual (DIVI, 0xFFFFFFFF))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x0A)
|
||||
}
|
||||
}
|
||||
|
||||
Method (PON, 0, NotSerialized)
|
||||
{
|
||||
Store (\MMRP (\TBSE), Local7)
|
||||
OperationRegion (L23P, SystemMemory, Local7, 0xE4)
|
||||
Field (L23P, WordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xA4),
|
||||
PSD0, 2,
|
||||
Offset (0xE2),
|
||||
, 2,
|
||||
L2TE, 1,
|
||||
L2TR, 1
|
||||
}
|
||||
|
||||
Store (\MMTB (\TBSE), Local6)
|
||||
OperationRegion (TBDI, SystemMemory, Local6, 0x0550)
|
||||
Field (TBDI, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
DIVI, 32,
|
||||
CMDR, 32,
|
||||
Offset (0xA4),
|
||||
TBPS, 2,
|
||||
Offset (0x548),
|
||||
TB2P, 32,
|
||||
P2TB, 32
|
||||
}
|
||||
|
||||
If (TBPE)
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Store (0x00, TOFF)
|
||||
Store (0x00, G2SD)
|
||||
If (\RTBC)
|
||||
{
|
||||
If (LNotEqual (DerefOf (Index (SCLK, 0x00)), 0x00))
|
||||
{
|
||||
PCRA (0xDC, 0x100C, Not (DerefOf (Index (SCLK, 0x01))))
|
||||
}
|
||||
|
||||
Sleep (\TBCD)
|
||||
}
|
||||
|
||||
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
|
||||
{
|
||||
\_SB.SGOV (DerefOf (Index (PWRG, 0x02)), DerefOf (Index (PWRG, 0x03)))
|
||||
Store (0x01, TBPE)
|
||||
Sleep (0x0A)
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
|
||||
{
|
||||
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02)), DerefOf (Index (PWRG, 0x03)))
|
||||
Store (0x01, TBPE)
|
||||
Sleep (0x0A)
|
||||
}
|
||||
}
|
||||
|
||||
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
|
||||
{
|
||||
\_SB.SPC0 (DerefOf (Index (RSTG, 0x02)), Or (\_SB.GPC0 (DerefOf (Index (RSTG, 0x02))), 0x0100))
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
|
||||
{
|
||||
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02)), DerefOf (Index (RSTG, 0x03)))
|
||||
}
|
||||
}
|
||||
|
||||
Store (0x00, DPGE)
|
||||
Store (0x01, L2TR)
|
||||
Sleep (0x10)
|
||||
Store (0x00, Local0)
|
||||
While (L2TR)
|
||||
{
|
||||
If (LGreater (Local0, 0x04))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x10)
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
Store (0x01, DPGE)
|
||||
Store (0x00, Local0)
|
||||
While (LEqual (LASX, 0x00))
|
||||
{
|
||||
If (LGreater (Local0, 0x08))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x10)
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
Store (0x00, LEDM)
|
||||
Store (PSD0, Local1)
|
||||
Store (0x00, PSD0)
|
||||
Store (0x14, Local2)
|
||||
While (LGreater (Local2, 0x00))
|
||||
{
|
||||
Store (Subtract (Local2, 0x01), Local2)
|
||||
Store (TB2P, Local3)
|
||||
If (LNotEqual (Local3, 0xFFFFFFFF))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x0A)
|
||||
}
|
||||
|
||||
If (LLessEqual (Local2, 0x00)){}
|
||||
SXEX ()
|
||||
Store (Local1, PSD0)
|
||||
}
|
||||
|
||||
Method (POFF, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (TOFF, 0x00))
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Store (\MMRP (\TBSE), Local7)
|
||||
OperationRegion (L23P, SystemMemory, Local7, 0xE4)
|
||||
Field (L23P, WordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xA4),
|
||||
PSD0, 2,
|
||||
Offset (0xE2),
|
||||
, 2,
|
||||
L2TE, 1,
|
||||
L2TR, 1
|
||||
}
|
||||
|
||||
Store (\MMTB (TBSE), Local6)
|
||||
OperationRegion (TBDI, SystemMemory, Local6, 0x0550)
|
||||
Field (TBDI, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
DIVI, 32,
|
||||
CMDR, 32,
|
||||
Offset (0xA4),
|
||||
TBPS, 2,
|
||||
Offset (0x548),
|
||||
TB2P, 32,
|
||||
P2TB, 32
|
||||
}
|
||||
|
||||
Store (PSD0, Local1)
|
||||
Store (0x00, PSD0)
|
||||
Store (P2TB, Local3)
|
||||
If (LGreater (TOFF, 0x01))
|
||||
{
|
||||
Sleep (0x0A)
|
||||
Store (Local1, PSD0)
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Store (0x00, TOFF)
|
||||
Store (Local1, PSD0)
|
||||
Store (0x01, L2TE)
|
||||
Sleep (0x10)
|
||||
Store (0x00, Local0)
|
||||
While (L2TE)
|
||||
{
|
||||
If (LGreater (Local0, 0x04))
|
||||
{
|
||||
Break
|
||||
}
|
||||
|
||||
Sleep (0x10)
|
||||
Increment (Local0)
|
||||
}
|
||||
|
||||
Store (0x01, LEDM)
|
||||
If (LNotEqual (DerefOf (Index (RSTG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x01))
|
||||
{
|
||||
\_SB.SPC0 (DerefOf (Index (RSTG, 0x02)), And (\_SB.GPC0 (DerefOf (Index (RSTG, 0x02))), 0xFFFFFEFF, Local4))
|
||||
Sleep (0x0A)
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (RSTG, 0x00)), 0x02))
|
||||
{
|
||||
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (RSTG, 0x01)), DerefOf (Index (RSTG, 0x02)), XOr (DerefOf (Index (RSTG, 0x03)), 0x01))
|
||||
Sleep (0x0A)
|
||||
}
|
||||
}
|
||||
|
||||
If (\RTBC)
|
||||
{
|
||||
If (LNotEqual (DerefOf (Index (SCLK, 0x00)), 0x00))
|
||||
{
|
||||
PCRO (0xDC, 0x100C, DerefOf (Index (SCLK, 0x01)))
|
||||
Sleep (0x10)
|
||||
}
|
||||
}
|
||||
|
||||
If (LNotEqual (DerefOf (Index (PWRG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x01))
|
||||
{
|
||||
\_SB.SGOV (DerefOf (Index (PWRG, 0x02)), XOr (DerefOf (Index (PWRG, 0x03)), 0x01))
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (PWRG, 0x00)), 0x02))
|
||||
{
|
||||
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (PWRG, 0x01)), DerefOf (Index (PWRG, 0x02)), XOr (DerefOf (Index (PWRG, 0x03)), 0x01))
|
||||
}
|
||||
}
|
||||
|
||||
Store (0x00, TBPE)
|
||||
Store (0x01, LDIS)
|
||||
Store (0x00, LDIS)
|
||||
If (WKEN)
|
||||
{
|
||||
If (LNotEqual (DerefOf (Index (WAKG, 0x00)), 0x00))
|
||||
{
|
||||
If (LEqual (DerefOf (Index (WAKG, 0x00)), 0x01))
|
||||
{
|
||||
\_SB.SGOV (DerefOf (Index (WAKG, 0x02)), DerefOf (Index (WAKG, 0x03)))
|
||||
\_SB.SHPO (DerefOf (Index (WAKG, 0x02)), 0x00)
|
||||
}
|
||||
|
||||
If (LEqual (DerefOf (Index (WAKG, 0x00)), 0x02))
|
||||
{
|
||||
\_SB.PCI0.GEXP.SGEP (DerefOf (Index (WAKG, 0x01)), DerefOf (Index (WAKG, 0x02)), DerefOf (Index (WAKG, 0x03)))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Sleep (\TBOD)
|
||||
}
|
||||
|
||||
Name (_PR0, Package (0x01) // _PR0: Power Resources for D0
|
||||
{
|
||||
PXP
|
||||
})
|
||||
Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot
|
||||
{
|
||||
PXP
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,253 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-6-CtdpB.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x0000056D (1389)
|
||||
* Revision 0x02
|
||||
* Checksum 0x55
|
||||
* OEM ID "LENOVO"
|
||||
* OEM Table ID "CtdpB"
|
||||
* OEM Revision 0x00001000 (4096)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "LENOVO", "CtdpB", 0x00001000)
|
||||
{
|
||||
External (_PR_.CPPC, IntObj) // (from opcode)
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR00.LPSS, PkgObj) // (from opcode)
|
||||
External (_PR_.PR00.TPSS, PkgObj) // (from opcode)
|
||||
External (_PR_.PR01, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR02, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR03, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR04, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR05, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR06, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR07, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR08, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR09, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR10, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR11, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR12, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR13, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR14, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR15, DeviceObj) // (from opcode)
|
||||
External (_SB_.OSCP, IntObj) // (from opcode)
|
||||
External (_SB_.PCI0, DeviceObj) // (from opcode)
|
||||
External (CTPC, UnknownObj) // (from opcode)
|
||||
External (CTPR, UnknownObj) // (from opcode)
|
||||
External (FTPS, UnknownObj) // (from opcode)
|
||||
External (PNHM, FieldUnitObj) // (from opcode)
|
||||
External (PNTF, MethodObj) // 1 Arguments (from opcode)
|
||||
External (PT0D, UnknownObj) // (from opcode)
|
||||
External (PT1D, UnknownObj) // (from opcode)
|
||||
External (PT2D, UnknownObj) // (from opcode)
|
||||
External (TCNT, FieldUnitObj) // (from opcode)
|
||||
|
||||
Scope (\_SB.PCI0)
|
||||
{
|
||||
OperationRegion (MBAR, SystemMemory, 0xFED15000, 0x1000)
|
||||
Field (MBAR, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x930),
|
||||
PTDP, 15,
|
||||
Offset (0x932),
|
||||
PMIN, 15,
|
||||
Offset (0x934),
|
||||
PMAX, 15,
|
||||
Offset (0x936),
|
||||
TMAX, 7,
|
||||
Offset (0x938),
|
||||
PWRU, 4,
|
||||
Offset (0x939),
|
||||
EGYU, 5,
|
||||
Offset (0x93A),
|
||||
TIMU, 4,
|
||||
Offset (0x958),
|
||||
Offset (0x95C),
|
||||
LPMS, 1,
|
||||
CTNL, 2,
|
||||
Offset (0x9A0),
|
||||
PPL1, 15,
|
||||
PL1E, 1,
|
||||
, 1,
|
||||
PL1T, 7,
|
||||
Offset (0x9A4),
|
||||
PPL2, 15,
|
||||
PL2E, 1,
|
||||
, 1,
|
||||
PL2T, 7,
|
||||
Offset (0xF3C),
|
||||
TARN, 8,
|
||||
Offset (0xF40),
|
||||
PTD1, 15,
|
||||
Offset (0xF42),
|
||||
TAR1, 8,
|
||||
Offset (0xF44),
|
||||
PMX1, 15,
|
||||
Offset (0xF46),
|
||||
PMN1, 15,
|
||||
Offset (0xF48),
|
||||
PTD2, 15,
|
||||
Offset (0xF4A),
|
||||
TAR2, 8,
|
||||
Offset (0xF4C),
|
||||
PMX2, 15,
|
||||
Offset (0xF4E),
|
||||
PMN2, 15,
|
||||
Offset (0xF50),
|
||||
CTCL, 2,
|
||||
, 29,
|
||||
CLCK, 1,
|
||||
TAR, 8
|
||||
}
|
||||
|
||||
Method (CTCU, 0, NotSerialized)
|
||||
{
|
||||
Store (PT2D, PPL1)
|
||||
Store (One, PL1E)
|
||||
Store (One, \CTPC)
|
||||
If (LEqual (Zero, \FTPS))
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
}
|
||||
ElseIf (LEqual (\CTPR, \FTPS))
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
Store (\CTPC, \FTPS)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
Store (\CTPC, \FTPS)
|
||||
Increment (\FTPS)
|
||||
}
|
||||
|
||||
\PNTF (0x80)
|
||||
Subtract (TAR2, One, TAR)
|
||||
Store (0x02, CTCL)
|
||||
}
|
||||
|
||||
Method (CTCN, 0, NotSerialized)
|
||||
{
|
||||
If (LEqual (CTCL, One))
|
||||
{
|
||||
Store (PT0D, PPL1)
|
||||
Store (One, PL1E)
|
||||
NPPC (TARN)
|
||||
Subtract (TARN, One, TAR)
|
||||
Store (Zero, CTCL)
|
||||
}
|
||||
ElseIf (LEqual (CTCL, 0x02))
|
||||
{
|
||||
Store (Zero, CTCL)
|
||||
Subtract (TARN, One, TAR)
|
||||
NPPC (TARN)
|
||||
Store (PT0D, PPL1)
|
||||
Store (One, PL1E)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (Zero, CTCL)
|
||||
Subtract (TARN, One, TAR)
|
||||
NPPC (TARN)
|
||||
Store (PT0D, PPL1)
|
||||
Store (One, PL1E)
|
||||
}
|
||||
}
|
||||
|
||||
Method (CTCD, 0, NotSerialized)
|
||||
{
|
||||
Store (One, CTCL)
|
||||
Subtract (TAR1, One, TAR)
|
||||
NPPC (TAR1)
|
||||
Store (PT1D, PPL1)
|
||||
Store (One, PL1E)
|
||||
}
|
||||
|
||||
Name (TRAT, Zero)
|
||||
Name (PRAT, Zero)
|
||||
Name (TMPI, Zero)
|
||||
Method (NPPC, 1, Serialized)
|
||||
{
|
||||
Store (Arg0, TRAT)
|
||||
If (CondRefOf (\_PR.PR00._PSS))
|
||||
{
|
||||
If (And (\_SB.OSCP, 0x0400))
|
||||
{
|
||||
Store (SizeOf (\_PR.PR00.TPSS), TMPI)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (SizeOf (\_PR.PR00.LPSS), TMPI)
|
||||
}
|
||||
|
||||
While (LNotEqual (TMPI, Zero))
|
||||
{
|
||||
Decrement (TMPI)
|
||||
If (And (\_SB.OSCP, 0x0400))
|
||||
{
|
||||
Store (DerefOf (Index (DerefOf (Index (\_PR.PR00.TPSS, TMPI)), 0x04)), PRAT)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (DerefOf (Index (DerefOf (Index (\_PR.PR00.LPSS, TMPI)), 0x04)), PRAT)
|
||||
}
|
||||
|
||||
ShiftRight (PRAT, 0x08, PRAT)
|
||||
If (LGreaterEqual (PRAT, TRAT))
|
||||
{
|
||||
Store (TMPI, \CTPC)
|
||||
If (LEqual (Zero, \FTPS))
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
}
|
||||
ElseIf (LEqual (\CTPR, \FTPS))
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
Store (\CTPC, \FTPS)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (\CTPC, \CTPR)
|
||||
Store (\CTPC, \FTPS)
|
||||
Increment (\FTPS)
|
||||
}
|
||||
|
||||
\PNTF (0x80)
|
||||
Break
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Method (CLC2, 1, Serialized)
|
||||
{
|
||||
And (PNHM, 0x0FFF0FF0, Local0)
|
||||
Switch (ToInteger (Local0))
|
||||
{
|
||||
Case (0x000306C0)
|
||||
{
|
||||
Return (Divide (Multiply (Arg0, 0x05), 0x04, ))
|
||||
}
|
||||
Case (0x00040650)
|
||||
{
|
||||
Return (0xC8)
|
||||
}
|
||||
Default
|
||||
{
|
||||
Return (Divide (Multiply (Arg0, 0x05), 0x04, ))
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-7-UsbCTabl.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x000006BF (1727)
|
||||
* Revision 0x02
|
||||
* Checksum 0xBC
|
||||
* OEM ID "LENOVO"
|
||||
* OEM Table ID "UsbCTabl"
|
||||
* OEM Revision 0x00001000 (4096)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "LENOVO", "UsbCTabl", 0x00001000)
|
||||
{
|
||||
External (_SB_.PCI0.LPCB.EC__.HKEY.MHPF, MethodObj) // 1 Arguments (from opcode)
|
||||
External (_SB_.PCI0.RP09.PXSX.TBDU.XHC_.RHUB.TPLD, MethodObj) // 2 Arguments (from opcode)
|
||||
External (_SB_.PCI0.XHC_.RHUB, DeviceObj) // (from opcode)
|
||||
External (ADBG, MethodObj) // 1 Arguments (from opcode)
|
||||
External (OSYS, UnknownObj) // (from opcode)
|
||||
External (TBTS, UnknownObj) // (from opcode)
|
||||
External (UBCB, UnknownObj) // (from opcode)
|
||||
External (USTC, UnknownObj) // (from opcode)
|
||||
External (UTCM, UnknownObj) // (from opcode)
|
||||
External (XDCE, UnknownObj) // (from opcode)
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
Device (UBTC)
|
||||
{
|
||||
Name (_HID, EisaId ("USBC000")) // _HID: Hardware ID
|
||||
Name (_CID, EisaId ("PNP0CA0")) // _CID: Compatible ID
|
||||
Name (_UID, Zero) // _UID: Unique ID
|
||||
Name (_DDN, "USB Type C") // _DDN: DOS Device Name
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Name (CRS, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite,
|
||||
0x00000000, // Address Base
|
||||
0x00001000, // Address Length
|
||||
_Y48)
|
||||
})
|
||||
Device (CR01)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USTC, One))
|
||||
{
|
||||
Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, One))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (CR02)
|
||||
{
|
||||
Name (_ADR, One) // _ADR: Address
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USTC, One))
|
||||
{
|
||||
Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, 0x02))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
|
||||
{
|
||||
CreateDWordField (CRS, \_SB.UBTC._Y48._BAS, CBAS) // _BAS: Base Address
|
||||
Store (UBCB, CBAS)
|
||||
Return (CRS)
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized) // _STA: Status
|
||||
{
|
||||
If (LAnd (LGreaterEqual (OSYS, 0x07DF), LEqual (TBTS, One)))
|
||||
{
|
||||
If (LEqual (USTC, One))
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
OperationRegion (USBC, SystemMemory, UBCB, 0x38)
|
||||
Field (USBC, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VER1, 8,
|
||||
VER2, 8,
|
||||
RSV1, 8,
|
||||
RSV2, 8,
|
||||
CCI0, 8,
|
||||
CCI1, 8,
|
||||
CCI2, 8,
|
||||
CCI3, 8,
|
||||
CTL0, 8,
|
||||
CTL1, 8,
|
||||
CTL2, 8,
|
||||
CTL3, 8,
|
||||
CTL4, 8,
|
||||
CTL5, 8,
|
||||
CTL6, 8,
|
||||
CTL7, 8,
|
||||
MGI0, 8,
|
||||
MGI1, 8,
|
||||
MGI2, 8,
|
||||
MGI3, 8,
|
||||
MGI4, 8,
|
||||
MGI5, 8,
|
||||
MGI6, 8,
|
||||
MGI7, 8,
|
||||
MGI8, 8,
|
||||
MGI9, 8,
|
||||
MGIA, 8,
|
||||
MGIB, 8,
|
||||
MGIC, 8,
|
||||
MGID, 8,
|
||||
MGIE, 8,
|
||||
MGIF, 8,
|
||||
MGO0, 8,
|
||||
MGO1, 8,
|
||||
MGO2, 8,
|
||||
MGO3, 8,
|
||||
MGO4, 8,
|
||||
MGO5, 8,
|
||||
MGO6, 8,
|
||||
MGO7, 8,
|
||||
MGO8, 8,
|
||||
MGO9, 8,
|
||||
MGOA, 8,
|
||||
MGOB, 8,
|
||||
MGOC, 8,
|
||||
MGOD, 8,
|
||||
MGOE, 8,
|
||||
MGOF, 8
|
||||
}
|
||||
|
||||
Mutex (UBSY, 0x00)
|
||||
Method (ECWR, 0, Serialized)
|
||||
{
|
||||
ADBG ("ECWR")
|
||||
Acquire (UBSY, 0xFFFF)
|
||||
Store (Buffer (0x25){}, Local0)
|
||||
Store (0x0A, Index (Local0, Zero))
|
||||
Store (Zero, Index (Local0, One))
|
||||
Store (0x02, Index (Local0, 0x02))
|
||||
Store (0x06, Index (Local0, 0x03))
|
||||
Store (MGO0, Index (Local0, 0x04))
|
||||
Store (MGO1, Index (Local0, 0x05))
|
||||
Store (MGO2, Index (Local0, 0x06))
|
||||
Store (MGO3, Index (Local0, 0x07))
|
||||
Store (MGO4, Index (Local0, 0x08))
|
||||
Store (MGO5, Index (Local0, 0x09))
|
||||
Store (MGO6, Index (Local0, 0x0A))
|
||||
Store (MGO7, Index (Local0, 0x0B))
|
||||
Store (MGO8, Index (Local0, 0x0C))
|
||||
Store (MGO9, Index (Local0, 0x0D))
|
||||
Store (MGOA, Index (Local0, 0x0E))
|
||||
Store (MGOB, Index (Local0, 0x0F))
|
||||
Store (MGOC, Index (Local0, 0x10))
|
||||
Store (MGOD, Index (Local0, 0x11))
|
||||
Store (MGOE, Index (Local0, 0x12))
|
||||
Store (MGOF, Index (Local0, 0x13))
|
||||
Store (0x10, Index (Local0, 0x24))
|
||||
\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0)
|
||||
Store (0x0A, Index (Local0, Zero))
|
||||
Store (Zero, Index (Local0, One))
|
||||
Store (0x02, Index (Local0, 0x02))
|
||||
Store (0x04, Index (Local0, 0x03))
|
||||
Store (CTL0, Index (Local0, 0x04))
|
||||
Store (CTL1, Index (Local0, 0x05))
|
||||
Store (CTL2, Index (Local0, 0x06))
|
||||
Store (CTL3, Index (Local0, 0x07))
|
||||
Store (CTL4, Index (Local0, 0x08))
|
||||
Store (CTL5, Index (Local0, 0x09))
|
||||
Store (CTL6, Index (Local0, 0x0A))
|
||||
Store (CTL7, Index (Local0, 0x0B))
|
||||
Store (0x08, Index (Local0, 0x24))
|
||||
\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0)
|
||||
Release (UBSY)
|
||||
}
|
||||
|
||||
Method (ECRD, 0, Serialized)
|
||||
{
|
||||
ADBG ("ECRD")
|
||||
Acquire (UBSY, 0xFFFF)
|
||||
Store (Buffer (0x25){}, Local0)
|
||||
Store (0x0B, Index (Local0, Zero))
|
||||
Store (Zero, Index (Local0, One))
|
||||
Store (0x02, Index (Local0, 0x02))
|
||||
Store (0x05, Index (Local0, 0x03))
|
||||
Store (0x10, Index (Local0, 0x24))
|
||||
Store (\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0), Local1)
|
||||
Store (DerefOf (Index (Local1, 0x04)), MGI0)
|
||||
Store (DerefOf (Index (Local1, 0x05)), MGI1)
|
||||
Store (DerefOf (Index (Local1, 0x06)), MGI2)
|
||||
Store (DerefOf (Index (Local1, 0x07)), MGI3)
|
||||
Store (DerefOf (Index (Local1, 0x08)), MGI4)
|
||||
Store (DerefOf (Index (Local1, 0x09)), MGI5)
|
||||
Store (DerefOf (Index (Local1, 0x0A)), MGI6)
|
||||
Store (DerefOf (Index (Local1, 0x0B)), MGI7)
|
||||
Store (DerefOf (Index (Local1, 0x0C)), MGI8)
|
||||
Store (DerefOf (Index (Local1, 0x0D)), MGI9)
|
||||
Store (DerefOf (Index (Local1, 0x0E)), MGIA)
|
||||
Store (DerefOf (Index (Local1, 0x0F)), MGIB)
|
||||
Store (DerefOf (Index (Local1, 0x10)), MGIC)
|
||||
Store (DerefOf (Index (Local1, 0x11)), MGID)
|
||||
Store (DerefOf (Index (Local1, 0x12)), MGIE)
|
||||
Store (DerefOf (Index (Local1, 0x13)), MGIF)
|
||||
Store (0x0B, Index (Local0, Zero))
|
||||
Store (Zero, Index (Local0, One))
|
||||
Store (0x02, Index (Local0, 0x02))
|
||||
Store (0x03, Index (Local0, 0x03))
|
||||
Store (0x04, Index (Local0, 0x24))
|
||||
Store (\_SB.PCI0.LPCB.EC.HKEY.MHPF (Local0), Local1)
|
||||
Store (DerefOf (Index (Local1, 0x04)), CCI0)
|
||||
Store (DerefOf (Index (Local1, 0x05)), CCI1)
|
||||
Store (DerefOf (Index (Local1, 0x06)), CCI2)
|
||||
Store (DerefOf (Index (Local1, 0x07)), CCI3)
|
||||
Release (UBSY)
|
||||
}
|
||||
|
||||
Method (NTFY, 0, Serialized)
|
||||
{
|
||||
ADBG ("NTFY_EC")
|
||||
ECRD ()
|
||||
Sleep (One)
|
||||
Notify (\_SB.UBTC, 0x80)
|
||||
}
|
||||
|
||||
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
|
||||
{
|
||||
If (LEqual (Arg0, ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f")))
|
||||
{
|
||||
ADBG (Concatenate ("S_UCSI=", ToHexString (Arg2)))
|
||||
Switch (ToInteger (Arg2))
|
||||
{
|
||||
Case (Zero)
|
||||
{
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x0F
|
||||
})
|
||||
}
|
||||
Case (One)
|
||||
{
|
||||
ECWR ()
|
||||
}
|
||||
Case (0x02)
|
||||
{
|
||||
ECRD ()
|
||||
}
|
||||
Case (0x03)
|
||||
{
|
||||
Return (XDCE)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
ADBG ("E_UCSI")
|
||||
}
|
||||
|
||||
Return (Buffer (One)
|
||||
{
|
||||
0x00
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-8-HdaDsp.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x000001D8 (472)
|
||||
* Revision 0x02
|
||||
* Checksum 0xFF
|
||||
* OEM ID "LENOVO"
|
||||
* OEM Table ID "HdaDsp"
|
||||
* OEM Revision 0x00000000 (0)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "LENOVO", "HdaDsp", 0x00000000)
|
||||
{
|
||||
External (_SB_.PCI0.HDAS, DeviceObj) // (from opcode)
|
||||
External (ADBG, MethodObj) // 1 Arguments (from opcode)
|
||||
External (ADPM, IntObj) // (from opcode)
|
||||
External (AG1H, IntObj) // (from opcode)
|
||||
External (AG1L, IntObj) // (from opcode)
|
||||
External (AG2H, IntObj) // (from opcode)
|
||||
External (AG2L, IntObj) // (from opcode)
|
||||
External (AG3H, IntObj) // (from opcode)
|
||||
External (AG3L, IntObj) // (from opcode)
|
||||
|
||||
Scope (\_SB.PCI0.HDAS)
|
||||
{
|
||||
Method (PPMS, 1, Serialized)
|
||||
{
|
||||
If (LEqual (Arg0, ToUUID ("7111001f-d35f-44d9-81d2-7ac685bed3d7")))
|
||||
{
|
||||
Store (And (ADPM, 0x2000), Local0)
|
||||
ADBG ("RkSA:")
|
||||
ADBG (Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ToUUID ("7c708106-3aff-40fe-88be-8c999b3f7445")))
|
||||
{
|
||||
Store (And (ADPM, 0x04), Local0)
|
||||
ADBG ("iSSP:")
|
||||
ADBG (Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ToUUID ("ec774fa9-28d3-424a-90e4-69f984f1eeb7")))
|
||||
{
|
||||
Store (And (ADPM, 0x0100), Local0)
|
||||
ADBG ("WoV:")
|
||||
ADBG (Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ToUUID ("849f0d73-1678-4d57-8c78-61c548253993")))
|
||||
{
|
||||
Store (And (ADPM, 0x08), Local0)
|
||||
ADBG ("Dolby:")
|
||||
ADBG (Local0)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ACCG (AG1L, AG1H)))
|
||||
{
|
||||
Return (And (ADPM, 0x20000000))
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ACCG (AG2L, AG2H)))
|
||||
{
|
||||
Return (And (ADPM, 0x40000000))
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, ACCG (AG3L, AG3H)))
|
||||
{
|
||||
Return (And (ADPM, 0x80000000))
|
||||
}
|
||||
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Method (ACCG, 2, NotSerialized)
|
||||
{
|
||||
Name (GBUF, Buffer (0x10){})
|
||||
Concatenate (Arg0, Arg1, GBUF)
|
||||
Return (GBUF)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-9-TbtTypeC.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x00000590 (1424)
|
||||
* Revision 0x02
|
||||
* Checksum 0x32
|
||||
* OEM ID "LENOVO"
|
||||
* OEM Table ID "TbtTypeC"
|
||||
* OEM Revision 0x00000000 (0)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "LENOVO", "TbtTypeC", 0x00000000)
|
||||
{
|
||||
External (_SB_.PCI0.RP01.PXSX, DeviceObj) // (from opcode)
|
||||
External (_SB_.PCI0.RP09.PXSX, DeviceObj) // (from opcode)
|
||||
External (TBSE, IntObj) // (from opcode)
|
||||
External (TBTS, IntObj) // (from opcode)
|
||||
External (UPT1, IntObj) // (from opcode)
|
||||
External (UPT2, IntObj) // (from opcode)
|
||||
External (USME, IntObj) // (from opcode)
|
||||
|
||||
If (LAnd (LEqual (TBTS, One), LEqual (TBSE, One)))
|
||||
{
|
||||
Scope (\_SB.PCI0.RP01.PXSX)
|
||||
{
|
||||
Name (TUSB, Package (0x02)
|
||||
{
|
||||
One,
|
||||
0x04
|
||||
})
|
||||
Device (TBDU)
|
||||
{
|
||||
Name (_ADR, 0x00020000) // _ADR: Address
|
||||
Device (XHC)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Method (_PS0, 0, Serialized) // _PS0: Power State 0
|
||||
{
|
||||
Sleep (0xC8)
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized) // _PS3: Power State 3
|
||||
{
|
||||
Sleep (0xC8)
|
||||
}
|
||||
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Method (TPLD, 2, Serialized)
|
||||
{
|
||||
Name (PCKG, Package (0x01)
|
||||
{
|
||||
Buffer (0x10){}
|
||||
})
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
|
||||
Store (One, REV)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
|
||||
Store (Arg0, VISI)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x57, 0x08, GPOS)
|
||||
Store (Arg1, GPOS)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x4A, 0x04, SHAP)
|
||||
Store (One, SHAP)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x20, 0x10, WID)
|
||||
Store (0x08, WID)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x30, 0x10, HGT)
|
||||
Store (0x03, HGT)
|
||||
Return (PCKG)
|
||||
}
|
||||
|
||||
Method (TUPC, 2, Serialized)
|
||||
{
|
||||
Name (PCKG, Package (0x04)
|
||||
{
|
||||
One,
|
||||
Zero,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Store (Arg0, Index (PCKG, Zero))
|
||||
Store (Arg1, Index (PCKG, One))
|
||||
Return (PCKG)
|
||||
}
|
||||
|
||||
Device (HS01)
|
||||
{
|
||||
Name (_ADR, One) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x08))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (Zero, Zero))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, One))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (Zero, Zero))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (HS02)
|
||||
{
|
||||
Name (_ADR, 0x02) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x08))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (Zero, Zero))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, 0x02))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (Zero, Zero))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS01)
|
||||
{
|
||||
Name (_ADR, 0x03) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x09))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (One, 0x0A))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, One))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (One, UPT1))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS02)
|
||||
{
|
||||
Name (_ADR, 0x04) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x09))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (One, 0x0A))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, 0x02))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (One, UPT2))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
If (LAnd (LEqual (TBTS, One), LEqual (TBSE, 0x09)))
|
||||
{
|
||||
Scope (\_SB.PCI0.RP09.PXSX)
|
||||
{
|
||||
Name (TUSB, Package (0x02)
|
||||
{
|
||||
0x03,
|
||||
0x04
|
||||
})
|
||||
Device (TBDU)
|
||||
{
|
||||
Name (_ADR, 0x00020000) // _ADR: Address
|
||||
Device (XHC)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Method (_PS0, 0, Serialized) // _PS0: Power State 0
|
||||
{
|
||||
Sleep (0xC8)
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized) // _PS3: Power State 3
|
||||
{
|
||||
Sleep (0xC8)
|
||||
}
|
||||
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, Zero) // _ADR: Address
|
||||
Method (TPLD, 2, Serialized)
|
||||
{
|
||||
Name (PCKG, Package (0x01)
|
||||
{
|
||||
Buffer (0x10){}
|
||||
})
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
|
||||
Store (One, REV)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
|
||||
Store (Arg0, VISI)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x57, 0x08, GPOS)
|
||||
Store (Arg1, GPOS)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x4A, 0x04, SHAP)
|
||||
Store (One, SHAP)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x20, 0x10, WID)
|
||||
Store (0x08, WID)
|
||||
CreateField (DerefOf (Index (PCKG, Zero)), 0x30, 0x10, HGT)
|
||||
Store (0x03, HGT)
|
||||
Return (PCKG)
|
||||
}
|
||||
|
||||
Method (TUPC, 2, Serialized)
|
||||
{
|
||||
Name (PCKG, Package (0x04)
|
||||
{
|
||||
One,
|
||||
Zero,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Store (Arg0, Index (PCKG, Zero))
|
||||
Store (Arg1, Index (PCKG, One))
|
||||
Return (PCKG)
|
||||
}
|
||||
|
||||
Device (HS01)
|
||||
{
|
||||
Name (_ADR, One) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x08))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (Zero, Zero))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, One))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (Zero, Zero))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (HS02)
|
||||
{
|
||||
Name (_ADR, 0x02) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x08))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (Zero, Zero))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, 0x02))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (Zero, Zero))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS01)
|
||||
{
|
||||
Name (_ADR, 0x03) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x09))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (One, 0x0A))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, One))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (One, UPT1))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS02)
|
||||
{
|
||||
Name (_ADR, 0x04) // _ADR: Address
|
||||
Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TUPC (One, 0x09))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TUPC (One, 0x0A))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device
|
||||
{
|
||||
If (LEqual (USME, Zero))
|
||||
{
|
||||
Return (TPLD (One, 0x02))
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (TPLD (One, UPT2))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,465 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_0-Cpu0Ist.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x000005EE (1518)
|
||||
* Revision 0x02
|
||||
* Checksum 0x8C
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "Cpu0Ist"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Ist", 0x00003000)
|
||||
{
|
||||
External (_PR_.CFGD, FieldUnitObj) // (from opcode)
|
||||
External (_PR_.CPPC, FieldUnitObj) // (from opcode)
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (_SB_.OSCP, IntObj) // (from opcode)
|
||||
External (PC00, IntObj) // (from opcode)
|
||||
External (TCNT, FieldUnitObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR00)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.CPPC)
|
||||
}
|
||||
|
||||
Name (_PCT, Package (0x02) // _PCT: Performance Control
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (FFixedHW,
|
||||
0x00, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000000000, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (FFixedHW,
|
||||
0x00, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000000000, // Address
|
||||
,)
|
||||
}
|
||||
})
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
If (And (\_SB.OSCP, 0x0400))
|
||||
{
|
||||
Return (TPSS)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (LPSS)
|
||||
}
|
||||
}
|
||||
|
||||
Name (LPSS, Package (0x10)
|
||||
{
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000835,
|
||||
0x00003A98,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00002A00,
|
||||
0x00002A00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000834,
|
||||
0x00003A98,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001500,
|
||||
0x00001500
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x0000076C,
|
||||
0x00003389,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001300,
|
||||
0x00001300
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000708,
|
||||
0x0000301D,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001200,
|
||||
0x00001200
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000006A4,
|
||||
0x00002CC3,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001100,
|
||||
0x00001100
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000640,
|
||||
0x00002A07,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001000,
|
||||
0x00001000
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000005DC,
|
||||
0x000026D0,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000F00,
|
||||
0x00000F00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000578,
|
||||
0x000023A7,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000E00,
|
||||
0x00000E00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000004B0,
|
||||
0x00001E10,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000C00,
|
||||
0x00000C00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x0000044C,
|
||||
0x00001B19,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000B00,
|
||||
0x00000B00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000003E8,
|
||||
0x00001834,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000A00,
|
||||
0x00000A00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000320,
|
||||
0x00001318,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000800,
|
||||
0x00000800
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000002BC,
|
||||
0x00001061,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000700,
|
||||
0x00000700
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000258,
|
||||
0x00000DBA,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000600,
|
||||
0x00000600
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000001F4,
|
||||
0x00000B22,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000500,
|
||||
0x00000500
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000190,
|
||||
0x00000915,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000400,
|
||||
0x00000400
|
||||
}
|
||||
})
|
||||
Name (TPSS, Package (0x13)
|
||||
{
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000835,
|
||||
0x00003A98,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00002A00,
|
||||
0x00002A00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000834,
|
||||
0x00003A98,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001500,
|
||||
0x00001500
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000007D0,
|
||||
0x00003708,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001400,
|
||||
0x00001400
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x0000076C,
|
||||
0x00003389,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001300,
|
||||
0x00001300
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000708,
|
||||
0x0000301D,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001200,
|
||||
0x00001200
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000006A4,
|
||||
0x00002CC3,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001100,
|
||||
0x00001100
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000640,
|
||||
0x00002A07,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00001000,
|
||||
0x00001000
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000005DC,
|
||||
0x000026D0,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000F00,
|
||||
0x00000F00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000578,
|
||||
0x000023A7,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000E00,
|
||||
0x00000E00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000514,
|
||||
0x00002090,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000D00,
|
||||
0x00000D00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000004B0,
|
||||
0x00001E10,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000C00,
|
||||
0x00000C00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x0000044C,
|
||||
0x00001B19,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000B00,
|
||||
0x00000B00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000003E8,
|
||||
0x00001834,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000A00,
|
||||
0x00000A00
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000384,
|
||||
0x0000155D,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000900,
|
||||
0x00000900
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000320,
|
||||
0x00001318,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000800,
|
||||
0x00000800
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000002BC,
|
||||
0x00001061,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000700,
|
||||
0x00000700
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000258,
|
||||
0x00000DBA,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000600,
|
||||
0x00000600
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x000001F4,
|
||||
0x00000B22,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000500,
|
||||
0x00000500
|
||||
},
|
||||
|
||||
Package (0x06)
|
||||
{
|
||||
0x00000190,
|
||||
0x00000915,
|
||||
0x0000000A,
|
||||
0x0000000A,
|
||||
0x00000400,
|
||||
0x00000400
|
||||
}
|
||||
})
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,930 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_1-ApIst.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x00000D14 (3348)
|
||||
* Revision 0x02
|
||||
* Checksum 0x2A
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "ApIst"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApIst", 0x00003000)
|
||||
{
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR00._PCT, MethodObj) // 0 Arguments (from opcode)
|
||||
External (_PR_.PR00._PPC, MethodObj) // 0 Arguments (from opcode)
|
||||
External (_PR_.PR00._PSS, MethodObj) // 0 Arguments (from opcode)
|
||||
External (_PR_.PR01, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR02, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR03, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR04, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR05, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR06, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR07, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR08, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR09, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR10, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR11, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR12, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR13, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR14, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR15, DeviceObj) // (from opcode)
|
||||
External (PC00, IntObj) // (from opcode)
|
||||
External (TCNT, FieldUnitObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR01)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR02)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR03)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR04)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR05)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR06)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR07)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR08)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR09)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR10)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR11)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR12)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR13)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR14)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
Scope (\_PR.PR15)
|
||||
{
|
||||
Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities
|
||||
{
|
||||
Return (\_PR.PR00._PPC ())
|
||||
}
|
||||
|
||||
Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._PCT ())
|
||||
}
|
||||
|
||||
Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
|
||||
{
|
||||
Return (\_PR.PR00._PSS ())
|
||||
}
|
||||
|
||||
Name (PSDF, Zero)
|
||||
Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
|
||||
{
|
||||
If (LNot (PSDF))
|
||||
{
|
||||
Store (TCNT, Index (DerefOf (Index (HPSD, Zero)), 0x04))
|
||||
Store (TCNT, Index (DerefOf (Index (SPSD, Zero)), 0x04))
|
||||
Store (Ones, PSDF)
|
||||
}
|
||||
|
||||
If (And (PC00, 0x0800))
|
||||
{
|
||||
Return (HPSD)
|
||||
}
|
||||
|
||||
Return (SPSD)
|
||||
}
|
||||
|
||||
Name (HPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFE,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
Name (SPSD, Package (0x01)
|
||||
{
|
||||
Package (0x05)
|
||||
{
|
||||
0x05,
|
||||
Zero,
|
||||
Zero,
|
||||
0xFC,
|
||||
0x80
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_2-Cpu0Cst.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x000003FF (1023)
|
||||
* Revision 0x02
|
||||
* Checksum 0x11
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "Cpu0Cst"
|
||||
* OEM Revision 0x00003001 (12289)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Cst", 0x00003001)
|
||||
{
|
||||
External (_PR_.C3LT, FieldUnitObj)
|
||||
External (_PR_.C3MW, FieldUnitObj)
|
||||
External (_PR_.C6LT, FieldUnitObj)
|
||||
External (_PR_.C6MW, FieldUnitObj)
|
||||
External (_PR_.C7LT, FieldUnitObj)
|
||||
External (_PR_.C7MW, FieldUnitObj)
|
||||
External (_PR_.CDLT, FieldUnitObj)
|
||||
External (_PR_.CDLV, FieldUnitObj)
|
||||
External (_PR_.CDMW, FieldUnitObj)
|
||||
External (_PR_.CDPW, FieldUnitObj)
|
||||
External (_PR_.CFGD, UnknownObj) // Warning: Unknown object
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (C3LT, UnknownObj) // (from opcode)
|
||||
External (C3MW, UnknownObj) // (from opcode)
|
||||
External (C6LT, UnknownObj) // (from opcode)
|
||||
External (C6MW, UnknownObj) // (from opcode)
|
||||
External (C7LT, UnknownObj) // (from opcode)
|
||||
External (C7MW, UnknownObj) // (from opcode)
|
||||
External (CDLT, UnknownObj) // (from opcode)
|
||||
External (CDLV, UnknownObj) // (from opcode)
|
||||
External (CDMW, UnknownObj) // (from opcode)
|
||||
External (CDPW, UnknownObj) // (from opcode)
|
||||
External (CFGD, UnknownObj) // (from opcode)
|
||||
External (FEMD, UnknownObj) // (from opcode)
|
||||
External (FMBL, UnknownObj) // (from opcode)
|
||||
External (PC00, UnknownObj) // (from opcode)
|
||||
External (PFLV, UnknownObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR00)
|
||||
{
|
||||
Name (C1TM, Package (0x04)
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (FFixedHW,
|
||||
0x00, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000000000, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
One,
|
||||
One,
|
||||
0x03E8
|
||||
})
|
||||
Name (C3TM, Package (0x04)
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (SystemIO,
|
||||
0x08, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000001814, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
0x02,
|
||||
Zero,
|
||||
0x01F4
|
||||
})
|
||||
Name (C6TM, Package (0x04)
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (SystemIO,
|
||||
0x08, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000001815, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
0x02,
|
||||
Zero,
|
||||
0x015E
|
||||
})
|
||||
Name (C7TM, Package (0x04)
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (SystemIO,
|
||||
0x08, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000001816, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
0x02,
|
||||
Zero,
|
||||
0xC8
|
||||
})
|
||||
Name (CDTM, Package (0x04)
|
||||
{
|
||||
ResourceTemplate ()
|
||||
{
|
||||
Register (SystemIO,
|
||||
0x08, // Bit Width
|
||||
0x00, // Bit Offset
|
||||
0x0000000000001816, // Address
|
||||
,)
|
||||
},
|
||||
|
||||
0x03,
|
||||
Zero,
|
||||
Zero
|
||||
})
|
||||
Name (MWES, ResourceTemplate ()
|
||||
{
|
||||
Register (FFixedHW,
|
||||
0x01, // Bit Width
|
||||
0x02, // Bit Offset
|
||||
0x0000000000000000, // Address
|
||||
0x01, // Access Size
|
||||
)
|
||||
})
|
||||
Name (AC2V, Zero)
|
||||
Name (AC3V, Zero)
|
||||
Name (C3ST, Package (0x04)
|
||||
{
|
||||
0x03,
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
},
|
||||
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
},
|
||||
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
}
|
||||
})
|
||||
Name (C2ST, Package (0x03)
|
||||
{
|
||||
0x02,
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
},
|
||||
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
}
|
||||
})
|
||||
Name (C1ST, Package (0x02)
|
||||
{
|
||||
One,
|
||||
Package (0x01)
|
||||
{
|
||||
Zero
|
||||
}
|
||||
})
|
||||
Name (CSTF, Zero)
|
||||
Method (_CST, 0, Serialized) // _CST: C-States
|
||||
{
|
||||
If (LNot (CSTF))
|
||||
{
|
||||
Store (C3LT, Index (C3TM, 0x02))
|
||||
Store (C6LT, Index (C6TM, 0x02))
|
||||
Store (C7LT, Index (C7TM, 0x02))
|
||||
Store (CDLT, Index (CDTM, 0x02))
|
||||
Store (CDPW, Index (CDTM, 0x03))
|
||||
Store (CDLV, Index (DerefOf (Index (CDTM, Zero)), 0x07))
|
||||
If (LAnd (And (CFGD, 0x0800), And (PC00, 0x0200)))
|
||||
{
|
||||
Store (MWES, Index (C1TM, Zero))
|
||||
Store (MWES, Index (C3TM, Zero))
|
||||
Store (MWES, Index (C6TM, Zero))
|
||||
Store (MWES, Index (C7TM, Zero))
|
||||
Store (MWES, Index (CDTM, Zero))
|
||||
Store (C3MW, Index (DerefOf (Index (C3TM, Zero)), 0x07))
|
||||
Store (C6MW, Index (DerefOf (Index (C6TM, Zero)), 0x07))
|
||||
Store (C7MW, Index (DerefOf (Index (C7TM, Zero)), 0x07))
|
||||
Store (CDMW, Index (DerefOf (Index (CDTM, Zero)), 0x07))
|
||||
}
|
||||
ElseIf (LAnd (And (CFGD, 0x0800), And (PC00, 0x0100)))
|
||||
{
|
||||
Store (MWES, Index (C1TM, Zero))
|
||||
}
|
||||
|
||||
Store (Ones, CSTF)
|
||||
}
|
||||
|
||||
Store (Zero, AC2V)
|
||||
Store (Zero, AC3V)
|
||||
Store (C1TM, Index (C3ST, One))
|
||||
If (And (CFGD, 0x20))
|
||||
{
|
||||
Store (C7TM, Index (C3ST, 0x02))
|
||||
Store (Ones, AC2V)
|
||||
}
|
||||
ElseIf (And (CFGD, 0x10))
|
||||
{
|
||||
Store (C6TM, Index (C3ST, 0x02))
|
||||
Store (Ones, AC2V)
|
||||
}
|
||||
ElseIf (And (CFGD, 0x08))
|
||||
{
|
||||
Store (C3TM, Index (C3ST, 0x02))
|
||||
Store (Ones, AC2V)
|
||||
}
|
||||
|
||||
If (And (CFGD, 0x4000))
|
||||
{
|
||||
Store (CDTM, Index (C3ST, 0x03))
|
||||
Store (Ones, AC3V)
|
||||
}
|
||||
|
||||
If (LAnd (AC2V, AC3V))
|
||||
{
|
||||
Return (C3ST)
|
||||
}
|
||||
ElseIf (AC2V)
|
||||
{
|
||||
Store (DerefOf (Index (C3ST, One)), Index (C2ST, One))
|
||||
Store (DerefOf (Index (C3ST, 0x02)), Index (C2ST, 0x02))
|
||||
Return (C2ST)
|
||||
}
|
||||
ElseIf (AC3V)
|
||||
{
|
||||
Store (DerefOf (Index (C3ST, One)), Index (C2ST, One))
|
||||
Store (DerefOf (Index (C3ST, 0x03)), Index (C2ST, 0x02))
|
||||
Store (0x02, Index (DerefOf (Index (C2ST, 0x02)), One))
|
||||
Return (C2ST)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Store (DerefOf (Index (C3ST, One)), Index (C1ST, One))
|
||||
Return (C1ST)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_3-ApCst.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x0000030A (778)
|
||||
* Revision 0x02
|
||||
* Checksum 0x93
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "ApCst"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApCst", 0x00003000)
|
||||
{
|
||||
External (_PR_.PR00._CST, UnknownObj) // (from opcode)
|
||||
External (_PR_.PR01, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR02, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR03, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR04, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR05, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR06, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR07, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR08, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR09, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR10, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR11, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR12, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR13, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR14, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR15, DeviceObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR01)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR02)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR03)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR04)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR05)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR06)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR07)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR08)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR09)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR10)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR11)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR12)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR13)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR14)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR15)
|
||||
{
|
||||
Method (_CST, 0, NotSerialized) // _CST: C-States
|
||||
{
|
||||
Return (\_PR.PR00._CST)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_4-Cpu0Hwp.aml, Wed Sep 12 21:34:44 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x000000BA (186)
|
||||
* Revision 0x02
|
||||
* Checksum 0x7D
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "Cpu0Hwp"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Hwp", 0x00003000)
|
||||
{
|
||||
External (_PR_.CFGD, IntObj) // (from opcode)
|
||||
External (_PR_.HWPA, FieldUnitObj) // (from opcode)
|
||||
External (_PR_.HWPV, IntObj) // (from opcode)
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR00.CPC2, PkgObj) // (from opcode)
|
||||
External (_PR_.PR00.CPOC, PkgObj) // (from opcode)
|
||||
External (CPC2, IntObj) // Warning: Unknown object
|
||||
External (CPOC, IntObj) // Warning: Unknown object
|
||||
External (TCNT, FieldUnitObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR00)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
If (And (\_PR.CFGD, 0x01000000))
|
||||
{
|
||||
Return (CPOC)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (CPC2)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_5-ApHwp.aml, Wed Sep 12 21:34:45 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x00000317 (791)
|
||||
* Revision 0x02
|
||||
* Checksum 0x80
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "ApHwp"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "ApHwp", 0x00003000)
|
||||
{
|
||||
External (_PR_.PR00, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR00._CPC, MethodObj) // 0 Arguments (from opcode)
|
||||
External (_PR_.PR01, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR02, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR03, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR04, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR05, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR06, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR07, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR08, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR09, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR10, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR11, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR12, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR13, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR14, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR15, ProcessorObj) // (from opcode)
|
||||
|
||||
Scope (\_PR.PR01)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR02)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR03)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR04)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR05)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR06)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR07)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR08)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR09)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR10)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR11)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR12)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR13)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR14)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_PR.PR15)
|
||||
{
|
||||
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
|
||||
{
|
||||
Return (\_PR.PR00._CPC ())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Intel ACPI Component Architecture
|
||||
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
|
||||
* Copyright (c) 2000 - 2018 Intel Corporation
|
||||
*
|
||||
* Disassembling to non-symbolic legacy ASL operators
|
||||
*
|
||||
* Disassembly of SSDT-x5_6-HwpLvt.aml, Wed Sep 12 21:34:45 2018
|
||||
*
|
||||
* Original Table Header:
|
||||
* Signature "SSDT"
|
||||
* Length 0x00000628 (1576)
|
||||
* Revision 0x02
|
||||
* Checksum 0x85
|
||||
* OEM ID "PmRef"
|
||||
* OEM Table ID "HwpLvt"
|
||||
* OEM Revision 0x00003000 (12288)
|
||||
* Compiler ID "INTL"
|
||||
* Compiler Version 0x20160527 (538314023)
|
||||
*/
|
||||
DefinitionBlock ("", "SSDT", 2, "PmRef", "HwpLvt", 0x00003000)
|
||||
{
|
||||
External (_PR_.PR00, DeviceObj) // (from opcode)
|
||||
External (_PR_.PR01, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR02, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR03, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR04, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR05, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR06, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR07, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR08, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR09, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR10, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR11, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR12, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR13, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR14, ProcessorObj) // (from opcode)
|
||||
External (_PR_.PR15, ProcessorObj) // (from opcode)
|
||||
External (TCNT, FieldUnitObj) // (from opcode)
|
||||
|
||||
Scope (\_GPE)
|
||||
{
|
||||
Method (HLVT, 0, Serialized)
|
||||
{
|
||||
Switch (ToInteger (TCNT))
|
||||
{
|
||||
Case (0x10)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
Notify (\_PR.PR07, 0x83)
|
||||
Notify (\_PR.PR08, 0x83)
|
||||
Notify (\_PR.PR09, 0x83)
|
||||
Notify (\_PR.PR10, 0x83)
|
||||
Notify (\_PR.PR11, 0x83)
|
||||
Notify (\_PR.PR12, 0x83)
|
||||
Notify (\_PR.PR13, 0x83)
|
||||
Notify (\_PR.PR14, 0x83)
|
||||
Notify (\_PR.PR15, 0x83)
|
||||
}
|
||||
Case (0x0E)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
Notify (\_PR.PR07, 0x83)
|
||||
Notify (\_PR.PR08, 0x83)
|
||||
Notify (\_PR.PR09, 0x83)
|
||||
Notify (\_PR.PR10, 0x83)
|
||||
Notify (\_PR.PR11, 0x83)
|
||||
Notify (\_PR.PR12, 0x83)
|
||||
Notify (\_PR.PR13, 0x83)
|
||||
}
|
||||
Case (0x0C)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
Notify (\_PR.PR07, 0x83)
|
||||
Notify (\_PR.PR08, 0x83)
|
||||
Notify (\_PR.PR09, 0x83)
|
||||
Notify (\_PR.PR10, 0x83)
|
||||
Notify (\_PR.PR11, 0x83)
|
||||
}
|
||||
Case (0x0A)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
Notify (\_PR.PR07, 0x83)
|
||||
Notify (\_PR.PR08, 0x83)
|
||||
Notify (\_PR.PR09, 0x83)
|
||||
}
|
||||
Case (0x08)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
Notify (\_PR.PR07, 0x83)
|
||||
}
|
||||
Case (0x07)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
Notify (\_PR.PR06, 0x83)
|
||||
}
|
||||
Case (0x06)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
Notify (\_PR.PR05, 0x83)
|
||||
}
|
||||
Case (0x05)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
Notify (\_PR.PR04, 0x83)
|
||||
}
|
||||
Case (0x04)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
Notify (\_PR.PR03, 0x83)
|
||||
}
|
||||
Case (0x03)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
Notify (\_PR.PR02, 0x83)
|
||||
}
|
||||
Case (0x02)
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
Notify (\_PR.PR01, 0x83)
|
||||
}
|
||||
Default
|
||||
{
|
||||
Notify (\_PR.PR00, 0x83)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
BIN
ACPI/origin/September ACPI - BIOS 1.30/DSDT.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/DSDT.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-0-DptfTabl.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-0-DptfTabl.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-1-SaSsdt.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-1-SaSsdt.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-10-Wwan.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-10-Wwan.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-2-PerfTune.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-2-PerfTune.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-3-RVP7Rtd3.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-3-RVP7Rtd3.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-4-ProjSsdt.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-4-ProjSsdt.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-5-CpuSsdt.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-5-CpuSsdt.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-6-CtdpB.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-6-CtdpB.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-7-UsbCTabl.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-7-UsbCTabl.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-8-HdaDsp.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-8-HdaDsp.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-9-TbtTypeC.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-9-TbtTypeC.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_0-Cpu0Ist.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_0-Cpu0Ist.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_1-ApIst.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_1-ApIst.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_2-Cpu0Cst.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_2-Cpu0Cst.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_3-ApCst.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_3-ApCst.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_4-Cpu0Hwp.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_4-Cpu0Hwp.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_5-ApHwp.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_5-ApHwp.aml
Executable file
Binary file not shown.
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_6-HwpLvt.aml
Executable file
BIN
ACPI/origin/September ACPI - BIOS 1.30/SSDT-x5_6-HwpLvt.aml
Executable file
Binary file not shown.
Loading…
Reference in a new issue