diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Battery.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Battery.aml index a705877..5409b66 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Battery.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Battery.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-DMAC.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-DMAC.aml index 937c975..403f0d6 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-DMAC.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-DMAC.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-INIT.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-INIT.aml index e6c2954..19bfe90 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-INIT.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-INIT.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml index da319f5..2d9625c 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-PM.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-PM.aml index d11d678..658869b 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-PM.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-PM.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml index 368b560..df657ae 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml deleted file mode 100644 index 4923e4e..0000000 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml index 5472d10..f371866 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml index 6ce48d7..4adc11a 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml differ diff --git a/EFI-OpenCore/EFI/OC/Drivers/TbtForcePower.efi b/EFI-OpenCore/EFI/OC/Drivers/TbtForcePower.efi deleted file mode 100755 index 667091f..0000000 Binary files a/EFI-OpenCore/EFI/OC/Drivers/TbtForcePower.efi and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/Info.plist deleted file mode 100755 index aff98de..0000000 --- a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/Info.plist +++ /dev/null @@ -1,98 +0,0 @@ - - - - - BuildMachineOSBuild - 19G2021 - CFBundleDevelopmentRegion - en - CFBundleExecutable - ThunderboltReset - CFBundleIdentifier - com.osy86.ThunderboltReset - CFBundleInfoDictionaryVersion - 6.0 - CFBundleName - ThunderboltReset - CFBundlePackageType - KEXT - CFBundleShortVersionString - 1.0.0d1 - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0d1 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11E708 - DTPlatformVersion - GM - DTSDKBuild - 19G68 - DTSDKName - macosx10.15 - DTXcode - 1160 - DTXcodeBuild - 11E708 - IOKitPersonalities - - ThunderboltReset - - CFBundleIdentifier - com.osy86.ThunderboltReset - IOClass - ThunderboltReset - IOMatchCategory - ThunderboltReset - IOProviderClass - IOResources - IOResourceMatch - IOKit - - ThunderboltWait - - CFBundleIdentifier - com.osy86.ThunderboltReset - IOClass - ThunderboltWait - IOPCIClassMatch - 0x08800000&0xffff0000 - IOPCIMatch - 0x15008086&0xff00ffff - IOPCITunnelCompatible - - IOProbeScore - 500 - IOProviderClass - IOPCIDevice - - - LSMinimumSystemVersion - 10.14 - NSHumanReadableCopyright - Copyright © 2019 osy86. All rights reserved. - OSBundleLibraries - - as.vit9696.Lilu - 1.2.0 - com.apple.kpi.bsd - 12.0.0 - com.apple.kpi.dsep - 12.0.0 - com.apple.kpi.iokit - 12.0.0 - com.apple.kpi.libkern - 12.0.0 - com.apple.kpi.mach - 12.0.0 - com.apple.kpi.unsupported - 12.0.0 - - OSBundleRequired - Local-Root - - diff --git a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/MacOS/ThunderboltReset b/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/MacOS/ThunderboltReset deleted file mode 100755 index 0a18e80..0000000 Binary files a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/MacOS/ThunderboltReset and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/_CodeSignature/CodeResources b/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/_CodeSignature/CodeResources deleted file mode 100755 index d5d0fd7..0000000 --- a/EFI-OpenCore/EFI/OC/Kexts/ThunderboltReset.kext/Contents/_CodeSignature/CodeResources +++ /dev/null @@ -1,115 +0,0 @@ - - - - - files - - files2 - - rules - - ^Resources/ - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^version.plist$ - - - rules2 - - .*\.dSYM($|/) - - weight - 11 - - ^(.*/)?\.DS_Store$ - - omit - - weight - 2000 - - ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ - - nested - - weight - 10 - - ^.* - - ^Info\.plist$ - - omit - - weight - 20 - - ^PkgInfo$ - - omit - - weight - 20 - - ^Resources/ - - weight - 20 - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^[^/]+$ - - nested - - weight - 10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist index f0e63d5..281b181 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19H2 + 20A5395g CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,29 +17,27 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.2.1 + 1.3.0 CFBundleSupportedPlatforms MacOSX CFBundleVersion - 1.2.1 + 1.3.0 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild - 12A7300 - DTPlatformName - macosx + 11E801a DTPlatformVersion - 10.15.6 + GM DTSDKBuild 19G68 DTSDKName macosx10.15 DTXcode - 1201 + 1170 DTXcodeBuild - 12A7300 + 11E801a IOKitPersonalities IdeaVPC @@ -127,6 +125,30 @@ + YogaHIDD + + CFBundleIdentifier + org.zhen.YogaSMC + IOClass + YogaHIDD + IOProbeScore + 200 + IOPropertyMatch + + + name + INT33D5 + + + name + INTC1051 + + + IOProviderClass + IOACPIPlatformDevice + IOUserClientClass + YogaSMCUserClient + YogaWMI CFBundleIdentifier diff --git a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC index c8aea93..a7d54ef 100644 Binary files a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC and b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC differ diff --git a/EFI-OpenCore/EFI/OC/config.plist b/EFI-OpenCore/EFI/OC/config.plist index 74af501..3ce998a 100755 --- a/EFI-OpenCore/EFI/OC/config.plist +++ b/EFI-OpenCore/EFI/OC/config.plist @@ -126,19 +126,81 @@ Path SSDT-XHC1.aml - - Comment - Patch USB Power - Enabled - - Path - SSDT-USBX.aml - Delete Patch + + Comment + INIT: OINIT to ZINI + Count + 0 + Enabled + + Find + + FEcaT0lOSQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + FEcaWklOSQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + Battery: BAT0 to BATX + Count + 0 + Enabled + + Find + + hkJBVDA= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + hkJBVFg= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + Comment Battery: Change HWAC to XWAC EC reads @@ -183,7 +245,7 @@ Find - BkdQUlcCcA== + R1BSVwI= Limit 0 @@ -195,7 +257,7 @@ Replace - BlpQUlcCcA== + WlBSVwI= ReplaceMask @@ -246,14 +308,14 @@ Comment - XHC1: Notify(XHC_, 0x02) to XHC1 + S3 Sleep: _PTS to ZPTS Count 0 Enabled Find - hlhIQ18K + X1BUUw== Limit 0 @@ -265,42 +327,7 @@ Replace - hlhIQzEK - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - RFNEVA== - - - - Comment - Thunderbolt 3: _L27 to XL27 - Count - 0 - Enabled - - Find - - X0wyNw== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEwyNw== + WlBUUw== ReplaceMask @@ -388,41 +415,7 @@ Comment - Thunderbolt 3: _L6F to XL6F (Thunderbolt 3 Hotplug GPE) - Count - 0 - Enabled - - Find - - X0w2Rg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEw2Rg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) + Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable Count 1 Enabled @@ -456,14 +449,14 @@ Comment - Thunderbolt 3: _PTS to ZPTS(1,N) + Thunderbolt 3: NTFY to XTFY Count 0 Enabled Find - X1BUUwE= + FENHTlRGWQk= Limit 0 @@ -475,7 +468,112 @@ Replace - WlBUUwE= + FENHWFRGWQk= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + + + + Comment + XHC1: _UPC to XUPC + Count + 0 + Enabled + + Find + + X1VQQw== + + Limit + 0 + Mask + + + OemTableId + + UHJvalNzZHQ= + + Replace + + WFVQQw== + + ReplaceMask + + + Skip + 0 + TableLength + 6103 + TableSignature + + U1NEVA== + + + + Comment + XHC1: _PS0 to XPS0 + Count + 0 + Enabled + + Find + + FEIQX1BTMAg= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + FEIQWFBTMAg= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + XHC1: _PS3 to XPS3 + Count + 0 + Enabled + + Find + + FEY/X1BTMwg= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + FEY/WFBTMwg= ReplaceMask @@ -550,22 +648,58 @@ Add + PciRoot(0x0)/Pci(0x14,0x0) + + acpi-wake-type + + AQAAAA== + + device_type + USB controller + model + Sunrise Point-LP USB 3.0 xHCI Controller + + PciRoot(0x0)/Pci(0x1C,0x0) + + device_type + PCI bridge + model + Sunrise Point-LP PCI Express Root Port #1 + reg-ltrovr + + AAQAAAAAAAA= + + + PciRoot(0x0)/Pci(0x1C,0x4) + + device_type + PCI bridge + model + Sunrise Point-LP PCI Express Root Port #5 + reg-ltrovr + + AAQAAAAAAAA= + + + PciRoot(0x0)/Pci(0x1D,0x0) + + device_type + PCI bridge + model + Sunrise Point-LP PCI Express Root Port #9 + reg-ltrovr + + AAQAAAAAAAA= + + PciRoot(0x0)/Pci(0x1D,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0) ThunderboltUUID bYT/DabNYl2Vq0VgT/Xr3w== - built-in - - AA== - device_type - Thunderbolt 3 Controller - linkDetails - - CAAAAAMAAAA= - + System peripheral model JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016] @@ -1037,24 +1171,6 @@ PlistPath Contents/Info.plist - - Arch - x86_64 - BundlePath - ThunderboltReset.kext - Comment - - Enabled - - ExecutablePath - Contents/MacOS/ThunderboltReset - MaxKernel - - MinKernel - - PlistPath - Contents/Info.plist - Arch x86_64 @@ -1337,6 +1453,8 @@ Automatic + CustomMemory + Generic AdviseWindows diff --git a/README.md b/README.md index 5d98323..2077710 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,8 @@ # macOS on Thinkpad X1 Carbon 6th Generation, Model 20KH\* -[![macOS](https://img.shields.io/badge/macOS-Catalina-yellow.svg)](https://www.apple.com/macos/catalina/) -[![version](https://img.shields.io/badge/10.15.7-yellow)](https://support.apple.com/en-us/HT210642) -[![BIOS](https://img.shields.io/badge/BIOS-1.45-blue)](https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x1-carbon-6th-gen-type-20kh-20kg/downloads/driver-list/component?name=BIOS%2FUEFI) +[![macOS](https://img.shields.io/badge/macOS-Big_Sur-yellow.svg)](https://www.apple.com/macos/catalina/) +[![version](https://img.shields.io/badge/11.0.1-yellow)](https://support.apple.com/en-us/HT210642) +[![BIOS](https://img.shields.io/badge/BIOS-1.50-blue)](https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x1-carbon-6th-gen-type-20kh-20kg/downloads/driver-list/component?name=BIOS%2FUEFI) [![MODEL](https://img.shields.io/badge/Model-20KH*-blue)](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) [![OpenCore](https://img.shields.io/badge/OpenCore-0.6.3-green)](https://github.com/acidanthera/OpenCorePkg) [![LICENSE](https://img.shields.io/badge/license-MIT-green.svg)](https://github.com/996icu/996.ICU/blob/master/LICENSE) @@ -25,52 +25,23 @@ ##### Recent | [Changelog Archive](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/CHANGELOG.md) -> ### 2020-11-3 +> ### 2020-11-13 #### Changed -- OC to 0.6.3 and upgrade various Acidanthera kexts -- Restructured docs: depricated legacy things and combined duplicates. -- `YogaSMC` is now the preferred method to handle Fn keys instead of ThinkpadAssisstant. - - Note that `YogaSMC` is still in its infancy, so you still prefer ThinkpadAssistant, use `SSDT-Keyboard-Legacy.dsl` and `/patches/OpenCore Patches/ Keyboard-Legacy.plist` - - Thank you @zhen-zen for the great kext and app. -- Updated `config.plsit`: - - Removed depricated ACPI renames in accordance with new ACPI patches. - - Added `Arch` value to each kext entry in accordance with new OpenCore doc. - - Added Thunderbolt 3 Device Properties. - - Added `ExtendBTFeatureFlags` value to replace `BT4LEContinuityFixup` -- Reorganized subdirectories within `/patches/` to make things easier to find and understand. -- Renamed `3_README-POSTinstallation.md` to `SUMMARY.md` since it's not really a step but more of an overview of what patches what. -- More readble and better writing of `SSDT-Keyboard` -- New `SSDT-PNLF` to accomodate `AppleBacklightSmoother.kext` -- New battery patch `SSDT-Battery` that fixes accesses to 16byte-EC-field HWAC (Issue #82). -- `SSDT-Sleep` is an all-in-one sleep patch over `SSDT-PTSWAK`, `SSDT-GPRW`, `SSDT-EXT*` - - It is no longer necessary to set sleep mode to `Linux` in BIOS as it is now indepently set by `SSDT-Sleep` -- `If (_OSI ("Darwin"))` and `SSDT-DTPG` are now replaced in favor of `SSDT-Darwin` and `OSDW`, just like in genuine Macs. -- Removed `USBPorts.kext` in favor of patching/mapping via ACPI with `SSDT-XHC1`, `SSDT-XHC2`, and `SSDT-USBX` -- `README.md`: - - Turned different sections into menus for better readability. - - Merged `3_README-POSTinstallation.md` into the `SUMMARY` section. -- Set `HibernateMode` to `NVRAM` instead of `Auto` - -#### Added - -- `update.sh` script to automatically build and replace all ACPI patches -- `SSDT-HWAC` to patch access to 16byte-EC-field HWAC -- `SSDT-EC` to patch embedded controller for use with `YogaSMC` -- `SSDT-Debug`, `SSDT-HOOKS`, and `Debug.plist` for debugging if needed -- `SSDT-INIT` to configure system values: `HPET`, `DYTC`, and `DPTF` -- `YogaSMC.kext` to interface with the device's EC. Make sure to also install the [app and pref pane](https://github.com/zhen-zen/YogaSMC/releases). -- `AppleBacklightSmoother.kext` is just as its name implies. -- `BrightnessKeys.kext` to handle Fn keys with ACPI renames. -- Documentation of modding the Thunderbolt 3 controller. +- Upgraded to Big Sur +- Upgraded to BIOS-v1.50 and added corresponding ACPI dump. +- Upgraded `YogaSMC` to stable build `1.3.0` +- Compatibiltity and improvements on `SSDT-Battery`. Thanks @benbender +- Experimental TB3 patch by @benbender: + - Complete hotplug and power management without modded TB3 controller firmware + - NOTE: Brokenb USB 3.1 Gen2 hotplug still, but everything else is amazing! + - Everyone thanks @benbender again! This would not have been possible without his hard work and research. #### Removed - -- `SSDT-HPET`, similar to genuine Macs, HPET is now disabled within `SSDT-INIT` - -#### Remark -- A large of these changes are due to the hardwork of [@benbender](https://github.com/benbender), who debugged and authored many of the new ACPI patches. Thank you for your hard work! +- Deprecated legacy keyboard patches. `YogaSMC` is now recommended and preferred. +- `TbtForcePower.efi` as it is no longer needed. +- `ThunderboltReset.kext` has it is no longer needed.
SUMMARY @@ -112,13 +83,9 @@ | 4K UHD output via HDMI/ DisplayPort **(Modded BIOS)** | ✅ | See `DMVT Pre-Allocated` to `64M` | See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) for information about modding the BIOS. | | 4K UHD output via HDMI/ DisplayPort **(Vanilla BIOS)** | ✅ | See `/patches/OpenCore Patches/4K-Output-wo-BIOSmod.plist` | - | | USB 2.0, USB 3.0, and Micro SD Card Reader | ✅ | `SSDT-XHC1.aml` | - | -| USB 3.1 | ⚠️ | `SSDT-XHC2.aml` | - | +| USB 3.1 | ⚠️ | `SSDT-XHC2.aml` | Hotplug WIP | | USB Power Properties in macOS | ✅ | `SSDT-USBX.aml` | - | -| Thunderbolt 3 **(Cold Boot)** | ✅ | `SSDT-TB3.aml`, | TB3 device must be plugged in before boot. | -| Thunderbolt 3 Hotplug **(Modded Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md), [Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | -| Thunderbolt 3 Hotplug **(Modded Controller and Vanilla BIOS)** | ⚠️ | `SSDT-TB3.aml` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | -| Thunderbolt 3 Hotplug **(Vanilla Controller and Modded BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext`, `GPIO3 Force Pwr` and `GPIO3 Force Pwr for PR05` checked in BIOS | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | -| Thunderbolt 3 Hotplug **(Vanilla Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext`, and `TbtForcePower.efi` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | +| Thunderbolt 3 Hotplug | ✅ | `SSDT-TB3.aml` | Native interface within System Report | > ### Display, TrackPad, TrackPoint, and Keyboard | Feature | Status | Dependency | Remarks | @@ -126,9 +93,9 @@ | Brightness Adjustments | ✅ | `WhateverGreen.kext`, `SSDT-PNLF.aml`, `AppleBacklightSmoother.kext`, and `BrightnessKeys.kext`| `AppleBacklightSmoother.kext` is optional for smoother birghtness adjustments | | HiDPI _(Optional)_ | ✅ | [xzhih/one-key-hidpi](https://github.com/xzhih/one-key-hidpi) | Scaling issues post-sleep fixed with AAPL, ig-platform `BAAnWQ==` | | TrackPoint | ✅ | `VoodooPS2Controller.kext` | - | -| TrackPad | ✅ | `VoodooPS2Controller.kext` or `VoodooSMBus.kext` and `VoodooRMI.kext` | I prefer `VoodooRMI.kext` so that is the repository default. | +| TrackPad | ✅ | `VoodooPS2Controller.kext` or `VoodooSMBus.kext` and `VoodooRMI.kext` | `VoodooRMI.kext` is recommended and preferred over `VoodooPS2`. | | Built-in Keyboard | ✅ | `VoodooPS2Controller.kext` | Optimizations recommended, see [`docs/3_README-other.md`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md) | -| Multimedia Keys | ✅ | `BrightnessKeys.kext` and [YogaSMC](https://github.com/zhen-zen/YogaSMC) or [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) with legacy patches | YogaSMC is the repo default, `SSDT-Keyboard-Legacy.aml`, `patches/OpenCore Patches/ Keyboard-Legacy.plist` if you want to use [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) instead | +| Multimedia Keys | ✅ | `BrightnessKeys.kext` and [YogaSMC](https://github.com/zhen-zen/YogaSMC) | `YogaSMC` is recommended and preferred over ThinkpadAssisstant | > ### macOS Continuity | Feature | Status | Dependency | Remarks | diff --git a/docs/1_README-HARDWAREandBIOS.md b/docs/1_README-HARDWAREandBIOS.md index 463b2a7..4221340 100644 --- a/docs/1_README-HARDWAREandBIOS.md +++ b/docs/1_README-HARDWAREandBIOS.md @@ -54,7 +54,7 @@ At the minimum, these BIOS settings must be made to install and run macOS withou | Main Menu | Sub 1 | Sub 2 | Sub 3 | | --------- | ----------- | --------------------------------------------- | ------------------------------------------------------------------ | | | >> Config | >> Thunderbolt (TM) 3 | Thunderbolt BIOS Assist Mode `Disabled` | -| | | | Thunderbolt(TM) Device `Enabled` | +| | | | Thunderbolt(TM) Device `Disabled` | > ## Modding the BIOS: @@ -120,30 +120,4 @@ The following are further optimization settings that can be figured once your BI |--------------|------------------------|------------------------------------|------------------------------------------------------------------------|--------------------------| | Advanced Tab | >> Power & Performance | >> CPU - Power Management Control | Boot performance mode `Max Battery` | | | | | | >> Config TDP Configurations | `Down` | -| | | | | | - * If you do do want to use Thunderbolt 3 hotplug on macOS (at the expense of idle power consumption): - -| Main Menu | Sub 1 | Sub 2 | Sub 3 | -|--------------|------------------------|------------------------------------|------------------------------------------------------------------------| -| Advanced Tab | >> Intel Advanced Menu | >> Thunderbolt(TM) Configuration | GPIO3 Force Pwr `Checked` | -| | | | GPIO3 Force Pwr for PR05 `Checked` | -| | | | | - -* Native macOS Thunderbolt interfacing, at the expense of TB3 hotplugging on other OSes: -If macOS is your only OS on the machine, or if you only need to use Thunderbolt 3 hotplug on macOS. There is a custom modded firmware that can be flashed onto the Thunderbolt 3 controller that allows for native Thunderbolt interfacing in macOS: -https://www.tonymacx86.com/threads/success-gigabyte-designare-z390-thunderbolt-3-i7-9700k-amd-rx-580.267551/page-2452#post-2160674 - - - Screenshot/testing courtesy of @nottthebee -* The Thunderbolt chip is located on the top right of the motherboard. -* A note before you do this, however, the modded thunderbolt firmware will still require that you disable Thunderbolt BIOS assist, so again, TB3 hotplug will come at the cost of power consumption. -* Secondly, as far as I can tell, this mod is really to make things look cleaner and more native within macOS, and doesn't have any real improvements versus the TB3 method currently in this repo. - -> ## Modding the Thunderbolt 3 Controller: -The `Intel JHL6540 (Alpine Ridge 4C)` TB3 chip is labeled as `Winbond` and `W25Q80DVS` is located on the top right of the motherboard. - -- Download [macOS compatible firmware](https://www.tonymacx86.com/attachments/lenovo-x1-carbon-nvm-43-mod-1-caseysj-bin-zip.483524/) -- Again, [@notthebee](https://github.com/notthebee) also has a useful video to follow: https://www.youtube.com/watch?v=ce7kqUEccUM -- Remember to dump the vanilla twice and use `diff` to make sure things were dumped properly, store this backup somewhere safe. -- Once the vanilla firmware has been safely dumped and backed up, you can flash the custom firmware onto the controller. -- Successfully modding your Thunderbolt 3 controller can be confirmed via macOS's System Report: -macOS native TB3 \ No newline at end of file +| | | | | | \ No newline at end of file diff --git a/docs/3_README-other.md b/docs/3_README-other.md index 14de93e..b653146 100644 --- a/docs/3_README-other.md +++ b/docs/3_README-other.md @@ -35,35 +35,13 @@ - See current available patches in `/patches/Internal Displays/`, merge them with `config.plist` - If a patch is not yet created for your display model. Please see [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) to create your own EDID override. Please create a pull request to add your EDID override for different displays. -> ## Thunderbolt 3 Hotplug a.k.a The Big Boss (Work in Progress): +> ## Thunderbolt 3 Hotplug -Summary, TB3 hotplug works perfectly, but with some caveats: -- Firstly, refer to [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) for BIOS configurations having to do with TB3 hotplug. -- `Thunderbolt BIOS Assist` needs to be disabled which raises idle CPU power consumption to 2W as opposed to ~0.8W with the option enabled. -- See the ongoing issue/discussion [Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) - -With those done, there are two scenarios: -- You want to use TB3 hotplug on both macOS and another OS, such as Linux or Windows. In this case, stick with the current TB3 hotplug setup in this repo. As my repo is currently designed around compatibility with other OSes as I need Windows for work. -- You only need TB3 hotplug on macOS. In this case, it is possible to reflash the Thunderbolt controller chip on the machine with a modded firmware designed to allow native Thunderbolt interfacing with macOS. See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md). - -With Thunderbolt 3 Hotplug, these are the possible scenarios: -- **Modded Controller and BIOS:** - - No additional kexts or drivers needed. (You can remove TB3 related kexts and drivers from your EFI) - - TB3 Hotplug will work natively in macOS. - - TB3 Hotplug will NOT work in Windows or other OS'es. -- **Modded Controller and Vanilla BIOS:** - - No additional kexts or drivers needed. (You can remove TB3 related kexts and drivers from your EFI) - - TB3 Hotplug will work natively in macOS. - - TB3 Hotplug will NOT work in Windows or other OS'es. -- **Vanilla Controller and Modded BIOS:** - - Use `ThunderboltReset.kext` - - Use modded BIOS to force power on `PR09` and `PR05` -- **Vanilla Controller and BIOS:** - - Use `ThunderboltReset.kext` and `TbtForcePower.efi` - - Hotplug will not work on Power port (`PR05`) - -- Regardless, current TB3 hotplug implementations are not perfect. Current conflicts include getting USB 3.1 gen2, pm, tb - in osx + win all working at the same time. -For a more detailed, and better explaination, refer to [osy86's Thunderbolt Hotplug Docs](https://github.com/osy86/HaC-Mini/tree/master/details) +- Native-like integration with macOS in System Report without the need of flashing a modded firmware. Thank you @benbender +- Please make sure of these settings in BIOS: + - Thunderbolt BIOS Assist Mode `Disabled` + - Thunderbolt(TM) Device `Disabled` +- USB 3.1 Gen2 hotplug still WIP. > ## Keyboard: diff --git a/docs/CHANGELOG.md b/docs/CHANGELOG.md index 1b67798..2da3458 100644 --- a/docs/CHANGELOG.md +++ b/docs/CHANGELOG.md @@ -3,6 +3,24 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/). +> ### 2020-11-13 + +#### Changed + +- Upgraded to Big Sur +- Upgraded to BIOS-v1.50 and added corresponding ACPI dump. +- Upgraded `YogaSMC` to stable build `1.3.0` +- Compatibiltity and improvements on `SSDT-Battery`. Thanks @benbender +- Experimental TB3 patch by @benbender: + - Complete hotplug and power management without modded TB3 controller firmware + - NOTE: Brokenb USB 3.1 Gen2 hotplug still, but everything else is amazing! + - Everyone thanks @benbender again! This would not have been possible without his hard work and research. + +#### Removed +- Deprecated legacy keyboard patches. `YogaSMC` is now recommended and preferred. +- `TbtForcePower.efi` as it is no longer needed. +- `ThunderboltReset.kext` has it is no longer needed. + > ### 2020-11-3 #### Changed diff --git a/patches/OpenCore Patches/Battery-Legacy.plist b/patches/OpenCore Patches/Battery-Legacy.plist deleted file mode 100644 index db31818..0000000 --- a/patches/OpenCore Patches/Battery-Legacy.plist +++ /dev/null @@ -1,139 +0,0 @@ - - - - - ACPI - - Patch - - - Comment - TP-BAT:GBIF03 to XBIF03 - Count - 0 - Enabled - - Find - - R0JJRgM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJJRgM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:GBIX03 to XBIX03 - Count - 0 - Enabled - - Find - - R0JJWAM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJJWAM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:GBST04 to XBST04 - Count - 0 - Enabled - - Find - - R0JTVAQ= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJTVAQ= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:AJTP03 to XJTP03 - Count - 0 - Enabled - - Find - - QUpUUAM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEpUUAM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - - - diff --git a/patches/OpenCore Patches/Battery.plist b/patches/OpenCore Patches/Battery.plist new file mode 100644 index 0000000..c27dbcd --- /dev/null +++ b/patches/OpenCore Patches/Battery.plist @@ -0,0 +1,47 @@ + + + + + ACPI + + Patch + + + Comment + Battery: BAT0 to BATX + Count + 0 + Enabled + + Find + + hkJBVDA= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + hkJBVFg= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + + diff --git a/patches/OpenCore Patches/INIT.plist b/patches/OpenCore Patches/INIT.plist new file mode 100644 index 0000000..305fbe7 --- /dev/null +++ b/patches/OpenCore Patches/INIT.plist @@ -0,0 +1,47 @@ + + + + + ACPI + + Patch + + + Comment + INIT: OINIT to ZINI + Count + 0 + Enabled + + Find + + FEcaT0lOSQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + FEcaWklOSQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + + diff --git a/patches/OpenCore Patches/Keyboard-Legacy.plist b/patches/OpenCore Patches/Keyboard-Legacy.plist deleted file mode 100644 index 2c7e60a..0000000 --- a/patches/OpenCore Patches/Keyboard-Legacy.plist +++ /dev/null @@ -1,397 +0,0 @@ - - - - - ACPI - - Add - - - Comment - Thinkpad Keyboard (Need x1c6-keyboard.plist) - Enabled - - Path - SSDT-Keyboard.aml - - - Patch - - - Comment - _Q6A to XQ6A (F4 - Microphone Mute) - Count - 1 - Enabled - - Find - - X1E2QQ== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2QQ== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q15 to XQ15 (F5 - Brightness Down) - Count - 1 - Enabled - - Find - - X1ExNQ== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFExNQ== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q14 to XQ14 (F6 - Brightness Up) - Count - 1 - Enabled - - Find - - X1ExNA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFExNA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q16 to XQ16 (F7 - Dual Display) - Count - 1 - Enabled - - Find - - X1ExNg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFExNg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q64 to XQ64 (F8 - Network) - Count - 1 - Enabled - - Find - - X1E2NA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2NA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q66 to XQ66 (F9 - Settings) - Count - 1 - Enabled - - Find - - X1E2Ng== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2Ng== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q60 to XQ60 (F10 - Bluetooth) - Count - 1 - Enabled - - Find - - X1E2MA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2MA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q61 to XQ61 (F11 - Keyboard) - Count - 1 - Enabled - - Find - - X1E2MQ== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2MQ== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q62 to XQ62 (F12 - Star) - Count - 1 - Enabled - - Find - - X1E2Mg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2Mg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q1F to XQ1F (Keyboard backlight - Fn + Space) - Count - 1 - Enabled - - Find - - X1ExRg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFExRg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q74 to XQ74 (FnLock - Fn + Esc) - Count - 1 - Enabled - - Find - - X1E3NA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE3NA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - - - diff --git a/patches/OpenCore Patches/Sleep.plist b/patches/OpenCore Patches/Sleep.plist index 03a0008..068d5fa 100644 --- a/patches/OpenCore Patches/Sleep.plist +++ b/patches/OpenCore Patches/Sleep.plist @@ -14,23 +14,32 @@ Enabled Find - BkdQUlcCcA== + + R1BSVwI= + Limit 0 Mask - + + OemTableId - + + Replace - BlpQUlcCcA== + + WlBSVwI= + ReplaceMask - + + Skip 0 TableLength 0 TableSignature - RFNEVA== + + RFNEVA== + Comment @@ -40,23 +49,67 @@ Enabled Find - X1dBSwk= + + X1dBSwk= + Limit 0 Mask - + + OemTableId - + + Replace - WldBSwk= + + WldBSwk= + ReplaceMask - + + Skip 0 TableLength 0 TableSignature - RFNEVA== + + RFNEVA== + + + + Comment + S3 Sleep: _PTS to ZPTS + Count + 0 + Enabled + + Find + + X1BUUw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WlBUUw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + diff --git a/patches/OpenCore Patches/Thunderbolt3.plist b/patches/OpenCore Patches/Thunderbolt3.plist index 73f76da..c193aaf 100644 --- a/patches/OpenCore Patches/Thunderbolt3.plist +++ b/patches/OpenCore Patches/Thunderbolt3.plist @@ -6,41 +6,6 @@ Patch - - Comment - Thunderbolt 3: _L27 to XL27 - Count - 0 - Enabled - - Find - - X0wyNw== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEwyNw== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - RFNEVA== - - Comment Thunderbolt 3: RP09:_PS0 to RP09:XPS0 @@ -115,14 +80,14 @@ Comment - Thunderbolt 3: _L6F to XL6F (Thunderbolt 3 Hotplug GPE) + Thunderbolt 3: NTFY to XTFY Count 0 Enabled Find - X0w2Rg== + FENHTlRGWQk= Limit 0 @@ -134,7 +99,7 @@ Replace - WEw2Rg== + FENHWFRGWQk= ReplaceMask @@ -149,7 +114,7 @@ Comment - Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) + Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable Count 1 Enabled @@ -181,72 +146,6 @@ - - Comment - Thunderbolt 3: _PTS to ZPTS(1,N) - Count - 0 - Enabled - - Find - - X1BUUwE= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WlBUUwE= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - RFNEVA== - - - - - Kernel - - Add - - - Arch - x86_64 - BundlePath - ThunderboltReset.kext - Comment - - Enabled - - ExecutablePath - Contents/MacOS/ThunderboltReset - MaxKernel - - MinKernel - - PlistPath - Contents/Info.plist - - - - UEFI - - Drivers - - TbtForcePower.efi diff --git a/patches/OpenCore Patches/XHC1.plist b/patches/OpenCore Patches/XHC1.plist index 4e3c3e4..1297bab 100644 --- a/patches/OpenCore Patches/XHC1.plist +++ b/patches/OpenCore Patches/XHC1.plist @@ -8,14 +8,50 @@ Comment - XHC1: Notify(XHC_, 0x02) to XHC1 (Fix Restart on Shutdown) + XHC1: _UPC to XUPC Count 0 Enabled Find - hlhIQ18K + X1VQQw== + + Limit + 0 + Mask + + + OemTableId + + UHJvalNzZHQ= + + Replace + + WFVQQw== + + ReplaceMask + + + Skip + 0 + TableLength + 6103 + TableSignature + + U1NEVA== + + + + Comment + XHC1: _PS0 to XPS0 + Count + 0 + Enabled + + Find + + FEIQX1BTMAg= Limit 0 @@ -27,7 +63,42 @@ Replace - hlhIQzEK + FEIQWFBTMAg= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + XHC1: _PS3 to XPS3 + Count + 0 + Enabled + + Find + + FEY/X1BTMwg= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + FEY/WFBTMwg= ReplaceMask diff --git a/patches/SSDT-Battery.dsl b/patches/SSDT-Battery.dsl index 37d0357..dbb1717 100644 --- a/patches/SSDT-Battery.dsl +++ b/patches/SSDT-Battery.dsl @@ -1,50 +1,115 @@ +// Depends on /patches/OpenCore Patches/ Battery.plist // // SSDT-BATX -// Revision 5 +// Revision 7 // // Copyleft (c) 2020 by bb. No rights reserved. // // // Abstract: +// // This SSDT is a complete, self-contained replacement for all battery-patches on Thinkpads which share -// a common EC-layout for battery-handling. It should be compatible with all(?) T- and X-series Thinkpads and maybe even more. +// a common EC-layout [1] for battery-handling. It should be compatible with all(?) T- and X-series Thinkpads which are using the basic H8-EC-Layout [2]. // -// It doesn't need any patches to the original DSDT, handles single- and dual-battery-systems gracefully and adds -// support for `Battery Information Supplement` (see: https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md). +// Its designed for the requirements of VirtualSMC [3], leaves the original DSDT largely untouched, +// handles single- and dual-battery-systems gracefully and adds support for `Battery Information Supplement` [4]. // -// It is faster, more compatible and much more robust than existing patches as it doesn't relie on the original DSDT-implementation -// for battery-handling and EC-access. It eliminates the need to patch mutexes, notifies or EC-fields completely. +// Sadly, it needs patching of battery-ACPI-notifies as the EC doesn't seem to be updated correctly by the firmware if they are missing. +// +// It is faster, more compatible and much more robust than existing patches as it doesn't rely on the original DSDT-implementation +// for battery-handling and EC-access. It eliminates the need to patch mutexes and EC-fields completely. Patching notify()'s is +// not needed, but may be desireable for smoother operation - espacially on dual-battery-systems. // // It replaces any battery-related DSDT-patches and any SSDT like SSDT-BAT0, SSDT-BATT, SSDT-BATC, SSDT-BATN and similar. // -// Its only dependency is the memory-layout of the Embedded Controller (EC), which is mostly the same for all decent modern thinkpads -// (at least T440/X440 upwards) and nothing else. Just drop the SSDT in and be done. -// For most Thinkpads, this should be the only thing you need to handle your batteries. Nothing more, nothing less. +// Because of its implementation, its only dependency is the memory-layout of the Embedded Controller (EC) [1], +// which is mostly the same for all decent modern thinkpads (at least T440/X440 upwards) and nothing else. +// Just drop the SSDT in and be done. For most Thinkpads, this should be the only thing you need to handle your batteries. +// Nothing more, nothing less. // // But be aware: this is newly created stuff, not much tested or battle proven yet. May contain bugs and edgecases. -// If so, please open a bug @ https://github.com/benbender/x1c6-hackintosh/issues +// If so, please open a bug @ https://github.com/benbender/x1c6-hackintosh/issues. +// Additionally, as this implementation is more straight-forward and according to specs, it may reveal bugs and glitches +// in other parts of the system. +// +// Compatibility: +// +// - Lenovo Thinkpad X1 Carbon generation 6 (X1C6) +// - Lenovo Thinkpad T480 (T480) +// - Lenovo Thinkpad T460 (T460) +// - Lenovo Thinkpad T460 (T440) +// - ... many more to be added as testing is done +// +// +// Technical Background +// +// On genuine MacBooks batteries are connected via SBS (Smart Battery System [5]) to the +// SMC (System Management Controller) [6]. The SMC provides the battery-data via SMC-keys [7] to the OS. +// +// On Hackintoshes we "only" have an emulated SMC as substitute for the HW-SMC because of the missing hardware. +// Our systems usually provide battery-data, read from an EC (Embedded Controller), via ACPI [8]. +// +// In practice the OS reads SMC-keys provided by VirtualSMC which uses its SMCBatteryManager-plugin to poll those +// raw-data from ACPI which normally reads those data from the EC of the machine. +// +// Every part of the flow computes and interpretes the data. Therefor control in this SSDT is limited. +// +// As the ACPI-battery-interface is a proven standard and commonly implemented, this approach should, theoretically, +// work out of the box on most laptop-systems. +// +// In practice the AppleACPIPlatform.kext doesn't implement access to EC-fields larger than 8 bits and +// will crash on reading them. This limitation of the driver in OSX is the reason why all those battery-patching +// is neccessary in the first place. We need to ensure that every EC-field, accessed from OSX, is 8 bit at most. +// +// Additionally no such thing as dual-battery-systems exist in mac-world. OSX is able to recognize +// multiple batteries, but will only handle display of the data for the first battery. Therefor we need +// to combine multiple batteries transperantly into one and hide additional batteries to the OS. +// +// Implementation-wise, the apple-approach is able to provide some more data to the OS in comparison to ACPI. +// That might be the reason why apple opted for their implementation in the first place. To circumvent those +// limitations of the ACPI specification, VirtualSMC adds `Battery Information Supplement` (BIS). +// +// BIS tries to add the missing information normally provided on genuine MacBooks. Therefor it enables +// much more OSX-native handling of batteries but also may reveal glitches and bugs between implementations +// of OSX/ACPI/EC. Therefor its configureable in this SSDT. // // -// References: -// https://github.com/coreboot/coreboot/blob/master/src/ec/quanta/it8518/acpi/ec.asl -// https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf -// https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md +// Known Issues: +// +// - no known issues atm +// +// +// Links & References: +// +// [1] https://github.com/coreboot/coreboot/blob/master/src/ec/quanta/it8518/acpi/ec.asl +// [2] https://en.wikipedia.org/wiki/H8_Family +// [3] https://github.com/acidanthera/VirtualSMC +// [4] https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md +// [5] https://en.wikipedia.org/wiki/Smart_Battery_System +// [6] https://en.wikipedia.org/wiki/System_Management_Controller +// [7] https://github.com/acidanthera/VirtualSMC/blob/master/Docs/SMCKeys.txt +// [6] https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf // // // Changelog: -// Revision 1 - Raised timeout for mutexes, factored bank-switching out, added sleep to bank-switching, moved HWAC to its own SSDT -// Revision 2 - Prelimitary dual-battery-support, large refactoring -// Revision 3 - Remove need of patched notifies, handle battery attach/detach inside, make the whole device self-contained (exept for the EC-helpers) -// Revision 4 - Waits on initialization of the batts now. Besides that: Optimization, rework, cleanup, fixes. Truely self-contained now. And faster. -// Revision 5 - optimization, bug-fixing. Adds temp, concatenates string-data on combined batteries. -// // -// Add the following methods if didn't have them defined anyways: +// Revision 7 - Smaller fixes, adds Notify-patches as EC won't update without them in edge-cases, replaces fake serials with battery-serial +// Revision 6 - fixes, make the whole system more configureable, adds technical backround-documentation +// Revision 5 - optimization, bug-fixing. Adds temp, concatenates string-data on combined batteries. +// Revision 4 - Waits on initialization of the batts now. Besides that: Optimization, rework, cleanup, fixes. Truely self-contained now. And faster. +// Revision 3 - Remove need of patched notifies, handle battery attach/detach inside, make the whole device self-contained (exept for the EC-helpers) +// Revision 2 - Prelimitary dual-battery-support, large refactoring +// Revision 1 - Raised timeout for mutexes, factored bank-switching out, added sleep to bank-switching, moved HWAC to its own SSDT +// // // Credits @benbender -DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) + +DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00007000) { + // Please ensure that your LPC bus-device is available at \_SB.PCI0.LPCB (check your DSDT). + // Some older Thinkpads provide the LPC on \_SB.PCI0.LPC and if thats the case for you, + // you need to adjust the paths in the following line until the first "Scope ()". External (_SB.PCI0.LPCB.EC, DeviceObj) // @see https://en.wikipedia.org/wiki/Bank_switching @@ -76,18 +141,46 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) { /************************* Configuration *************************/ - Name (BDBG, One) + // + // Enable debugging output + // + // Add https://github.com/acidanthera/DebugEnhancer to your kexts + // and add `debug=0x12a acpi_layer=0x8 acpi_level=0x2` to your boot-args + // to see the output in syslog/dmesg (f.e. via `sudo dmesg|egrep BATX`) + // + Name (BDBG, Zero) // possible values: One / Zero + + // + // Enable Battery Information Supplement (BIS) + // + // BIS tries to add the missing information normally provided on genuine MacBooks + // but not available in the ACPI-specification. It enables much more OSX-native handling + // of batteries but also may reveal glitches and bugs between implementation of OSX/ACPI/EC. + // + // Therefor its configureable here. + // + // See https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md + // + Name (BBIS, One) // possible values: One / Zero + + // + // Disable quickpoll in VirtualSMC SMCBatteryManager + // + // Implicitly disabled if BBIS is disabled + // + Name (BDQP, One) // possible values: One / Zero /************************* Mutex **********************************/ + // We reimplement the battery-mutex here to solve the need to patch the original mutex + // on older thinkpads where the mutex has a non-zero synclevel which isn't handled by OSX. Mutex (BAXM, 0x00) /************************* EC overlay *****************************/ - - Field(BRAM, ByteAcc, NoLock, Preserve) + Field (BRAM, ByteAcc, NoLock, Preserve) { Offset (0x38), // HB0S: [Battery 0 status (read only)] @@ -106,8 +199,15 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) HB1S, 7, /* Battery 1 state */ HB1A, 1, /* Battery 1 present */ - Offset (0xC9), - HWAT, 8, /* Wattage of AC/DC */ + Offset (0x46), + , 1, + , 1, + , 1, + , 1, + HPAC, 1, + + // Offset (0xC9), + // HWAT, 8, /* Wattage of AC/DC */ // Zero on the X1C6. Probably because of the charging is handled by the TI USB-C-PD-chip. // Offset (0xCC), @@ -435,23 +535,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) */ Method (SBSN, 0, NotSerialized) { - Local0 = B1B2 (SN00, SN01) - - Local3 = Buffer (0x06) - { - " " - } - - Local2 = 0x04 - - While (Local0) - { - Divide (Local0, 10, Local1, Local0) - Local3 [Local2] = (Local1 + 0x30) - Local2-- - } - - Return (ToString (Local3)) + Return (B1B2 (SN00, SN01)) } /** @@ -610,7 +694,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) 0x01, // 0x00: BIXRevision - Revision - Integer 0x01, // 0x01: BIXPowerUnit - Power Unit: mAh - Integer (DWORD) // ACPI spec : 0 - mWh : 1 - mAh - // We are always outputting mAh. 0xFFFFFFFF, // 0x02: BIXDesignCapacity - Design Capacity - Integer (DWORD) 0xFFFFFFFF, // 0x03: BIXLastFullChargeCapacity - Last Full Charge Capacity - Integer (DWORD) 0x01, // 0x04: BIXBatteryTechnology - Battery Technology: Rechargeable - Integer (DWORD) @@ -766,7 +849,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) Arg1 [0x05] = SBDV /* \_SB_.PCI0.LPCB.EC__.BATX.SBDV */ // Serial Number - Arg1 [0x11] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + Arg1 [0x11] = ToString (SBSN) /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ // @@ -811,7 +894,10 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) */ Method (_BIX, 0, NotSerialized) // _BIX: Battery Information Extended { - Debug = "BATX:_BIX" + If (BDBG == One) + { + Debug = "BATX:_BIX" + } // needs to be run in any way as it waits for the bat-device to be available BX0I = GBIX (0x00, PBIX) @@ -974,19 +1060,45 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) Local6 = HB1S } - // Not charging - Local0 = 0x00 - - If ((Local6 & 0x20) == 0x20) + If ((Local6 & 0x20)) { // 2 = Charging - Local0 = 0x02 + Local0 = 2 } - ElseIf ((Local6 & 0x40) == 0x40) + ElseIf ((Local6 & 0x40) ) { // 1 = Discharging - Local0 = 0x01 + Local0 = 1 } + Else + { + // 0 = Not charging / Full + Local0 = 0 + } + + // Set critical flag if battery is empty + If ((Local6 & 0x0F) == 0) + { + Local6 = Local6 | 0x04 + } + + Store (Zero, Local1) + + // Check if AC is present + If (HPAC) + { + // Set only charging/discharging bits + And (Local0, 0x03, Local1) + } + Else + { + // Always discharging when on battery power + Local0 = One + } + + // Flag if the battery level is critical + Local4 = Local0 & 0x04 + Local0 = Local1 | Local4 // @@ -1019,17 +1131,18 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) If ((Local1 >= 0x8000)) { // If discharging - If ((Local0 & 0x01) == 0x01) + If ((Local0 & 0x01)) { // Negate present rate Local1 = (0x00010000 - Local1) } Else { + // Error Local1 = 0x00 } } - ElseIf (!(Local0 & 0x02) == 0x02) + ElseIf (!(Local0 & 0x02)) { Local1 = 0x00 } @@ -1070,7 +1183,10 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) */ Method (_BST, 0, NotSerialized) // _BST: Battery Status { - Debug = "BATX:_BST()" + If (BDBG == One) + { + Debug = "BATX:_BST()" + } // Check if battery is added or removed Local3 = DerefOf (PBAI [0x00]) @@ -1146,18 +1262,18 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) Local4 = DerefOf (BT0P [0x00]) Local5 = DerefOf (BT1P [0x00]) - If (Local4 != Local5) + // Discharging + Local0 [0x00] = 0 + + If ((Local4 == 2) || (Local5 == 2)) { - If (((Local4 & 0x02) == 0x02) || ((Local5 & 0x02) == 0x02)) - { - // 2 = Charging - Local0 [0x00] = 0x02 - } - ElseIf (((Local4 & 0x01) == 0x01) || ((Local5 & 0x01) == 0x01)) - { - // 1 = Discharging - Local0 [0x00] = 0x01 - } + // 2 = Critical + Local0 [0x00] = 2 + } + ElseIf ((Local4 == 1) || (Local5 == 1)) + { + // 1 = Charging + Local0 [0x00] = 1 } // _BST 1 - Battery Present Rate - add BAT0 and BAT1 values @@ -1182,205 +1298,221 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) } - - /** - * Battery Status Supplement pack layout - */ - Name (PBSS, Package (0x07) + // Provide the API for `Battery Information Supplement` if enabled in configuration above + If (BBIS) { - 0xFFFFFFFF, // 0x00: BSSTemperature - Temperature, AppleSmartBattery format - 0xFFFFFFFF, // 0x01: BSSTimeToFull - TimeToFull [minutes] (0xFF) - 0xFFFFFFFF, // 0x02: BSSTimeToEmpty - TimeToEmpty [minutes] (0) - 0xFFFFFFFF, // 0x03: BSSChargeLevel - ChargeLevel [percent] - 0xFFFFFFFF, // 0x04: BSSAverageRate - AverageRate [mA] (signed) - 0xFFFFFFFF, // 0x05: BSSChargingCurrent - ChargingCurrent [mA] - 0xFFFFFFFF, // 0x06: BSSChargingVoltage - ChargingVoltage [mV] - }) - - Name (PBS0, Package (0x07) {}) - Name (PBS1, Package (0x07) {}) - - /** - * Get Battery Status Supplement per battery - * - * Arg0: Battery 0x00/0x10 - * Arg1: package - */ - Method (GBSS, 2, NotSerialized) - { - If (Acquire (BAXM, 65535)) + /** + * Battery Status Supplement pack layout + */ + Name (PBSS, Package (0x07) { - Debug = "BATX:AcquireLock failed in GBSS" + 0xFFFFFFFF, // 0x00: BSSTemperature - Temperature, AppleSmartBattery format + 0xFFFFFFFF, // 0x01: BSSTimeToFull - TimeToFull [minutes] (0xFF) + 0xFFFFFFFF, // 0x02: BSSTimeToEmpty - TimeToEmpty [minutes] (0) + 0xFFFFFFFF, // 0x03: BSSChargeLevel - ChargeLevel [percent] + 0xFFFFFFFF, // 0x04: BSSAverageRate - AverageRate [mA] (signed) + 0xFFFFFFFF, // 0x05: BSSChargingCurrent - ChargingCurrent [mA] + 0xFFFFFFFF, // 0x06: BSSChargingVoltage - ChargingVoltage [mV] + }) - Return (PBSS) + Name (PBS0, Package (0x07) {}) + Name (PBS1, Package (0x07) {}) + + /** + * Get Battery Status Supplement per battery + * + * Arg0: Battery 0x00/0x10 + * Arg1: package + */ + Method (GBSS, 2, NotSerialized) + { + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in GBSS" + + Return (PBSS) + } + + // + // Information Page 0 - + // + HIID = Arg0 + + // 0x01: TimeToFull (0x11), minutes (0xFF) + Local6 = SBAF + + If (Local6 == 0xFFFF) + { + Local6 = 0 + } + + Arg1 [0x01] = Local6 + + // 0x02: TimeToEmpty (0x12), minutes (0) + Local6 = SBAE + + If (Local6 == 0xFFFF) + { + Local6 = 0 + } + + Arg1 [0x02] = Local6 + + // 0x03: BSSChargeLevel - ChargeLevel, percentage + Arg1 [0x03] = SBRS + + // 0x04: AverageRate (0x14), mA (signed) + Arg1 [0x04] = SBAC + + // 0x05: ChargingCurrent (0x15), mA, seems to be unused anyways + // Arg1 [0x05] = ??? + + // 0x06: ChargingVoltage (0x16), mV, seems to be unused anyways + // Arg1 [0x06] = ??? + + // Fake Temperature (0x10) to 30C as it isn't available from the EC, AppleSmartBattery format + Arg1 [0x00] = 0xBD7 + + Release (BAXM) + + Return (Arg1) } - // - // Information Page 0 - - // - HIID = Arg0 - - // 0x01: TimeToFull (0x11), minutes (0xFF) - Local6 = SBAF - - If (Local6 == 0xFFFF) + /** + * Battery Status Supplement + */ + Method (CBSS, 0, NotSerialized) { - Local6 = 0 - } + If (BDBG == One) + { + Debug = "BATX:CBSS()" + } - Arg1 [0x01] = Local6 + If (!H8DR) + { + Return (PBSS) + } - // 0x02: TimeToEmpty (0x12), minutes (0) - Local6 = SBAE + If (HB0A) + { + PBS0 = GBSS (0x00, PBSS) - If (Local6 == 0xFFFF) - { - Local6 = 0 - } + If (BDBG == One) + { + Concatenate ("BATX:BSSTimeToFull: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x04])), Debug) + } - Arg1 [0x02] = Local6 + If (!HB1A) + { + Return (PBS0) + } + } - // 0x03: BSSChargeLevel - ChargeLevel, percentage - Arg1 [0x03] = SBRS - - // 0x04: AverageRate (0x14), mA (signed) - Arg1 [0x04] = SBAC - - // 0x05: ChargingCurrent (0x15), mA, seems to be unused anyways - // Arg1 [0x05] = ??? - - // 0x06: ChargingVoltage (0x16), mV, seems to be unused anyways - // Arg1 [0x06] = ??? - - // Fake Temperature (0x10) to 30C as it isn't available from the EC, AppleSmartBattery format - Arg1 [0x00] = 0xBD7 - - Release (BAXM) - - Return (Arg1) - } - - /** - * Battery Status Supplement - */ - Method (CBSS, 0, NotSerialized) - { - Debug = "BATX:CBSS()" - - If (!H8DR) - { - Return (PBSS) - } - - If (HB0A) - { - PBS0 = GBSS (0x00, PBSS) + // gather battery data from BAT1 + PBS1 = GBSS (0x10, PBSS) If (BDBG == One) { - Concatenate ("BATX:BSSTimeToFull: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x01])), Debug) - Concatenate ("BATX:BSSTimeToEmpty: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x02])), Debug) - Concatenate ("BATX:BSSChargeLevel: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x03])), Debug) - Concatenate ("BATX:BSSAverageRate: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x04])), Debug) + Concatenate ("BATX:BSSTimeToFull: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x04])), Debug) } - If (!HB1A) + If (!HB0A) { - Return (PBS0) + Return (PBS1) } + + // combine batteries into Local0 result if possible + Local0 = PBS0 + + // 0x01: TimeToFull (0x11), minutes (0xFF), Valid integer in minutes + Local0 [0x01] = (DerefOf (PBS0 [0x01]) + DerefOf (PBS1 [0x01])) + + // 0x02: BSSTimeToEmpty - TimeToEmpty, minutes (0), Valid integer in minutes + Local0 [0x02] = (DerefOf (PBS0 [0x02]) + DerefOf (PBS1 [0x02])) + + // 0x03: BSSChargeLevel - ChargeLevel, percentage, 0 - 100 for percentage. + Local0 [0x03] = (DerefOf (PBS0 [0x03]) + DerefOf (PBS1 [0x03])) / 2 + + // 0x04: BSSAverageRate - AverageRate, mA (signed), Valid signed integer in mA. + Local0 [0x04] = (DerefOf (PBS0 [0x04]) + DerefOf (PBS1 [0x04])) + + If (BDBG == One) + { + Concatenate ("BATX:BSSTimeToFull: BATX ", ToDecimalString (DerefOf (Local0 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BATX ", ToDecimalString (DerefOf (Local0 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BATX ", ToDecimalString (DerefOf (Local0 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BATX ", ToDecimalString (DerefOf (Local0 [0x04])), Debug) + } + + Return (Local0) } - // gather battery data from BAT1 - PBS1 = GBSS (0x10, PBSS) - If (BDBG == One) + + /** + * Battery Information Supplement pack layout + */ + Name (PBIS, Package (0x07) { - Concatenate ("BATX:BSSTimeToFull: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x01])), Debug) - Concatenate ("BATX:BSSTimeToEmpty: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x02])), Debug) - Concatenate ("BATX:BSSChargeLevel: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x03])), Debug) - Concatenate ("BATX:BSSAverageRate: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x04])), Debug) - } + 0x007F007F, // 0x00: BISConfig - config + // double check if you have valid AverageRate before disabling QuicPoll + // - 0x007F007F - Quickpoll disabled, more native battery handling + // - 0x006F007F - Quickpoll enabled, more robust battery handling + 0xFFFFFFFF, // 0x01: BISManufactureDate - ManufactureDate (0x1), AppleSmartBattery format + 0x00002342, // 0x02: BISPackLotCode - PackLotCode + 0x00002342, // 0x03: BISPCBLotCode - PCBLotCode + 0x00002342, // 0x04: BISFirmwareVersion - FirmwareVersion + 0x00002342, // 0x05: BISHardwareVersion - HardwareVersion + 0x00002342, // 0x06: BISBatteryVersion - BatteryVersion + }) - If (!HB0A) + /** + * Battery Information Supplement + */ + Method (CBIS, 0, NotSerialized) { - Return (PBS1) - } + If (BDQP == One) + { + PBIS[0x00] = 0x006F007F + } - // combine batteries into Local0 result if possible - Local0 = PBS0 + If (BDBG == One) + { + Debug = "BATX:CBIS()" + } - // 0x01: TimeToFull (0x11), minutes (0xFF), Valid integer in minutes - Local0 [0x01] = (DerefOf (PBS0 [0x01]) + DerefOf (PBS1 [0x01])) + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in CBIS" - // 0x02: BSSTimeToEmpty - TimeToEmpty, minutes (0), Valid integer in minutes - Local0 [0x02] = (DerefOf (PBS0 [0x02]) + DerefOf (PBS1 [0x02])) + Return (PBIS) + } - // 0x03: BSSChargeLevel - ChargeLevel, percentage, 0 - 100 for percentage. - Local0 [0x03] = (DerefOf (PBS0 [0x03]) + DerefOf (PBS1 [0x03])) / 2 + // + // Information Page 2 - + // + HIID = (0x00 | 0x02) - // 0x04: BSSAverageRate - AverageRate, mA (signed), Valid signed integer in mA. - Local0 [0x04] = (DerefOf (PBS0 [0x04]) + DerefOf (PBS1 [0x04])) + // 0x01: ManufactureDate (0x1), AppleSmartBattery format + PBIS [0x01] = SBDT - If (BDBG == One) - { - Concatenate ("BATX:BSSTimeToFull: BATX ", ToDecimalString (DerefOf (Local0 [0x01])), Debug) - Concatenate ("BATX:BSSTimeToEmpty: BATX ", ToDecimalString (DerefOf (Local0 [0x02])), Debug) - Concatenate ("BATX:BSSChargeLevel: BATX ", ToDecimalString (DerefOf (Local0 [0x03])), Debug) - Concatenate ("BATX:BSSAverageRate: BATX ", ToDecimalString (DerefOf (Local0 [0x04])), Debug) - } + // Serial Number + PBIS [0x02] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + PBIS [0x03] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + PBIS [0x04] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + PBIS [0x05] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + PBIS [0x06] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ - Return (Local0) - } - - - - /** - * Battery Information Supplement pack layout - */ - Name (PBIS, Package (0x07) - { - // 0x006F007F, // 0x00: BISConfig - config, double check if you have valid AverageRate before - // fliping that bit to 0x007F007F since it will disable quickPoll - 0x007F007F, // disable quickpoll - 0xFFFFFFFF, // 0x01: BISManufactureDate - ManufactureDate (0x1), AppleSmartBattery format - 0x00002342, // 0x02: BISPackLotCode - PackLotCode - 0x00002342, // 0x03: BISPCBLotCode - PCBLotCode - 0x00002342, // 0x04: BISFirmwareVersion - FirmwareVersion - 0x00002342, // 0x05: BISHardwareVersion - HardwareVersion - 0x00002342, // 0x06: BISBatteryVersion - BatteryVersion - }) - - /** - * Battery Information Supplement - */ - Method (CBIS, 0, NotSerialized) - { - Debug = "BATX:CBIS()" - - If (!H8DR) - { - Return (PBIS) - } - - If (Acquire (BAXM, 65535)) - { - Debug = "BATX:AcquireLock failed in CBIS" + Release (BAXM) Return (PBIS) } - - - // - // Information Page 2 - - // - HIID = (0x00 | 0x02) - - // 0x01: ManufactureDate (0x1), AppleSmartBattery format - PBIS [0x01] = SBDT - - Release (BAXM) - - Return (PBIS) } } } diff --git a/patches/SSDT-DMAC.dsl b/patches/SSDT-DMAC.dsl index b081ab5..11a88f3 100755 --- a/patches/SSDT-DMAC.dsl +++ b/patches/SSDT-DMAC.dsl @@ -36,26 +36,5 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_DMAC", 0x00001000) Return (Zero) } } - - /* FPU / MATH */ - Device(MAT0) - { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } - }) - - Method (_STA, 0, NotSerialized) - { - If (OSDW ()) - { - Return (0x0F) - } - - Return (Zero) - } - } } -} \ No newline at end of file +} diff --git a/patches/SSDT-HWAC.dsl b/patches/SSDT-HWAC.dsl index 96bb97f..ecec434 100644 --- a/patches/SSDT-HWAC.dsl +++ b/patches/SSDT-HWAC.dsl @@ -1,4 +1,6 @@ /* + * Depends on /patches/OpenCore Patches/ HWAC.plist + * * On many modern hackintoshed thinkpads there are ofthen accesses to the 16-bit EC-field `HWAC`, which are mostly * not handled by battery-patches (f.e. those currated by @daliansky). Those accesses are (mostly) located in the _OWAK() * and/or _L17-ACPI-methods of the original DSDT. @@ -26,7 +28,6 @@ * This includes 16, 32, 64, and larger fields.` * - @Rehabman, https://www.tonymacx86.com/threads/guide-how-to-patch-dsdt-for-working-battery-status.116102/ * - * Depends on /patches/OpenCore Patches/ HWAC.plist */ @@ -37,9 +38,9 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_HWAC", 0x00001000) Scope (\_SB.PCI0.LPCB.EC) { - // - // EC region overlay. - // + /** + * EC region overlay. + */ OperationRegion (ERAM, EmbeddedControl, 0x00, 0x0100) Field (ERAM, ByteAcc, NoLock, Preserve) { diff --git a/patches/SSDT-INIT.dsl b/patches/SSDT-INIT.dsl index b92ba66..11ab6b8 100644 --- a/patches/SSDT-INIT.dsl +++ b/patches/SSDT-INIT.dsl @@ -1,3 +1,5 @@ +// Depends on /patches/OpenCore Patches/ INIT.plist +// /* Source: https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl // @@ -43,27 +45,57 @@ Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port selector Offset(84), BDID, 8, // Offset(84), Board ID */ +// // Credits @benbender DefinitionBlock ("", "SSDT", 2, "tyler", "_INIT", 0x00001000) { - External (OSDW, MethodObj) // 0 Arguments + // External method from SSDT-Darwin.dsl + External (OSDW, MethodObj) // 0 Arguments + External (_SB.PCI0, DeviceObj) + + // System External (HPTE, FieldUnitObj) // HPET enabled? External (WNTF, FieldUnitObj) // DYTC enabled? External (DPTF, FieldUnitObj) // DPTF enabled? + External (OSYS, FieldUnitObj) // OS type - If (OSDW ()) + External (ZINI, MethodObj) + + // Thunderbolt + External (_SB.PCI0.RP09.INIT, MethodObj) + + + Scope (\_SB.PCI0) { - Debug = "INIT: Set Variables..." + Method (OINI, 0, NotSerialized) + { + If (OSDW()) + { + Debug = "INIT: Set Variables..." - // Disable HPET. It shouldn't be needed on modern systems anyway and is also disabled in genuine OSX - HPTE = Zero + // disable HPET. It shouldn't be needed on modern systems anyway and is also disabled in genuine OSX + HPTE = Zero - // Enables DYTC, Lenovos thermal solution. Can be controlled by YogaSMC - WNTF = One + // Enables DYTC, Lenovos thermal solution. Can be controlled by YogaSMC + WNTF = One - // Disable DPTF, we use DYTC! - DPTF = Zero + // Disable DPTF, we use DYTC! + DPTF = Zero + + // Patch OSYS to native value of darwin + OSYS = 0x07DF + } + + ZINI () + + // Thunderbolt-setup + If (OSDW () && CondRefOf (\_SB.PCI0.RP09.INIT)) + { + \_SB.PCI0.RP09.INIT () + } + } } -} \ No newline at end of file +} +//EOF diff --git a/patches/SSDT-Keyboard-Legacy.dsl b/patches/SSDT-Keyboard-Legacy.dsl deleted file mode 100644 index d68cfa7..0000000 --- a/patches/SSDT-Keyboard-Legacy.dsl +++ /dev/null @@ -1,327 +0,0 @@ -/* - * For use with ThinkpadAssistant (would need ACPI renames: /patches/OpenCore Patches/ Keyboard-Legacy.plist) - * https://github.com/MSzturc/ThinkpadAssistant - * - */ - -DefinitionBlock("", "SSDT", 2, "tyler", "_KBD", 0) -{ - External (OSDW, MethodObj) - External (_SB.PCI0.LPCB.KBD, DeviceObj) - External (_SB.PCI0.LPCB.EC, DeviceObj) - External (_SB.PCI0.LPCB.EC.XQ74, MethodObj) // FnLock - External (_SB.PCI0.LPCB.EC.XQ6A, MethodObj) // F4 - Mic Mute - External (_SB.PCI0.LPCB.EC.XQ15, MethodObj) // F5 - External (_SB.PCI0.LPCB.EC.XQ14, MethodObj) // F6 - External (_SB.PCI0.LPCB.EC.XQ16, MethodObj) // F7 - External (_SB.PCI0.LPCB.EC.XQ64, MethodObj) // F8 - External (_SB.PCI0.LPCB.EC.XQ66, MethodObj) // F9 - External (_SB.PCI0.LPCB.EC.XQ60, MethodObj) // F10 - External (_SB.PCI0.LPCB.EC.XQ61, MethodObj) // F11 - External (_SB.PCI0.LPCB.EC.XQ62, MethodObj) // F12 - External (_SB.PCI0.LPCB.EC.XQ1F, MethodObj) // Keyboard Backlight (Fn+Space) - External (_SB.PCI0.LPCB.EC.HKEY.MHKQ, MethodObj) // FnLock LED - External (_SB.PCI0.LPCB.EC.HKEY.MMTS, MethodObj) // F4 - Mic Mute LED - External (_SB.PCI0.LPCB.EC.HKEY.MLCS, MethodObj) // Keyboard Backlight LED - - Scope (_SB.PCI0.LPCB.EC) - { - Name (FUNL, Zero) // FnLock LED - Method (_Q74, 0, NotSerialized) // FnLock (Fn + Esc) - { - If (OSDW ()) - { - FUNL = (FUNL + 1) % 2 - Switch (FUNL) - { - Case (One) - { - // Right Shift + F18 - Notify (KBD, 0x012A) - Notify (KBD, 0x0369) - Notify (KBD, 0x01aa) - - // Enable LED - \_SB.PCI0.LPCB.EC.HKEY.MHKQ (0x02) - } - Case (Zero) - { - // Left Shift + F18 - Notify (KBD, 0x0136) - Notify (KBD, 0x0369) - Notify (KBD, 0x01b6) - - // Disable LED - \_SB.PCI0.LPCB.EC.HKEY.MHKQ (Zero) - } - } - } - Else - { - // Call original _Q74 method. - XQ74() - } - } - - Name (MICL, Zero) // F4 - Mic Mute LED - Method (_Q6A, 0, NotSerialized) // F4 - Microphone Mute = F20 - { - If (OSDW ()) - { - MICL = (MICL + 1) % 2 - Switch (MICL) - { - Case (One) - { - // Right Shift + F20 - Notify (KBD, 0x0136) - Notify (KBD, 0x036B) - Notify (KBD, 0x01b6) - - // Enable LED - \_SB.PCI0.LPCB.EC.HKEY.MMTS (0x02) - } - Case (Zero) - { - // Left Shift + F20 - Notify (KBD, 0x012A) - Notify (KBD, 0x036B) - Notify (KBD, 0x01aa) - - // Disable LED - \_SB.PCI0.LPCB.EC.HKEY.MMTS (Zero) - } - } - } - Else - { - // Call original _Q6A method. - XQ6A() - } - } - - Method (_Q15, 0, NotSerialized) // F5 - Brightness Down = F14 - { - If (OSDW ()) - { - Notify(KBD, 0x0405) - Notify(KBD, 0x20) // Reserved - } - Else - { - // Call original _Q15 method. - XQ15() - } - } - - Method (_Q14, 0, NotSerialized) // F6 - Brightness Up = F15 - { - If (OSDW ()) - { - Notify(KBD, 0x0406) - Notify(KBD, 0x10) // Reserved - } - Else - { - // Call original _Q14 method. - XQ14() - } - } - - Method (_Q16, 0, NotSerialized) // F7 - Dual Display = F16 - { - If (OSDW ()) - { - Notify(KBD, 0x0367) - } - Else - { - // Call original _Q16 method. - XQ16() - } - } - - Method (_Q64, 0, NotSerialized) // F8 - Network = F17 - { - If (OSDW ()) - { - Notify(KBD, 0x0368) - } - Else - { - // Call original _Q64 method. - XQ64() - } - } - - Method (_Q66, 0, NotSerialized) // F9 - Settings = F18 - { - If (OSDW ()) - { - Notify(KBD, 0x0369) - } - Else - { - // Call original _Q66 method. - XQ66() - } - } - - Method (_Q60, 0, NotSerialized) // F10 - Bluetooth - { - - If (OSDW ()) - { - // Left Shift + F17 - Notify (KBD, 0x012A) - Notify (KBD, 0x0368) - Notify (KBD, 0x01AA) - } - Else - { - // Call original _Q60 method. - XQ60() - } - } - - Method (_Q61, 0, NotSerialized) // F11 - Keyboard - { - If (OSDW ()) - { - // Send a down event for the Control key (scancode 1d), then a one-shot event (down then up) for - // the up arrow key (scancode 0e 48), and finally an up event for the Control key (break scancode 9d). - // This is picked up by VoodooPS2 and sent to macOS as the Control+Up key combo. - Notify (KBD, 0x011D) - Notify (KBD, 0x0448) - Notify (KBD, 0x019D) - } - Else - { - // Call original _Q61 method. - XQ61() - } - } - - Method (_Q62, 0, NotSerialized) // F12 - Star = F19 - { - If (OSDW ()) - { - Notify(KBD, 0x036A) - } - Else - { - // Call original _Q62 method. - XQ62() - } - } - - Name (KEYL, Zero) // Keyboard Backlight LED (Fn+Space) - Method (_Q1F, 0, NotSerialized) // cycle keyboard backlight - { - If (OSDW ()) - { - KEYL = (KEYL + 1) % 3 - Switch (KEYL) - { - Case (Zero) - { - // Left Shift + F16. - Notify (KBD, 0x012a) - Notify (KBD, 0x0367) - Notify (KBD, 0x01aa) - - // Bright --> Off - \_SB.PCI0.LPCB.EC.HKEY.MLCS (Zero) - } - Case (One) - { - // Right Shift + F16. - Notify (KBD, 0x0136) - Notify (KBD, 0x0367) - Notify (KBD, 0x01b6) - - // Off --> Dim - \_SB.PCI0.LPCB.EC.HKEY.MLCS (One) - } - Case (0x02) - { - // Left Shift + F19. - Notify (KBD, 0x012a) - Notify (KBD, 0x036a) - Notify (KBD, 0x01aa) - - // Dim --> Bright - \_SB.PCI0.LPCB.EC.HKEY.MLCS (0x02) - } - } - } - Else - { - // Call original _Q1F method. - XQ1F() - } - } - - } - - Scope (_SB.PCI0.LPCB.KBD) - { - Method(_DSM, 4) - { - If (!Arg2) { Return (Buffer() { 0x03 } ) } - Return (Package() - { - "RM,oem-id", "LENOVO", - "RM,oem-table-id", "Thinkpad_ClickPad", - }) - } - - // Overrides (the example data here is default in the Info.plist) - Name(RMCF, Package() - { - "Synaptics TouchPad", Package() - { - "BogusDeltaThreshX", 800, - "BogusDeltaThreshY", 800, - "Clicking", ">y", - "DragLockTempMask", 0x40004, - "DynamicEWMode", ">n", - "FakeMiddleButton", ">n", - "HWResetOnStart", ">y", - //"ForcePassThrough", ">y", - //"SkipPassThrough", ">y", - "PalmNoAction When Typing", ">y", - "ScrollResolution", 800, - "SmoothInput", ">y", - "UnsmoothInput", ">y", - "Thinkpad", ">y", - "EdgeBottom", 0, - "FingerZ", 30, - "MaxTapTime", 100000000, - "MouseMultiplierX", 2, - "MouseMultiplierY", 2, - "MouseScrollMultiplierX", 2, - "MouseScrollMultiplierY", 2, - //"TrackpointScrollYMultiplier", 1, //Change this value to 0xFFFF in order to inverse the vertical scroll direction of the Trackpoint when holding the middle mouse button. - //"TrackpointScrollXMultiplier", 1, //Change this value to 0xFFFF in order to inverse the horizontal scroll direction of the Trackpoint when holding the middle mouse button. - }, - - "Keyboard", Package() - { - "Custom PS2 Map", Package() - { - Package() { }, - "e037=64", // PrtSc = F13 - "46=80", // Fn + K = Deadkey - "e045=80", // Fn + P = Deadkey - "38=e05b", // Left Alt (mismapped to Left GUI by default) = Left Alt - "e038=e05c", // Right Alt (mismapped to Right GUI by default) = Right Alt - "e05b=38", // Windows (mismapped to Left Alt by default) = Left GUI - // "1d=80", // Fn + B = Deadkey - // "54=80", // Fn + S = Deadkey - }, - }, - }) - } -} -//EOF \ No newline at end of file diff --git a/patches/SSDT-Keyboard.dsl b/patches/SSDT-Keyboard.dsl index 8340190..974226a 100644 --- a/patches/SSDT-Keyboard.dsl +++ b/patches/SSDT-Keyboard.dsl @@ -1,7 +1,9 @@ /* - * For use with BrightnessKeys.kext and YogaSMC + * For use with BrightnessKeys.kext, YogaSMC, and VoodooRMI * https://github.com/zhen-zen/YogaSMC * + * For more customizations, refer to YogaSMCPrefPane, VoodooRMI's info.plist + * and/or third party software such as BetterTouchTool or Karabiner-Elements. */ DefinitionBlock("", "SSDT", 2, "tyler", "_KBD", 0) @@ -10,46 +12,8 @@ DefinitionBlock("", "SSDT", 2, "tyler", "_KBD", 0) Scope (_SB.PCI0.LPCB.KBD) { - Method(_DSM, 4) - { - If (!Arg2) { Return (Buffer() { 0x03 } ) } - Return (Package() - { - "RM,oem-id", "LENOVO", - "RM,oem-table-id", "Thinkpad_ClickPad", - }) - } - - // Overrides (the example data here is default in the Info.plist) Name(RMCF, Package() { - "Synaptics TouchPad", Package() - { - "BogusDeltaThreshX", 800, - "BogusDeltaThreshY", 800, - "Clicking", ">y", - "DragLockTempMask", 0x40004, - "DynamicEWMode", ">n", - "FakeMiddleButton", ">n", - "HWResetOnStart", ">y", - //"ForcePassThrough", ">y", - //"SkipPassThrough", ">y", - "PalmNoAction When Typing", ">y", - "ScrollResolution", 800, - "SmoothInput", ">y", - "UnsmoothInput", ">y", - "Thinkpad", ">y", - "EdgeBottom", 0, - "FingerZ", 30, - "MaxTapTime", 100000000, - "MouseMultiplierX", 2, - "MouseMultiplierY", 2, - "MouseScrollMultiplierX", 2, - "MouseScrollMultiplierY", 2, - //"TrackpointScrollYMultiplier", 1, //Change this value to 0xFFFF in order to inverse the vertical scroll direction of the Trackpoint when holding the middle mouse button. - //"TrackpointScrollXMultiplier", 1, //Change this value to 0xFFFF in order to inverse the horizontal scroll direction of the Trackpoint when holding the middle mouse button. - }, - "Keyboard", Package() { "Custom PS2 Map", Package() diff --git a/patches/SSDT-TB3.dsl b/patches/SSDT-TB3.dsl index 7766d9f..797b8d5 100644 --- a/patches/SSDT-TB3.dsl +++ b/patches/SSDT-TB3.dsl @@ -1,12 +1,20 @@ +// // Depends on /patches/OpenCore Patches/ Thunderbolt3.plist +// /** * Thunderbolt For Alpine Ridge on X1C6 * * Large parts (link training and enumeration) * taken from decompiled Mac AML. * - * Implements mostly of the ACPI-part for handling Thunderbolt 3 on an Lenovo X1C6. Does power management and force power management for TB & USB 3.1. + * Implements mostly of the ACPI-part for handling Thunderbolt 3 on an Lenovo X1C6. Does power management for TB. + * + * This SSDT expects an unpatched controller in "windows native mode with RTD3" aka disabled "BIOS assist". It will silently disable itself on "bios-assist". + * + * It enables not only the PCIe-to-PCIe-bridge mode of the TB controller but the native drivers incl. power-management. + * The controller is visible in SysInfo and the ICM is disabled on boot to let OSX' drivers take over the job. + * * WIP but should be complete now. And full of bugs. Its largely untested. Intended to give a mostly complete and as native as possible experience. - * Pair with SSDT-XHC1.dsl (native USB 2.0/3.0), SSDT-XHC2.dsl (USB 3.1) & SSDT-PTS.dsl (handling sleep). + * Pair with SSDT-XHC1.dsl (native USB 2.0/3.0), SSDT-XHC2.dsl (USB 3.1 Gen2), SSDT-INIT.dsl (boot-time init) & SSDT-PTS.dsl (handling sleep). * See config.plist for details. * * Copyright (c) 2019 osy86 @@ -18,67 +26,80 @@ * Platform-reference: https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/AcpiTables * osy86-implementation: https://github.com/osy86/HaC-Mini/blob/master/ACPI/SSDT-TbtOnPCH.asl */ -DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) +// +// Credits @benbeder + +DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00002000) { - /* Support methods */ - External (DTGP, MethodObj) // 5 Arguments - // OS Is Darwin? - External (OSDW, MethodObj) // 0 Arguments + // Common utils from SSDT-Darwin.dsl + External (DTGP, MethodObj) // 5 Arguments + External (OSDW, MethodObj) // 0 Arguments - /* Patching existing devices */ - External (\_SB.PCI0.RP09, DeviceObj) - External (\_SB.PCI0.RP09.LEDM, FieldUnitObj) - External (\_SB.PCI0.RP09.L23E, FieldUnitObj) - External (\_SB.PCI0.RP09.L23R, FieldUnitObj) - External (\_SB.PCI0.RP09.LDIS, FieldUnitObj) - External (\_SB.PCI0.RP09.PXSX, DeviceObj) - External (\_SB.PCI0.RP09.PXSX.TBDU, DeviceObj) - External (\_SB.PCI0.XHC1, DeviceObj) + External (_SB.PCI0.RP09, DeviceObj) // PCIe-port + External (_SB.PCI0.RP09.PXSX, DeviceObj) // original PCIe-bridge + External (_SB.PCI0.RP09.XINI, MethodObj) // original _INI patched by OC + External (_SB.PCI0.RP09.XPS0, MethodObj) // original _PS0 patched by OC + External (_SB.PCI0.RP09.XPS3, MethodObj) // original _PS3 patched by OC + External (_SB.PCI0.XHC, DeviceObj) // USB2/3 device - External (\_SB.PCI0.RP09.XINI, MethodObj) // original _INI patched by OC - External (\_SB.PCI0.RP09.XPS0, MethodObj) // original _PS0 patched by OC - External (\_SB.PCI0.RP09.XPS3, MethodObj) // original _PS3 patched by OC + External (_SB.PCI0.GPCB, MethodObj) // 0 Arguments + + External (_GPE.TBFF, MethodObj) // detect TB root port + External (_GPE.TFPS, MethodObj) // TB force status + External (_GPE.XTFY, MethodObj) // Notify TB-controller on hotplug + External (_SB.TBFP, MethodObj) // 1 Arguments + External (FFTB, MethodObj) // Detect TB powered on + External (MMRP, MethodObj) // Memory mapped root port + External (MMTB, MethodObj) // Memory mapped TB port + + External (OSUM, MutexObj) // OSUP mutex + + External (_SB.PCI0.RP09.VDID, FieldUnitObj) External (_SB.PCI0.RP09.UPSB.DSB2.XHC2, DeviceObj) External (_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND, FieldUnitObj) - // get PCI MMIO base - External (_SB.PCI0.GPCB, MethodObj) - // Get GPI Input Value - External (_SB_.GGII, MethodObj) // 1 Arguments - // Set GPI Input Value - External (_SB_.SGII, MethodObj) // 2 Arguments - // Get GPO Output Value - External (_SB_.GGOV, MethodObj) // 1 Arguments - // Set GPO Output Value - External (_SB_.SGOV, MethodObj) // 2 Arguments - // Get GPIO group index for GpioPad - External (GGRP, MethodObj) // 1 Arguments - // Get GPIO pin number for GpioPad - External (GNMB, MethodObj) // 1 Arguments - // Get GPIO register address - // This is internal library function - External (GADR, MethodObj) // 2 Arguments - // Memory mapped root port - External (MMRP, MethodObj) // 1 Arguments - // Memory mapped TB port - External (MMTB, MethodObj) // 1 Arguments + External (TNAT, FieldUnitObj) // Native hot plug + External (TBSF, FieldUnitObj) + External (SOHP, FieldUnitObj) // SMI on Hot Plug + External (TWIN, FieldUnitObj) // TB Windows native mode + External (GP5F, FieldUnitObj) + External (NOHP, FieldUnitObj) // Notify HotPlug + External (TBSE, FieldUnitObj) // TB root port number + External (WKFN, FieldUnitObj) + External (TBTS, IntObj) // TB enabled + External (TARS, FieldUnitObj) + External (FPEN, FieldUnitObj) + External (FPG1, FieldUnitObj) + External (FP1L, FieldUnitObj) + External (CPGN, FieldUnitObj) // CIO Hotplug GPIO + External (CPG1, FieldUnitObj) + External (TRWA, FieldUnitObj) + External (TBOD, FieldUnitObj) + External (TSXW, FieldUnitObj) + External (RTBT, IntObj) // Runtime D3 on TB enabled + External (RTBC, FieldUnitObj) + External (TBCD, FieldUnitObj) + External (USME, FieldUnitObj) + External (UWAB, FieldUnitObj) + External (USBP, FieldUnitObj) + External (USTC, FieldUnitObj) + External (TBAS, FieldUnitObj) - External (TBSE, FieldUnitObj) // TB root port number - External (TBTS, FieldUnitObj) // TB enabled? - External (XLTP, IntObj) - - External (_GPE.XTFY, MethodObj) // 1 Arguments + External (XLTP, IntObj) // DeepSleep ACPI-S0 Scope (\_GPE) { Method (NTFY, 1, Serialized) { - If (OSDW ()) - { - Debug = "TB:_GPE:NTFY()" + Debug = "TB:_GPE:NTFY" - \_SB.PCI0.RP09.UPSB.AMPE () + // Patch only if in windows native mode and OSX + If (OSDW () && (\TWIN != Zero) && (NOHP == 0x01) && Arg0 == 0x09) + { + Debug = "TB:_GPE:NTFY() - call AMPE ()" + + \_SB.PCI0.RP09.UPSB.AMPE () // Notify UPSB } Else { @@ -87,1371 +108,1427 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) } } - Scope (\_SB) + + If (\TBTS == One) { - Method (SGDI, 1, Serialized) - { - Local0 = GGRP (Arg0) - Local1 = GNMB (Arg0) - Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) - OperationRegion (PDW0, SystemMemory, Local2, 0x04) - Field (PDW0, AnyAcc, NoLock, Preserve) - { - Offset (0x01), - TEMP, 2, - Offset (0x04) - } - - TEMP = One - } - - Method (SGDO, 1, Serialized) - { - Local0 = GGRP (Arg0) - Local1 = GNMB (Arg0) - Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) - OperationRegion (PDW0, SystemMemory, Local2, 0x04) - Field (PDW0, AnyAcc, NoLock, Preserve) - { - Offset (0x01), - TEMP, 2, - Offset (0x04) - } - - TEMP = 0x02 - } - - Method (GGDV, 1, Serialized) - { - Local0 = GGRP (Arg0) - Local1 = GNMB (Arg0) - Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) - OperationRegion (PDW0, SystemMemory, Local2, 0x04) - Field (PDW0, AnyAcc, NoLock, Preserve) - { - Offset (0x01), - TEMP, 2, - Offset (0x04) - } - - If (TEMP == One) - { - Return (One) - } - ElseIf (TEMP == 0x02) - { - Return (Zero) - } - Else - { - Return (One) - } - } - - } - - Scope (\_SB.PCI0.RP09) - { - Name (EICM, Zero) - Name (R020, Zero) // RP base/limit from UEFI - Name (R024, Zero) // RP prefetch base/limit from UEFI - Name (R028, Zero) - Name (R02C, Zero) - - Name (R118, Zero) // UPSB Pri Bus = RP Sec Bus (UEFI) - Name (R119, Zero) // UPSB Sec Bus = RP Sec Bus + 1 - Name (R11A, Zero) // UPSB Sub Bus = RP Sub Bus (UEFI) - Name (R11C, Zero) // UPSB IO base/limit = RP IO base/limit (UEFI) - Name (R120, Zero) // UPSB mem base/limit = RP mem base/limit (UEFI) - Name (R124, Zero) // UPSB pre base/limit = RP pre base/limit (UEFI) - Name (R128, Zero) - Name (R12C, Zero) - - Name (R218, Zero) // DSB0 Pri Bus = UPSB Sec Bus - Name (R219, Zero) // DSB0 Sec Bus = UPSB Sec Bus + 1 - Name (R21A, Zero) // DSB0 Sub Bus = UPSB Sub Bus - Name (R21C, Zero) // DSB0 IO base/limit = UPSB IO base/limit - Name (R220, Zero) // DSB0 mem base/limit = UPSB mem base/limit - Name (R224, Zero) // DSB0 pre base/limit = UPSB pre base/limit - Name (R228, Zero) - Name (R22C, Zero) - - Name (R318, Zero) // DSB1 Pri Bus = UPSB Sec Bus - Name (R319, Zero) // DSB1 Sec Bus = UPSB Sec Bus + 2 - Name (R31A, Zero) // DSB1 Sub Bus = no children - Name (R31C, Zero) // DSB1 disable IO - Name (R320, Zero) // DSB1 disable mem - Name (R324, Zero) // DSB1 disable prefetch - Name (R328, Zero) - Name (R32C, Zero) - - Name (R418, Zero) // DSB2 Pri Bus = UPSB Sec Bus - Name (R419, Zero) // DSB2 Sec Bus = UPSB Sec Bus + 3 - Name (R41A, Zero) // DSB2 Sub Bus = no children - Name (R41C, Zero) // DSB2 disable IO - Name (R420, Zero) // DSB2 disable mem - Name (R424, Zero) // DSB2 disable prefetch - Name (R428, Zero) - Name (R42C, Zero) - - Name (RVES, Zero) // DSB2 offset 0x564, unknown - Name (R518, Zero) // DSB4 Pri Bus = UPSB Sec Bus - Name (R519, Zero) // DSB4 Sec Bus = UPSB Sec Bus + 4 - Name (R51A, Zero) // DSB4 Sub Bus = no children - Name (R51C, Zero) // DSB4 disable IO - Name (R520, Zero) // DSB4 disable mem - Name (R524, Zero) // DSB4 disable prefetch - Name (R528, Zero) - Name (R52C, Zero) - - Name (R618, Zero) - Name (R619, Zero) - Name (R61A, Zero) - Name (R61C, Zero) - Name (R620, Zero) - Name (R624, Zero) - Name (R628, Zero) - Name (R62C, Zero) - - Name (RH10, Zero) // NHI0 BAR0 = DSB0 mem base - Name (RH14, Zero) // NHI0 BAR1 unused - Name (POC0, Zero) - - Name (TBH1, Zero) - Name (BICM, Zero) // Boot windows? - - /** - * Get PCI base address - * Arg0 = bus, Arg1 = device, Arg2 = function - */ - Method (MMIO, 3, NotSerialized) - { - Local0 = \_SB.PCI0.GPCB () // base address - Local0 += (Arg0 << 20) - Local0 += (Arg1 << 15) - Local0 += (Arg2 << 12) - Return (Local0) - } - - // OperationRegion (RSTR, SystemMemory, NHI1, 0x0100) - OperationRegion (RSTR, SystemMemory, NH10 + 0x39858, 0x0100) - Field (RSTR, DWordAcc, NoLock, Preserve) - { - CIOR, 32, - Offset (0xB8), - ISTA, 32, - Offset (0xF0), - ICME, 32 - } - - // OperationRegion (T2PM, SystemMemory, T2P1, 0x08) - // Field (T2PM, DWordAcc, NoLock, Preserve) + // Scope (_SB) // { - // T2PR, 32, - // P2TR, 32 + // Method (GGDV, 1, Serialized) + // { + // Local0 = GGRP (Arg0) + // Local1 = GNMB (Arg0) + // Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + // OperationRegion (PDW0, SystemMemory, Local2, 0x04) + // Field (PDW0, AnyAcc, NoLock, Preserve) + // { + // Offset (0x01), + // TEMP, 2, + // Offset (0x04) + // } + + // If (TEMP == One) + // { + // Return (One) + // } + // ElseIf (TEMP == 0x02) + // { + // Return (Zero) + // } + // Else + // { + // Return (One) + // } + // } + + // Method (SGDI, 1, Serialized) + // { + // Local0 = GGRP (Arg0) + // Local1 = GNMB (Arg0) + // Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + // OperationRegion (PDW0, SystemMemory, Local2, 0x04) + // Field (PDW0, AnyAcc, NoLock, Preserve) + // { + // Offset (0x01), + // TEMP, 2, + // Offset (0x04) + // } + + // TEMP = One + // } + + // Method (SGDO, 1, Serialized) + // { + // Local0 = GGRP (Arg0) + // Local1 = GNMB (Arg0) + // Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + // OperationRegion (PDW0, SystemMemory, Local2, 0x04) + // Field (PDW0, AnyAcc, NoLock, Preserve) + // { + // Offset (0x01), + // TEMP, 2, + // Offset (0x04) + // } + + // TEMP = 0x02 + // } // } - // OperationRegion (RPSM, SystemMemory, 0xE00E4000, 0x54) - // Root port configuration base - OperationRegion (RPSM, SystemMemory, MMRP (TBSE), 0x54) - Field (RPSM, DWordAcc, NoLock, Preserve) + Scope (\_SB.PCI0.RP09) { - RPVD, 32, - RPR4, 8, - Offset (0x18), - RP18, 8, - RP19, 8, - RP1A, 8, - Offset (0x1C), - RP1C, 16, - Offset (0x20), - R_20, 32, - R_24, 32, - R_28, 32, - R_2C, 32, - Offset (0x52), - , 11, - RPLT, 1, - Offset (0x54) - } + Name (UPN1, 0x03) // USBCPortNumber of SSP1/HS03 + Name (UPN2, 0x04) // USBCPortNumber of SSP2/HS04 - // OperationRegion (UPSM, SystemMemory, TUP1, 0x0548) - // UPSB (up stream port) configuration base - OperationRegion (UPSM, SystemMemory, MMTB (TBSE), 0x0550) - Field (UPSM, DWordAcc, NoLock, Preserve) - { - UPVD, 32, - UP04, 8, - Offset (0x08), - CLRD, 32, - Offset (0x18), - UP18, 8, - UP19, 8, - UP1A, 8, - Offset (0x1C), - UP1C, 16, - Offset (0x20), - UP20, 32, - UP24, 32, - UP28, 32, - UP2C, 32, - Offset (0xD2), - , 11, - UPLT, 1, - Offset (0xD4), - Offset (0x544), - UPMB, 1, - Offset (0x548), - T2PR, 32, - P2TR, 32 - } + Name (R020, Zero) + Name (R024, Zero) + Name (R028, Zero) + Name (R02C, Zero) - // OperationRegion (DNSM, SystemMemory, TDB1, 0xD4) - // DSB0 configuration base - OperationRegion (DNSM, SystemMemory, MMIO (UP19, 0, 0), 0xD4) - Field (DNSM, DWordAcc, NoLock, Preserve) - { - DPVD, 32, - DP04, 8, - Offset (0x18), - DP18, 8, - DP19, 8, - DP1A, 8, - Offset (0x1C), - DP1C, 16, - Offset (0x20), - DP20, 32, - DP24, 32, - DP28, 32, - DP2C, 32, - Offset (0xD2), - , 11, - DPLT, 1, - Offset (0xD4) - } + Name (R118, Zero) + Name (R119, Zero) + Name (R11A, Zero) + Name (R11C, Zero) + Name (R120, Zero) + Name (R124, Zero) + Name (R128, Zero) + Name (R12C, Zero) - // OperationRegion (DS3M, SystemMemory, TD11, 0x40) - // DSB1 configuration base - OperationRegion (DS3M, SystemMemory, MMIO (UP19, 1, 0), 0x40) - Field (DS3M, DWordAcc, NoLock, Preserve) - { - D3VD, 32, - D304, 8, - Offset (0x18), - D318, 8, - D319, 8, - D31A, 8, - Offset (0x1C), - D31C, 16, - Offset (0x20), - D320, 32, - D324, 32, - D328, 32, - D32C, 32 - } + Name (R218, Zero) + Name (R219, Zero) + Name (R21A, Zero) + Name (R21C, Zero) + Name (R220, Zero) + Name (R224, Zero) + Name (R228, Zero) + Name (R22C, Zero) - // OperationRegion (DS4M, SystemMemory, TD21, 0x0568) - // DSB2 configuration base - OperationRegion (DS4M, SystemMemory, MMIO (UP19, 2, 0), 0x0568) - Field (DS4M, DWordAcc, NoLock, Preserve) - { - D4VD, 32, - D404, 8, - Offset (0x18), - D418, 8, - D419, 8, - D41A, 8, - Offset (0x1C), - D41C, 16, - Offset (0x20), - D420, 32, - D424, 32, - D428, 32, - D42C, 32, - Offset (0x564), - DVES, 32 - } + Name (R318, Zero) + Name (R319, Zero) + Name (R31A, Zero) + Name (R31C, Zero) + Name (R320, Zero) + Name (R324, Zero) + Name (R328, Zero) + Name (R32C, Zero) - // OperationRegion (DS5M, SystemMemory, TD41, 0x40) - // DSB4 configuration base - OperationRegion (DS5M, SystemMemory, MMIO (UP19, 4, 0), 0x40) - Field (DS5M, DWordAcc, NoLock, Preserve) - { - D5VD, 32, - D504, 8, - Offset (0x18), - D518, 8, - D519, 8, - D51A, 8, - Offset (0x1C), - D51C, 16, - Offset (0x20), - D520, 32, - D524, 32, - D528, 32, - D52C, 32 - } + Name (R418, Zero) + Name (R419, Zero) + Name (R41A, Zero) + Name (R41C, Zero) + Name (R420, Zero) + Name (R424, Zero) + Name (R428, Zero) + Name (R42C, Zero) + Name (RVES, Zero) - // OperationRegion (NHIM, SystemMemory, TNH1, 0x40) - OperationRegion (NHIM, SystemMemory, MMIO (DP19, 0, 0), 0x40) - Field (NHIM, DWordAcc, NoLock, Preserve) - { - NH00, 32, - NH04, 8, - Offset (0x10), - NH10, 32, - NH14, 32 - } + Name (R518, Zero) + Name (R519, Zero) + Name (R51A, Zero) + Name (R51C, Zero) + Name (R520, Zero) + Name (R524, Zero) + Name (R528, Zero) + Name (R52C, Zero) + Name (R618, Zero) + Name (R619, Zero) + Name (R61A, Zero) + Name (R61C, Zero) + Name (R620, Zero) + Name (R624, Zero) + Name (R628, Zero) + Name (R62C, Zero) - Method (_INI, 0, NotSerialized) // _INI: Initialize - { - Debug = "TB:_INI" + Name (RH10, Zero) + Name (RH14, Zero) - \_SB.PCI0.RP09.XINI() + Name (POC0, Zero) - If (!OSDW ()) + + /** + * Get PCI base address + * Arg0 = bus, Arg1 = device, Arg2 = function + */ + Method (MMIO, 3, NotSerialized) { - TBH1 = One - BICM = One - - Debug = "TB:_INI - Save Ridge Config on Boot ICM" - - R020 = R_20 /* \_SB_.PCI0.RP09.R_20 */ - R024 = R_24 /* \_SB_.PCI0.RP09.R_24 */ - R028 = R_28 /* \_SB_.PCI0.RP09.R_28 */ - R02C = R_2C /* \_SB_.PCI0.RP09.R_2C */ - R118 = UP18 /* \_SB_.PCI0.RP09.UP18 */ - R119 = UP19 /* \_SB_.PCI0.RP09.UP19 */ - R11A = UP1A /* \_SB_.PCI0.RP09.UP1A */ - R11C = UP1C /* \_SB_.PCI0.RP09.UP1C */ - R120 = UP20 /* \_SB_.PCI0.RP09.UP20 */ - R124 = UP24 /* \_SB_.PCI0.RP09.UP24 */ - R128 = UP28 /* \_SB_.PCI0.RP09.UP28 */ - R12C = UP2C /* \_SB_.PCI0.RP09.UP2C */ - R218 = DP18 /* \_SB_.PCI0.RP09.DP18 */ - R219 = DP19 /* \_SB_.PCI0.RP09.DP19 */ - R21A = DP1A /* \_SB_.PCI0.RP09.DP1A */ - R21C = DP1C /* \_SB_.PCI0.RP09.DP1C */ - R220 = DP20 /* \_SB_.PCI0.RP09.DP20 */ - R224 = DP24 /* \_SB_.PCI0.RP09.DP24 */ - R228 = DP28 /* \_SB_.PCI0.RP09.DP28 */ - R228 = DP28 /* \_SB_.PCI0.RP09.DP28 */ - R318 = D318 /* \_SB_.PCI0.RP09.D318 */ - R319 = D319 /* \_SB_.PCI0.RP09.D319 */ - R31A = D31A /* \_SB_.PCI0.RP09.D31A */ - R31C = D31C /* \_SB_.PCI0.RP09.D31C */ - R320 = D320 /* \_SB_.PCI0.RP09.D320 */ - R324 = D324 /* \_SB_.PCI0.RP09.D324 */ - R328 = D328 /* \_SB_.PCI0.RP09.D328 */ - R32C = D32C /* \_SB_.PCI0.RP09.D32C */ - R418 = D418 /* \_SB_.PCI0.RP09.D418 */ - R419 = D419 /* \_SB_.PCI0.RP09.D419 */ - R41A = D41A /* \_SB_.PCI0.RP09.D41A */ - R41C = D41C /* \_SB_.PCI0.RP09.D41C */ - R420 = D420 /* \_SB_.PCI0.RP09.D420 */ - R424 = D424 /* \_SB_.PCI0.RP09.D424 */ - R428 = D428 /* \_SB_.PCI0.RP09.D428 */ - R42C = D42C /* \_SB_.PCI0.RP09.D42C */ - RVES = DVES /* \_SB_.PCI0.RP09.DVES */ - R518 = D518 /* \_SB_.PCI0.RP09.D518 */ - R519 = D519 /* \_SB_.PCI0.RP09.D519 */ - R51A = D51A /* \_SB_.PCI0.RP09.D51A */ - R51C = D51C /* \_SB_.PCI0.RP09.D51C */ - R520 = D520 /* \_SB_.PCI0.RP09.D520 */ - R524 = D524 /* \_SB_.PCI0.RP09.D524 */ - R528 = D528 /* \_SB_.PCI0.RP09.D528 */ - R52C = D52C /* \_SB_.PCI0.RP09.D52C */ - RH10 = NH10 /* \_SB_.PCI0.RP09.NH10 */ - RH14 = NH14 /* \_SB_.PCI0.RP09.NH14 */ - - Debug = "TB:_INI - Store Complete" - Debug = "TB:_INI - ICM ready" - - Sleep (One) - ICMS () + Local0 = \_SB.PCI0.GPCB () // base address + Local0 += (Arg0 << 20) + Local0 += (Arg1 << 15) + Local0 += (Arg2 << 12) + Return (Local0) } - } - /** - * Boot ICM - */ - Method (ICMB, 0, NotSerialized) - { - If (BICM == One) + // Root port configuration base + OperationRegion (RPSM, SystemMemory, MMRP (TBSE), 0x54) + Field (RPSM, DWordAcc, NoLock, Preserve) { - Debug = "TB:ICMB" - - If (!OSDW ()) - { - ICMS () - Debug = "TB:ICMB - Enable ICM on Boot, Complete" - SGOV (0x02060001, Zero) - SGDO (0x02060001) - Debug = "TB:ICMB - Enable ICM on Boot, Complete" - } + RPVD, 32, + RPR4, 8, + Offset (0x18), + RP18, 8, + RP19, 8, + RP1A, 8, + Offset (0x1C), + RP1C, 16, + Offset (0x20), + R_20, 32, + R_24, 32, + R_28, 32, + R_2C, 32, + Offset (0x52), + , 11, + RPLT, 1, + Offset (0x54) } - } - // ICM Start ??? - Method (ICMS, 0, NotSerialized) - { - POC0 = One - - Debug = "TB:ICMS - ICME" - Debug = \_SB.PCI0.RP09.ICME - - If (\_SB.PCI0.RP09.ICME != 0x800001A6 && \_SB.PCI0.RP09.ICME != 0x800000A6) + // UPSB (up stream port) configuration base + OperationRegion (UPSM, SystemMemory, MMTB (TBSE), 0x0550) + Field (UPSM, DWordAcc, NoLock, Preserve) { - If (\_SB.PCI0.RP09.CNHI ()) - { - Debug = "TB:ICMS - ICME" - Debug = \_SB.PCI0.RP09.ICME + UPVD, 32, + UP04, 8, + Offset (0x08), + CLRD, 32, + Offset (0x18), + UP18, 8, + UP19, 8, + UP1A, 8, + Offset (0x1C), + UP1C, 16, + Offset (0x20), + UP20, 32, + UP24, 32, + UP28, 32, + UP2C, 32, + Offset (0xD2), + , 11, + UPLT, 1, + Offset (0xD4), + Offset (0x544), + UPMB, 1, + Offset (0x548), + T2PR, 32, + P2TR, 32 + } - If (\_SB.PCI0.RP09.ICME != 0xFFFFFFFF) + // DSB0 configuration base + OperationRegion (DNSM, SystemMemory, MMIO (UP19, 0, 0), 0xD4) + Field (DNSM, DWordAcc, NoLock, Preserve) + { + DPVD, 32, + DP04, 8, + Offset (0x18), + DP18, 8, + DP19, 8, + DP1A, 8, + Offset (0x1C), + DP1C, 16, + Offset (0x20), + DP20, 32, + DP24, 32, + DP28, 32, + DP2C, 32, + Offset (0xD2), + , 11, + DPLT, 1, + Offset (0xD4) + } + + // DSB1 configuration base + OperationRegion (DS3M, SystemMemory, MMIO (UP19, 1, 0), 0x40) + Field (DS3M, DWordAcc, NoLock, Preserve) + { + D3VD, 32, + D304, 8, + Offset (0x18), + D318, 8, + D319, 8, + D31A, 8, + Offset (0x1C), + D31C, 16, + Offset (0x20), + D320, 32, + D324, 32, + D328, 32, + D32C, 32 + } + + // DSB2 configuration base + OperationRegion (DS4M, SystemMemory, MMIO (UP19, 2, 0), 0x0568) + Field (DS4M, DWordAcc, NoLock, Preserve) + { + D4VD, 32, + D404, 8, + Offset (0x18), + D418, 8, + D419, 8, + D41A, 8, + Offset (0x1C), + D41C, 16, + Offset (0x20), + D420, 32, + D424, 32, + D428, 32, + D42C, 32, + Offset (0x564), + DVES, 32 + } + + // DSB4 configuration base + OperationRegion (DS5M, SystemMemory, MMIO (UP19, 4, 0), 0x40) + Field (DS5M, DWordAcc, NoLock, Preserve) + { + D5VD, 32, + D504, 8, + Offset (0x18), + D518, 8, + D519, 8, + D51A, 8, + Offset (0x1C), + D51C, 16, + Offset (0x20), + D520, 32, + D524, 32, + D528, 32, + D52C, 32 + } + + OperationRegion (NHIM, SystemMemory, MMIO (DP19, 0, 0), 0x40) + Field (NHIM, DWordAcc, NoLock, Preserve) + { + NH00, 32, + NH04, 8, + Offset (0x10), + NH10, 32, + NH14, 32 + } + + OperationRegion (RSTR, SystemMemory, NH10 + 0x39858, 0x0100) + // OperationRegion (RSTR, SystemMemory, NHI1, 0x0100) + Field (RSTR, DWordAcc, NoLock, Preserve) + { + CIOR, 32, + Offset (0xB8), + ISTA, 32, + // Offset (0xF0), + Offset (0xEC), + ICME, 32 + } + + Method (INIT, 0, NotSerialized) + { + If (OSDW ()) + { + Concatenate("TB:INIT: TBSF - Thunderbolt(TM) SMI Function Number: ", TBSF, Debug) + Concatenate("TB:INIT: SOHP - SMI on Hot Plug for TBT devices: ", SOHP, Debug) + Concatenate("TB:INIT: TWIN - TbtWin10Support: ", TWIN, Debug) + Concatenate("TB:INIT: GP5F - Gpio filter to detect USB Hotplug event: ", GP5F, Debug) + Concatenate("TB:INIT: NOHP - Notify on Hot Plug for TBT devices: ", NOHP, Debug) + Concatenate("TB:INIT: TBSE - Thunderbolt(TM) Root port selector: ", TBSE, Debug) + Concatenate("TB:INIT: WKFN - WAK Finished: ", WKFN, Debug) + Concatenate("TB:INIT: TBTS - Thunderbolt support: ", TBTS, Debug) + Concatenate("TB:INIT: TARS - TbtAcpiRemovalSupport: ", TARS, Debug) + Concatenate("TB:INIT: FPEN - TbtFrcPwrEn: ", FPEN, Debug) + Concatenate("TB:INIT: FPG1 - TbtFrcPwrGpioNo: ", FPG1, Debug) + Concatenate("TB:INIT: FP1L - TbtFrcPwrGpioLevel: ", FP1L, Debug) + Concatenate("TB:INIT: CPG1 - TbtCioPlugEventGpioNo: ", CPG1, Debug) + Concatenate("TB:INIT: TRWA - Titan Ridge Osup command: ", TRWA, Debug) + Concatenate("TB:INIT: TBOD - Rtd3TbtOffDelay TBT RTD3 Off Delay: ", TBOD, Debug) + Concatenate("TB:INIT: TSXW - TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW logic is required: ", TSXW, Debug) + Concatenate("TB:INIT: RTBT - Enable Rtd3 support for TBT: ", RTBT, Debug) + Concatenate("TB:INIT: RTBC - Enable TBT RTD3 CLKREQ mask: ", RTBC, Debug) + Concatenate("TB:INIT: TBCD - TBT RTD3 CLKREQ mask delay: ", TBCD, Debug) + + Concatenate("TB:INIT: USBP - Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG): ", USBP, Debug) + Concatenate("TB:INIT: UWAB - USB2 Workaround Available: ", UWAB, Debug) + Concatenate("TB:INIT: USME - Disables HS01/HS01@XHC2 & Switches SSP1/SSP2@XHC2 -> 0x0A (maybe like U2OP?) ???: ", USME, Debug) + Concatenate("TB:INIT: USTC - USBC-if enabled (UBTC) ???: ", USTC, Debug) + Concatenate("TB:INIT: TBAS - Enables HS03/04@XHC1 ???: ", TBAS, Debug) + + If (\TBTS) { - SGDI (0x01070004) - \_SB.PCI0.RP09.WTLT () - - Debug = "TB:ICMS - ICME" - Debug = \_SB.PCI0.RP09.ICME + Debug = "INIT: TB enabled" - If (!Local0 = (\_SB.PCI0.RP09.ICME & 0x80000000)) // NVM started means we need reset + If (\TWIN != Zero) { - \_SB.PCI0.RP09.ICME |= 0x06 // invert EN | enable CPU - Local0 = 1000 - While ((Local1 = (\_SB.PCI0.RP09.ICME & 0x80000000)) == Zero) + Debug = "INIT: TB native mode enabled" + Debug = "TB:INIT - Save Ridge Config on Boot ICM" + R020 = R_20 /* \_SB.PCI0.RP09.R_20 */ + R024 = R_24 /* \_SB.PCI0.RP09.R_24 */ + R028 = R_28 /* \_SB.PCI0.RP09.R_28 */ + R02C = R_2C /* \_SB.PCI0.RP09.R_2C */ + R118 = UP18 /* \_SB.PCI0.RP09.UP18 */ + R119 = UP19 /* \_SB.PCI0.RP09.UP19 */ + R11A = UP1A /* \_SB.PCI0.RP09.UP1A */ + R11C = UP1C /* \_SB.PCI0.RP09.UP1C */ + R120 = UP20 /* \_SB.PCI0.RP09.UP20 */ + R124 = UP24 /* \_SB.PCI0.RP09.UP24 */ + R128 = UP28 /* \_SB.PCI0.RP09.UP28 */ + R12C = UP2C /* \_SB.PCI0.RP09.UP2C */ + R218 = DP18 /* \_SB.PCI0.RP09.DP18 */ + R219 = DP19 /* \_SB.PCI0.RP09.DP19 */ + R21A = DP1A /* \_SB.PCI0.RP09.DP1A */ + R21C = DP1C /* \_SB.PCI0.RP09.DP1C */ + R220 = DP20 /* \_SB.PCI0.RP09.DP20 */ + R224 = DP24 /* \_SB.PCI0.RP09.DP24 */ + R228 = DP28 /* \_SB.PCI0.RP09.DP28 */ + R228 = DP28 /* \_SB.PCI0.RP09.DP28 */ + R318 = D318 /* \_SB.PCI0.RP09.D318 */ + R319 = D319 /* \_SB.PCI0.RP09.D319 */ + R31A = D31A /* \_SB.PCI0.RP09.D31A */ + R31C = D31C /* \_SB.PCI0.RP09.D31C */ + R320 = D320 /* \_SB.PCI0.RP09.D320 */ + R324 = D324 /* \_SB.PCI0.RP09.D324 */ + R328 = D328 /* \_SB.PCI0.RP09.D328 */ + R32C = D32C /* \_SB.PCI0.RP09.D32C */ + R418 = D418 /* \_SB.PCI0.RP09.D418 */ + R419 = D419 /* \_SB.PCI0.RP09.D419 */ + R41A = D41A /* \_SB.PCI0.RP09.D41A */ + R41C = D41C /* \_SB.PCI0.RP09.D41C */ + R420 = D420 /* \_SB.PCI0.RP09.D420 */ + R424 = D424 /* \_SB.PCI0.RP09.D424 */ + R428 = D428 /* \_SB.PCI0.RP09.D428 */ + R42C = D42C /* \_SB.PCI0.RP09.D42C */ + RVES = DVES /* \_SB.PCI0.RP09.DVES */ + R518 = D518 /* \_SB.PCI0.RP09.D518 */ + R519 = D519 /* \_SB.PCI0.RP09.D519 */ + R51A = D51A /* \_SB.PCI0.RP09.D51A */ + R51C = D51C /* \_SB.PCI0.RP09.D51C */ + R520 = D520 /* \_SB.PCI0.RP09.D520 */ + R524 = D524 /* \_SB.PCI0.RP09.D524 */ + R528 = D528 /* \_SB.PCI0.RP09.D528 */ + R52C = D52C /* \_SB.PCI0.RP09.D52C */ + RH10 = NH10 /* \_SB.PCI0.RP09.NH10 */ + RH14 = NH14 /* \_SB.PCI0.RP09.NH14 */ + Debug = "TB:INIT - Store Complete" + + Sleep (One) + + ICMD () + } + Else + { + Debug = "INIT: TB bios-assist enabled" + + If (\_GPE.TFPS ()) { - Local0-- - If (Local0 == Zero) + Debug = "INIT: TB Force Power alread enabled" + } + Else + { + Debug = "INIT: enabling TB Force Power" + + \_SB.TBFP (One) // force power + + Local0 = 10000 // 10 seconds + While (Local0 > 0 && \_SB.PCI0.RP09.VDID == 0xFFFFFFFF) { - Break + Sleep (1) + Local0-- } - Sleep (One) + Debug = Concatenate ("INIT: saw TB-Controller VDID: ", \_SB.PCI0.RP09.VDID) + Debug = Concatenate ("INIT: ms waited: ", (10000 - Local0)) } - - Debug = "TB:ICMS - TB:ICME" - Debug = \_SB.PCI0.RP09.ICME - \_SB.SGOV (0x01070004, Zero) - \_SB.SGDO (0x01070004) } } } } - \_SB.PCI0.RP09.POC0 = Zero - - // disable USB force power - SGOV (0x01070007, Zero) - SGDO (0x01070007) - } - - /** - * Send TBT command - */ - Method (TBTC, 1, Serialized) - { - Debug = "TB:TBTC - Send TBT command" - - P2TR = Arg0 - - Local0 = 0x64 - Local1 = T2PR /* \_SB_.PCI0.RP09.T2PR */ - - While ((Local2 = (Local1 & One)) == Zero) + Method (_INI, 0, NotSerialized) // _INI: Initialize { - If (Local1 == 0xFFFFFFFF) + If (!OSDW ()) { + XINI () + } + } + + // /** + // * ThunderboltPowerUp + // * Force power with controller and does init. + // * Returns 1 if power up was successful + // */ + // Method (TBON, 0, Serialized) + // { + // Debug = Concatenate ("TB:TBON - CPGN: ", CPGN) + + // If (\_GPE.TFPS ()) + // { + // Debug = "TB:TBON - Already on" + // Return (Zero) + // } + + // Debug = "TB:TBON - Force power on" + // TBFP (One) // force power + + // Debug = "TB:TBON - Wait for TB root power up" + // Local1 = Timer + 6000000 // timeout in 600ms + // While (Timer < Local1 && FFTB (TBSE)) + // { + // Sleep (1) // 1 millisecond + // } + + // Debug = "TB:TBON - Sending OSUP handshake" + // Acquire (OSUM, 0xFFFF) + // Local0 = \_GPE.TBFF (TBSE) // calls OSUP if not already up + // Release (OSUM) + // Debug = Concatenate ("TB:TBON - TBFF: ", Local0) + + // Debug = "TB:TBON - TB hardware init sequence" + // SOHP = Zero + // TNAT = One + // \_GPE.XTBT (TBSE, CPGN) + + // Debug = "TB:TBON - Waiting for controller to appear" + // Local1 = Timer + 50000000 // timeout in 5s + // While (Timer < Local1 && UPVD == 0xFFFFFFFF) + // { + // Sleep (100) // 100 milliseconds + // } + + // If (UPVD != 0xFFFFFFFF) + // { + // Debug = Concatenate ("TB:TBON - Seen controller: ", UPVD) + // Debug = Concatenate ("TB:TBON - CPGN: ", CPGN) + + // Return (One) + // } + + // Debug = "TB:TBON - Failed" + // Return (Zero) + // } + + // /** + // * ThunderboltPowerOff + // * Release force power. This does not poll until controller + // * is actually down! + // * Return 1 if power down was successful. + // */ + // Method (TBOF, 0, Serialized) + // { + // Debug = "TB:TBOF" + + // If (\_GPE.TFPS ()) + // { + // TBFP (Zero) + + // Return (One) + // } + + // Debug = "TB:TBOF - Already off" + + // Return (Zero) + // } + + /** + * Thunderbolt status + */ + Method (TBST, 0, Serialized) + { + Debug = Concatenate ("TB:_PS0 - MDUV: ", \_SB.PCI0.RP09.UPSB.MDUV) + Debug = Concatenate ("TB:_PS0 - NHI: ", \_SB.PCI0.RP09.NH00) + Debug = Concatenate ("TB:_PS0 - Root port: ", \_SB.PCI0.RP09.RPVD) + Debug = Concatenate ("TB:_PS0 - Upstream port: ", \_SB.PCI0.RP09.UPVD) + Debug = Concatenate ("TB:_PS0 - DSB0: ", \_SB.PCI0.RP09.DPVD) + Debug = Concatenate ("TB:_PS0 - DSB1: ", \_SB.PCI0.RP09.D3VD) + Debug = Concatenate ("TB:_PS0 - DSB2: ", \_SB.PCI0.RP09.D4VD) + Debug = Concatenate ("TB:_PS0 - DSB4: ", \_SB.PCI0.RP09.D5VD) + } + + /** + * SendCMD + * Sends command to TB controller. Assumes powered up. + */ + Method (SCMD, 2, Serialized) + { + Debug = "TB:SCMD" + // Local0 = (MMTB (TBSE) + 0x0548) + // OperationRegion (PXVD, SystemMemory, Local0, 0x8) + // Field (PXVD, DWordAcc, NoLock, Preserve) + // { + // TB2P, 32, + // P2TB, 32 + // } + + // T2PR, 32, + // P2TR, 32 + + P2TR = (Arg1 << 8) | (Arg0 << 1) | 0x1 + Local0 = 50 + While (Local0 > 0) + { + If (T2PR == 0xC || (T2PR & 1)) // 0xC = error, 0x1 = success + { + Break + } + Local0-- + Sleep (100) + } + + Debug = Concatenate ("TB:SCMD - P2TR: ", P2TR) + Debug = Concatenate ("TB:SCMD - T2PR: ", T2PR) + + P2TR = Zero + } + + /** + * ICM Disable + + * Disable ICM to allow the OSX-driver to take control + * + * #define REG_FW_STS 0x39944 + * #define REG_FW_STS_NVM_AUTH_DONE BIT(31) + * #define REG_FW_STS_CIO_RESET_REQ BIT(30) + * #define REG_FW_STS_ICM_EN_CPU BIT(2) + * #define REG_FW_STS_ICM_EN_INVERT BIT(1) + * #define REG_FW_STS_ICM_EN BIT(0) + * + * Source: https://github.com/dell/thunderbolt-dkms/blob/master/thunderbolt/nhi_regs.h + */ + Method (ICMD, 0, NotSerialized) + { + Debug = "TB:ICMD - Disable ICM " + + \_SB.PCI0.RP09.POC0 = One + + Debug = Concatenate ("TB:ICMD - ICME 1: ", \_SB.PCI0.RP09.ICME) + + If (\_SB.PCI0.RP09.ICME != 0x800001A3) + { + If (\_SB.PCI0.RP09.CNHI ()) + { + Debug = Concatenate ("TB:ICMD - ICME 2: ", \_SB.PCI0.RP09.ICME) + + If (\_SB.PCI0.RP09.ICME != 0xFFFFFFFF) + { + \_SB.PCI0.RP09.WTLT () + + Debug = Concatenate ("TB:ICMD - ICME 3: ", \_SB.PCI0.RP09.ICME) + + If (Local0 = (\_SB.PCI0.RP09.ICME & 0x80000000)) // NVM started means we need reset + { + Debug = "TB:ICMD - NVM already started, resetting" + + \_SB.PCI0.RP09.ICME = 0x102 // REG_FW_STS_ICM_EN_INVERT + + Local0 = 1000 + While ((\_SB.PCI0.RP09.ICME & 0x1) == Zero) + { + Local0-- + If (Local0 == Zero) + { + Break + } + + Sleep (One) + } + + Debug = Concatenate ("TB:ICMD - ICME 4: ", \_SB.PCI0.RP09.ICME) + + Sleep (1000) + } + } + } + } + + \_SB.PCI0.RP09.POC0 = Zero + } + + + /** + * Send TBT command + */ + Method (TBTC, 1, Serialized) + { + Debug = "TB:TBTC" + + P2TR = Arg0 + + Local0 = 0x64 + Local1 = T2PR /* \_SB.PCI0.RP09.T2PR */ + + While ((Local1 & One) == Zero) + { + If (Local1 == 0xFFFFFFFF) + { + Return (Zero) + } + + Local0-- + If (Local0 == Zero) + { + Break + } + + Local1 = T2PR /* \_SB.PCI0.RP09.T2PR */ + Sleep (0x32) + } + + P2TR = Zero + + Return (Zero) + } + + /** + * Plug detection for Windows + */ + Method (CMPE, 0, Serialized) + { + Debug = "TB:CMPE" + + Notify (\_SB.PCI0.RP09, Zero) // Bus Check + } + + Method (CNHI, 0, Serialized) + { + Debug = "TB:CNHI" + + Local0 = 10 + + Debug = "TB:CNHI - Configure root port" + While (Local0) + { + R_20 = R020 // Memory Base/Limit + R_24 = R024 // Prefetch Base/Limit + R_28 = R028 /* \_SB.PCI0.RP09.R028 */ + R_2C = R02C /* \_SB.PCI0.RP09.R02C */ + RPR4 = 0x07 // Command + + If (R020 == R_20) // read back check + { + Break + } + + Sleep (One) + Local0-- + } + + If (R020 != R_20) // configure root port failed + { + Debug = "TB:CNHI - Error: configure root port failed" + Return (Zero) } - Local0-- - If (Local0 == Zero) + Local0 = 10 + + Debug = "TB:CNHI - Configure UPSB" + While (Local0) { - Break + + UP18 = R118 // UPSB Pri Bus + UP19 = R119 // UPSB Sec Bus + UP1A = R11A // UPSB Sub Bus + UP1C = R11C // UPSB IO Base/Limit + UP20 = R120 // UPSB Memory Base/Limit + UP24 = R124 // UPSB Prefetch Base/Limit + UP28 = R128 /* \_SB.PCI0.RP09.R128 */ + UP2C = R12C /* \_SB.PCI0.RP09.R12C */ + UP04 = 0x07 // Command + + If (R119 == UP19) // read back check + { + Break + } + + Sleep (One) + Local0-- } - Local1 = T2PR /* \_SB_.PCI0.RP09.T2PR */ - Sleep (0x32) - } - - P2TR = Zero - - Return (Zero) - } - - /** - * Plug detection for Windows - */ - Method (CMPE, 0, Serialized) - { - Debug = "TB:CMPE - Plug detection for Windows" - - Notify (\_SB.PCI0.RP09, Zero) // Bus Check - } - - /** - * Configure NHI device - */ - Method (CNHI, 0, Serialized) - { - // Configure root port - Debug = "TB:CNHI - Configure NHI root" - - Local0 = 10 - - While (Local0) - { - R_20 = R020 // Memory Base/Limit - R_24 = R024 // Prefetch Base/Limit - R_28 = R028 /* \_SB_.PCI0.RP09.R028 */ - R_2C = R02C /* \_SB_.PCI0.RP09.R02C */ - - RPR4 = 0x07 // Command - - If (R020 == R_20) + If (R119 != UP19) // configure UPSB failed { - Break + Debug = "TB:CNHI - Error: configure UPSB failed" + + Return (Zero) } - Sleep (One) - - Local0-- - } - - If (R020 != R_20) // configure failed - { - Debug = "TB:CNHI - Configure NHI failed" - - Return (Zero) - } - - // Configure UPSB - Debug = "TB:CNHI - Configure UPSB" - - Local0 = 10 - - While (Local0) - { - UP18 = R118 // UPSB Pri Bus - UP19 = R119 // UPSB Sec Bus - UP1A = R11A // UPSB Sub Bus - UP1C = R11C // UPSB IO Base/Limit - UP20 = R120 // UPSB Memory Base/Limit - UP24 = R124 // UPSB Prefetch Base/Limit - UP28 = R128 /* \_SB_.PCI0.RP09.R128 */ - UP2C = R12C /* \_SB_.PCI0.RP09.R12C */ - UP04 = 0x07 // UPSB Command - - If (R119 == UP19) // read back check + Debug = "TB:CNHI - Wait for link training" + If (WTLT () != One) { - Break + Debug = "TB:CNHI - Error: Wait for link training failed" + + Return (Zero) } - Sleep (One) + Local0 = 10 - Local0-- - } - - If (R119 != UP19) // configure failed - { - Debug = "TB:CNHI - Configure UPSB failed" - - Return (Zero) - } - - Debug = "TB:CNHI - Wait for link training" - - If (WTLT () != One) - { - Debug = "TB:CNHI - Wait for link training failed" - - Return (Zero) - } - - // Configure DSB0 - Debug = "TB:CNHI - Configure DSB" - - Local0 = 10 - - While (Local0) - { - DP18 = R218 // Pri Bus - DP19 = R219 // Sec Bus - DP1A = R21A // Sub Bus - DP1C = R21C // IO Base/Limit - DP20 = R220 // Memory Base/Limit - DP24 = R224 // Prefetch Base/Limit - DP28 = R228 /* \_SB_.PCI0.RP09.R228 */ - DP2C = R22C /* \_SB_.PCI0.RP09.R22C */ - DP04 = 0x07 // Command - Debug = "TB:CNHI - Configure NHI Dp 0 done" - - D318 = R318 // Pri Bus - D319 = R319 // Sec Bus - D31A = R31A // Sub Bus - D31C = R31C // IO Base/Limit - D320 = R320 // Memory Base/Limit - D324 = R324 // Prefetch Base/Limit - D328 = R328 /* \_SB_.PCI0.RP09.R328 */ - D32C = R32C /* \_SB_.PCI0.RP09.R32C */ - D304 = 0x07 // Command - Debug = "TB:CNHI - Configure NHI Dp 3 done" - - D418 = R418 // Pri Bus - D419 = R419 // Sec Bus - D41A = R41A // Sub Bus - D41C = R41C // IO Base/Limit - D420 = R420 // Memory Base/Limit - D424 = R424 // Prefetch Base/Limit - D428 = R428 /* \_SB_.PCI0.RP09.R428 */ - D42C = R42C /* \_SB_.PCI0.RP09.R42C */ - DVES = RVES // DSB2 0x564 - D404 = 0x07 // Command - Debug = "TB:CNHI - Configure NHI Dp 4 done" - - D518 = R518 // Pri Bus - D519 = R519 // Sec Bus - D51A = R51A // Sub Bus - D51C = R51C // IO Base/Limit - D520 = R520 // Memory Base/Limit - D524 = R524 // Prefetch Base/Limit - D528 = R528 /* \_SB_.PCI0.RP09.R528 */ - D52C = R52C /* \_SB_.PCI0.RP09.R52C */ - D504 = 0x07 // Command - Debug = "TB:CNHI - Configure NHI Dp 5 done" - - If (R219 == DP19) // read back check + // Configure DSB0 + Debug = "TB:CNHI - Configure DSB" + While (Local0) { - Break + DP18 = R218 // Pri Bus + DP19 = R219 // Sec Bus + DP1A = R21A // Sub Bus + DP1C = R21C // IO Base/Limit + DP20 = R220 // Memory Base/Limit + DP24 = R224 // Prefetch Base/Limit + DP28 = R228 /* \_SB.PCI0.RP09.R228 */ + DP2C = R22C /* \_SB.PCI0.RP09.R22C */ + DP04 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 0 done" + + D318 = R318 // Pri Bus + D319 = R319 // Sec Bus + D31A = R31A // Sub Bus + D31C = R31C // IO Base/Limit + D320 = R320 // Memory Base/Limit + D324 = R324 // Prefetch Base/Limit + D328 = R328 /* \_SB.PCI0.RP09.R328 */ + D32C = R32C /* \_SB.PCI0.RP09.R32C */ + D304 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 3 done" + + D418 = R418 // Pri Bus + D419 = R419 // Sec Bus + D41A = R41A // Sub Bus + D41C = R41C // IO Base/Limit + D420 = R420 // Memory Base/Limit + D424 = R424 // Prefetch Base/Limit + D428 = R428 /* \_SB.PCI0.RP09.R428 */ + D42C = R42C /* \_SB.PCI0.RP09.R42C */ + DVES = RVES // DSB2 0x564 + D404 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 4 done" + + D518 = R518 // Pri Bus + D519 = R519 // Sec Bus + D51A = R51A // Sub Bus + D51C = R51C // IO Base/Limit + D520 = R520 // Memory Base/Limit + D524 = R524 // Prefetch Base/Limit + D528 = R528 /* \_SB.PCI0.RP09.R528 */ + D52C = R52C /* \_SB.PCI0.RP09.R52C */ + D504 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 5 done" + + If (R219 == DP19) + { + Break + } + + Sleep (One) + Local0-- } - Sleep (One) - Local0-- - } - - If (R219 != DP19) // configure failed - { - Debug = "TB:CNHI - Configure DSB failed" - - Return (Zero) - } - - Debug = "TB:CNHI - Wait for down link" - - If (WTDL () == One) - { - Debug = "TB:CNHI - Configure NHI DPs done" - } - Else - { - Return (Zero) - } - - // Configure NHI - Debug = "TB:CNHI - Configure NHI" - - Local0 = 100 - - While (Local0) - { - NH10 = RH10 // NHI BAR 0 - NH14 = RH14 // NHI BAR 1 - NH04 = 0x07 // NHI Command - - If (RH10 == NH10) // read back check + If (R219 != DP19) // configure DSB failed { - Break + Debug = "TB:CNHI - Error: configure DSB failed" + + Return (Zero) } - Sleep (One) - Local0-- - } + If (WTDL () != One) + { + Debug = "TB:CNHI - Error: Configure NHI DPs failed" - // Debug = "TB:CNHI NHI BAR" - // Debug = NH10 + Return (Zero) + } - If (RH10 != NH10) // configure failed - { - Return (Zero) - } + // Configure NHI + Debug = "TB:CNHI - Configure NHI" - Debug = "TB:CNHI - CNHI done" + Local0 = 100 - Return (One) - } + While (Local0) + { + NH10 = RH10 // NHI BAR 0 + NH14 = RH14 // NHI BAR 1 + NH04 = 0x07 // NHI Command - /** - * Uplink check - */ - Method (UPCK, 0, Serialized) - { - Debug = "TB:UBCK - Uplink check - Upstream VID/DID =" - Debug = UPVD /* \_SB_.PCI0.RP09.UPVD */ + If (RH10 == NH10) + { + Break + } + + Sleep (One) + Local0-- + } + + If (RH10 != NH10) // configure failed + { + Debug = "TB:CNHI - Error: Configure NHI failed" + + Return (Zero) + } + + Debug = "TB:CNHI - Configure NHI0 done" - // accepts every intel chip - If ((UPVD & 0xFFFF) == 0x8086) - { Return (One) } - Return (Zero) - } - - /** - * Uplink training check - */ - Method (ULTC, 0, Serialized) - { - Debug = "TB:ULTC - Uplink training check" - - If (RPLT == Zero) + /** + * Uplink check + */ + Method (UPCK, 0, Serialized) { - If (UPLT == Zero) + Debug = Concatenate ("TB:UPCK - Up Stream VID/DID: ", UPVD) + + // Accepts every intel device + If ((UPVD & 0xFFFF) == 0x8086) { Return (One) } + + Return (Zero) } - Return (Zero) - } - - /** - * Wait for link training - */ - Method (WTLT, 0, Serialized) - { - Debug = "TB:WTLT - Wait for link training" - - Local0 = 2000 - Local1 = Zero - - While (Local0) + /** + * Uplink training check + */ + Method (ULTC, 0, Serialized) { - If (RPR4 == 0x07) + Debug = "TB:ULTC" + + If (RPLT == Zero) { - If (ULTC ()) - { - If (UPCK ()) - { - Local1 = One - Break - } - } - } - - Sleep (One) - Local0-- - } - - // Debug = "TB:WTLT LOOP=" - // Debug = Local0 - - Return (Local1) - } - - /** - * Downlink training check - */ - Method (DLTC, 0, Serialized) - { - Debug = "TB:DLTC - Downlink training check" - - If (RPLT == Zero) - { - If (UPLT == Zero) - { - If (DPLT == Zero) + If (UPLT == Zero) { Return (One) } } + + Return (Zero) } - Return (Zero) - } - - /** - * Wait for downlink training - */ - Method (WTDL, 0, Serialized) - { - Debug = "TB:WTDL - Wait for downlink training" - - Local0 = 2000 - Local1 = Zero - - While (Local0) + /** + * Wait for link training + */ + Method (WTLT, 0, Serialized) { - If (RPR4 == 0x07) + // Debug = "TB:WTLT" + + Local0 = 0x07D0 + Local1 = Zero + + While (Local0) { - If (DLTC ()) + If (RPR4 == 0x07) { - If (UPCK ()) + If (ULTC ()) { - Local1 = One - Break - } - } - } - - Sleep (One) - Local0-- - } - - // Debug = "TB:WTDL LOOP=" - // Debug = Local0 - - Return (Local1) - } - - Name (IIP3, Zero) - Name (PRSR, Zero) - Name (PCIA, One) - - /** - * Bring up PCI link - * Train downstream link - */ - Method (PCEU, 0, Serialized) - { - Debug = "TB:PCEU - Bring up PCI link" - - \_SB.PCI0.RP09.PRSR = Zero - - // Debug = "TB:PCEU - Put upstream bridge back into D0 " - If (\_SB.PCI0.RP09.PSTX != Zero) - { - // Debug = "TB:PCEU - exit D0, restored = true" - \_SB.PCI0.RP09.PRSR = One - \_SB.PCI0.RP09.PSTX = Zero - } - - If (\_SB.PCI0.RP09.LDXX == One) - { - // Debug = "TB:PCEU - Clear link disable on upstream bridge" - // Debug = "TB:PCEU - clear link disable, restored = true" - \_SB.PCI0.RP09.PRSR = One - \_SB.PCI0.RP09.LDXX = Zero - } - - If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRTE != Zero) - { - // Debug = "TB:PCEU - XRST changed, restored = true" - \_SB.PCI0.RP09.PRSR = One - \_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRST (Zero) - } - } - - /** - * Bring down PCI link - */ - Method (PCDA, 0, Serialized) - { - Debug = "TB:PCDA - Bring down PCI link" - - If (\_SB.PCI0.RP09.POFX () != Zero) - { - \_SB.PCI0.RP09.PCIA = Zero - - // Debug = "TB:PCDA - Put upstream bridge into D3" - \_SB.PCI0.RP09.PSTX = 0x03 - - // Debug = "TB:PCDA - Set link disable on upstream bridge" - \_SB.PCI0.RP09.LDXX = One - - Local5 = (Timer + 0x00989680) - - While (Timer <= Local5) - { - // Debug = "TB:PCDA - Wait for link to drop..." - If (\_SB.PCI0.RP09.LACR == One) - { - If (\_SB.PCI0.RP09.LACT == Zero) - { - // Debug = "TB:PCDA - No link activity" - Break - } - } - ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) - { - // Debug = "TB:PCDA - VID/DID is -1" - Break - } - - Sleep (0x0A) - } - - // Debug = "TB:PCDA - disable GPIO" - \_SB.PCI0.RP09.GPCI = Zero - \_SB.PCI0.RP09.UGIO () - } - Else - { - Debug = "TB:PCDA - Not disabling" - } - - \_SB.PCI0.RP09.IIP3 = One - } - - /** - * Returns true if both TB and TB-USB are idle - */ - Method (POFX, 0, Serialized) - { - If (!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB) - { - Debug = "TB:POFX - TB & USB are both idle" - } - ElseIf (!\_SB.PCI0.RP09.RTBT) - { - Debug = "TB:POFX - USB active, TB idle" - } - ElseIf (!\_SB.PCI0.RP09.RUSB) - { - Debug = "TB:POFX - USB idle, TB active" - } - Else - { - Debug = "TB:POFX - WE SHOULDNT SEE THIS CASE, IF YOU DO, ITS A BUG :)" - } - - - Return ((!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB)) - } - - Name (GPCI, One) - Name (GNHI, One) - Name (GXCI, One) - Name (RTBT, One) - Name (RUSB, One) - Name (CTPD, Zero) - - /** - * Send power down ack to CP - */ - Method (CTBT, 0, Serialized) - { - Debug = "TB:CTBT - Send power down ack to CP" - - If ((GGDV (0x02060000) == One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) - // If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) - { - // Debug = "TB:CTBT - TBT domain is enabled" - Local2 = \_SB.PCI0.RP09.UPSB.CRMW (0x3C, Zero, 0x02, 0x04000000, 0x04000000) - - If (Local2 == Zero) - { - // Debug = "TB:CTBT - Set CP_ACK_POWERDOWN_OVERRIDE" - \_SB.PCI0.RP09.CTPD = One - } - } - } - - /** - * Toggle controller power - * Power controllers either up or down depending on the request. - * On Macs, there's two GPIO signals for controlling TB and XHC - * separately. If such signals exist, we need to find it. Otherwise - * we lose the power saving capabilities. - * Returns if controller is powered up - */ - Method (UGIO, 0, Serialized) - { - // Which controller is requested to be on? - Local0 = (\_SB.PCI0.RP09.GNHI || \_SB.PCI0.RP09.RTBT) // TBT - Local1 = (\_SB.PCI0.RP09.GXCI || \_SB.PCI0.RP09.RUSB) // USB - - // Debug = "TB:UGIO - TBT-state:" - // Debug = Local0 - // Debug = "TB:UGIO - usb-state:" - // Debug = Local1 - - If (\_SB.PCI0.RP09.GPCI == Zero) - { - Debug = "TB:UGIO - PCI wants off (GPCI = Zero)" - } - Else - { - Debug = "TB:UGIO - PCI wants on (GPCI = One)" - } - - If (\_SB.PCI0.RP09.GNHI == Zero) - { - Debug = "TB:UGIO - NHI wants off (GNHI = Zero)" - } - Else - { - Debug = "TB:UGIO - NHI wants on (GNHI = One)" - } - - If (\_SB.PCI0.RP09.GXCI == Zero) - { - Debug = "TB:UGIO - XHCI wants off (GXCI = Zero)" - } - Else - { - Debug = "TB:UGIO - XHCI wants on (GXCI = One)" - } - - If (\_SB.PCI0.RP09.RTBT == Zero) - { - Debug = "TB:UGIO - TBT allows off (RTBT = Zero)" - } - Else - { - Debug = "TB:UGIO - TBT forced on (RTBT = One)" - } - - If (\_SB.PCI0.RP09.RUSB == Zero) - { - Debug = "TB:UGIO - USB allows off (RUSB = Zero)" - } - Else - { - Debug = "TB:UGIO - USB forced on (RUSB = One)" - } - - // NHI controller wants to be on - If (\_SB.PCI0.RP09.GPCI != Zero) - { - // if neither are requested to be on but the NHI controller - // needs to be up, then we go ahead and power it on anyways - If ((Local0 == Zero) && (Local1 == Zero)) - { - Local0 = One - Local1 = One - } - } - - // If (Local0 == Zero) - // { - // Debug = "TB:UGIO - TBT GPIO should be off" - // } - // Else - // { - // Debug = "TB:UGIO - TBT GPIO should be on" - // } - - // If (Local1 == Zero) - // { - // Debug = "TB:UGIO - USB GPIO should be off" - // } - // Else - // { - // Debug = "TB:UGIO - USB GPIO should be on" - // } - - Local2 = Zero - - If (Local0 != Zero) - { - // Debug = "TB:UGIO - Make sure TBT is on" - If (GGDV (0x02060000) == Zero) - { - // Debug = "TB:UGIO - Turn on TBT GPIO" - SGDI (0x02060000) - Local2 = One - \_SB.PCI0.RP09.CTPD = Zero - - Debug = "TB:UGIO - Enable TB" - } - } - - If (Local1 != Zero) - { - // Debug = "TB:UGIO - Make sure USB is on" - If (GGDV (0x02060001) == Zero) - { - // Debug = "TB:UGIO - Turn on USB GPIO" - SGDI (0x02060001) - Local2 = One - - Debug = "TB:UGIO - Enable USB" - } - } - - If (Local2 != Zero) - { - Sleep (0x01F4) - } - - Local3 = Zero - - If (Local0 == Zero) - { - // Debug = "TB:UGIO - Make sure TBT is off" - - If (GGDV (0x02060000) == One) - { - \_SB.PCI0.RP09.CTBT () - - If (\_SB.PCI0.RP09.CTPD != Zero) - { - // Debug = "TB:UGIO - Turn off TBT GPIO" - SGOV (0x02060000, Zero) - SGDO (0x02060000) - Local3 = One - - Debug = "TB:UGIO - Disable TB" - } - Else - { - // Debug = "TB:UGIO - CP_ACK_POWERDOWN_OVERRIDE not configured, cannot turn off TBT GPIO" - } - } - } - - If (Local1 == Zero) - { - // Debug = "TB:UGIO - Make sure USB is off" - If (GGDV (0x02060001) == One) - { - // Debug = "TB:UGIO - Turn off USB GPIO" - SGOV (0x02060001, Zero) - SGDO (0x02060001) - Local3 = One - - Debug = "TB:UGIO - Disable USB" - } - } - - If (Local3 != Zero) - { - Sleep (0x64) - } - - If (Local2 != Zero) - { - // Debug = "TB:UGIO - Either TB or USB powerstate changed" - } - - // One if status of TB or USB changed to on - Return (Local2) - } - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 - { - Debug = "TB:_PS0" - - \_SB.PCI0.RP09.XPS0() - - If (OSDW ()) - { - PCEU () - } - } - - Method (_PS3, 0, Serialized) // _PS3: Power State 3 - { - Debug = "TB:_PS3" - - If (OSDW ()) - { - If (\_SB.PCI0.RP09.POFX () != Zero) - { - \_SB.PCI0.RP09.CTBT () - } - - PCDA () - } - - \_SB.PCI0.RP09.XPS3() - } - - Method (TGPE, 0, Serialized) - { - Debug = "TB:TGPE" - - Notify (\_SB.PCI0.RP09, 0x02) // Device Wake - } - - Method (UTLK, 2, Serialized) - { - Debug = "TB:UTLK" - - Local0 = Zero - - // if CIO force power is zero - If ((GGOV (0x02060000) == Zero) && (GGDV (0x02060000) == Zero)) - // If (Zero) - { - \_SB.PCI0.RP09.PSTX = Zero - While (One) - { - If (\_SB.PCI0.RP09.LDXX == One) - { - \_SB.PCI0.RP09.LDXX = Zero - } - - // here, we force CIO power on - SGDI (0x02060000) - Local1 = Zero - Local2 = (Timer + 0x00989680) - - While (Timer <= Local2) - { - If (\_SB.PCI0.RP09.LACR == Zero) - { - If (\_SB.PCI0.RP09.LTRN != One) + If (UPCK ()) { + Local1 = One Break } } - ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + } + + Sleep (One) + Local0-- + } + + Return (Local1) + } + + /** + * Downlink training check + */ + Method (DLTC, 0, Serialized) + { + // Debug = "TB:DLTC" + + If (RPLT == Zero) + { + If (UPLT == Zero) + { + If (DPLT == Zero) { - Break + Return (One) } - - Sleep (0x0A) } + } - Sleep (Arg1) - While (Timer <= Local2) + Return (Zero) + } + + /** + * Wait for downlink training + */ + Method (WTDL, 0, Serialized) + { + // Debug = "TB:WTDL" + + Local0 = 0x07D0 + Local1 = Zero + While (Local0) + { + If (RPR4 == 0x07) { - If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + If (DLTC ()) { - Local1 = One - Break + If (UPCK ()) + { + Local1 = One + Break + } } - - Sleep (0x0A) } - If (Local1 == One) - { - \_SB.PCI0.RP09.MABT = One - Break - } + Sleep (One) + Local0-- + } - If (Local0 == 0x04) - { - Break - } + Return (Local1) + } - Local0++ - // CIO force power back to 0 - SGOV (0x02060000, Zero) - SGDO (0x02060000) - Sleep (0x03E8) + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + /** + * Bring up PCI link + * Train downstream link + */ + Method (PCEU, 0, Serialized) + { + Debug = "TB:PCEU" + \_SB.PCI0.RP09.PRSR = Zero + + Debug = "TB:PCEU - Put upstream bridge back into D0 " + If (\_SB.PCI0.RP09.PSTX != Zero) + { + Debug = "TB:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.PSTX = Zero + } + + If (\_SB.PCI0.RP09.LDXX == One) + { + Debug = "TB:PCEU - Clear link disable on upstream bridge" + Debug = "TB:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.LDXX = Zero + } + + If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRTE != Zero) + { + Debug = "TB:PCEU - XRST changed, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRST (Zero) } } - Debug = "UTLK: Up Stream VID/DID =" - Debug = \_SB.PCI0.RP09.UPSB.AVND - Debug = "UTLK: Root Port VID/DID =" - Debug = \_SB.PCI0.RP09.AVND - // Debug = "UTLK: Root Port PRIB =" - // Debug = \_SB.PCI0.RP09.PRIB - // Debug = "UTLK: Root Port SECB =" - // Debug = \_SB.PCI0.RP09.SECB - // Debug = "UTLK: Root Port SUBB =" - // Debug = \_SB.PCI0.RP09.SUBB - } - - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (HD94, PCI_Config, 0x0D94, 0x08) - Field (HD94, ByteAcc, NoLock, Preserve) - { - Offset (0x04), - PLEQ, 1, - Offset (0x08) - } - - OperationRegion (A1E1, PCI_Config, 0x40, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDXX, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0xA0, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTX, 2 - } - - // OperationRegion (OE2H, PCI_Config, 0xE2, One) - // Field (OE2H, ByteAcc, NoLock, Preserve) - // { - // , 2, - // L23E, 1, - // L23D, 1 - // } - - // OperationRegion (DMIH, PCI_Config, 0x0324, One) - // Field (DMIH, ByteAcc, NoLock, Preserve) - // { - // , 3, - // LEDM, 1 - // } - - OperationRegion (A1E3, PCI_Config, 0x0200, 0x20) - Field (A1E3, ByteAcc, NoLock, Preserve) - { - Offset (0x14), - Offset (0x16), - PSTS, 4 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - /** - * PXSX replaced by UPSB - */ - Scope (PXSX) - { - Method (_STA, 0, NotSerialized) + /** + * Bring down PCI link + */ + Method (PCDA, 0, Serialized) { - Return (Zero) // hidden - } - } + Debug = "TB:PCDA" + If (\_SB.PCI0.RP09.POFX () != Zero) + { + \_SB.PCI0.RP09.PCIA = Zero + + Debug = "TB:PCDA - Put upstream bridge into D3" + \_SB.PCI0.RP09.PSTX = 0x03 + + Debug = "TB:PCDA - Set link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = One + + Local5 = (Timer + 10000000) + While (Timer <= Local5) + { + Debug = "TB:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.LACR == One) + { + If (\_SB.PCI0.RP09.LACT == Zero) + { + Debug = "TB:PCDA - No link activity" + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) + { + Debug = "TB:PCDA - UPSB is down - VID/DID is -1" + Break + } + + Sleep (0x0A) + } + + Debug = "TB:PCDA - Request PCI-GPIO to be disabled" + \_SB.PCI0.RP09.GPCI = Zero + \_SB.PCI0.RP09.UGIO () + } + Else + { + Debug = "TB:PCDA - Already disabled, not disabling" + } + + \_SB.PCI0.RP09.IIP3 = One + } + + /** + * Returns true if both TB and TB-USB are idle + */ + Method (POFX, 0, Serialized) + { + Debug = Concatenate ("TB:POFX - Result (!RTBT && !RUSB): ", (!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB)) + + Return ((!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB)) + } + + Name (GPCI, One) + Name (GNHI, One) + Name (GXCI, One) + Name (RTBT, One) + Name (RUSB, One) + Name (CTPD, Zero) + + + /** + * Send power down ack to CP + */ + Method (CTBT, 0, Serialized) + { + Debug = "TB:CTBT" + + // If ((GGDV (CPGN) == One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + // If ((\_GPE.TFPS () == One) && \_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Debug = "TB:CTBT - UPSB-device enabled" + Local2 = \_SB.PCI0.RP09.UPSB.CRMW (0x3C, Zero, 0x02, 0x04000000, 0x04000000) + + If (Local2 == Zero) + { + Debug = "TB:CTBT - Set CP_ACK_POWERDOWN_OVERRIDE" + \_SB.PCI0.RP09.CTPD = One + } + } + Else + { + Debug = "TB:CTBT - UPSB-device disabled" + } + } + + /** + * Set once we do a force power + * Then when NHI comes up we do a ICM reset. We have to wait for + * NHI because we have to use it to send the ICM reset. + */ + Name (IRST, Zero) + + + /** + * Toggle controller power + * + * Power controllers either up or down depending on the request. + * On Macs, there's two GPIO signals for controlling TB and XHC + * separately. If such signals exist, we need to find it. Otherwise + * we lose the power saving capabilities. + * + * Returns non-zero Local2 if GPIOs changed and reinit is necessary + */ + Method (UGIO, 0, Serialized) + { + Debug = "TB:UGIO" + + If (\_SB.PCI0.RP09.GPCI == Zero) + { + Debug = "TB:UGIO - PCI wants off (GPCI)" + } + Else + { + Debug = "TB:UGIO - PCI wants on (GPCI)" + } + + If (\_SB.PCI0.RP09.GNHI == Zero) + { + Debug = "TB:UGIO - NHI wants off (GNHI)" + } + Else + { + Debug = "TB:UGIO - NHI wants on (GNHI)" + } + + If (\_SB.PCI0.RP09.GXCI == Zero) + { + Debug = "TB:UGIO - XHCI wants off (GXCI)" + } + Else + { + Debug = "TB:UGIO - XHCI wants on (GXCI)" + } + + If (\_SB.PCI0.RP09.RTBT == Zero) + { + Debug = "TB:UGIO - TBT allows off (RTBT)" + } + Else + { + Debug = "TB:UGIO - TBT forced on (RTBT)" + } + + If (\_SB.PCI0.RP09.RUSB == Zero) + { + Debug = "TB:UGIO - USB allows off (RUSB)" + } + Else + { + Debug = "TB:UGIO - USB forced on (RUSB)" + } + + // Which controller is requested to be on? + Local0 = (\_SB.PCI0.RP09.GNHI || \_SB.PCI0.RP09.RTBT) // TBT + Local1 = (\_SB.PCI0.RP09.GXCI || \_SB.PCI0.RP09.RUSB) // USB + + If (\_SB.PCI0.RP09.GPCI != Zero) + { + // if neither are requested to be on but the NHI controller + // needs to be up, then we go ahead and power it on anyways + If ((Local0 == Zero) && (Local1 == Zero)) + { + Local0 = One + Local1 = One + } + } + + If (Local0 == Zero) + { + Debug = "TB:UGIO - TBT GPIO should be off" + } + Else + { + Debug = "TB:UGIO - TBT GPIO should be on" + } + + If (Local1 == Zero) + { + Debug = "TB:UGIO - USB GPIO should be off" + } + Else + { + Debug = "TB:UGIO - USB GPIO should be on" + } + + Local2 = Zero + + /** + * Force power to CIO + */ + If (Local0 != Zero) + { + Debug = "TB:UGIO - Make sure TBT is on" + + // TODO: check if CIO power is forced + //If (GGDV (0x01070004) == Zero) + If (Zero) + { + Debug = "TB:UGIO - Turn on TBT GPIO" + + // TODO: force CIO power + //SGDI (0x01070004) + Local2 = One + + \_SB.PCI0.RP09.CTPD = Zero + } + } + + /** + * Force power to USB + */ + If (Local1 != Zero) + { + Debug = "TB:UGIO - Make sure USB is on" + + // TODO: check if USB power is forced + //If (GGDV (0x01070007) == Zero) + If (Zero) + { + // TODO: force USB power + //SGDI (0x01070007) + Local2 = One + } + } + + // if we did power on + If (Local2 != Zero) + { + Sleep (500) + } + + Local3 = Zero + + /** + * Disable force power to CIO + */ + If (Local0 == Zero) + { + Debug = "TB:UGIO - Make sure TBT is off" + + // TODO: check if CIO power is off + //If (GGDV (0x01070004) == One) + If (Zero) + { + \_SB.PCI0.RP09.CTBT () + + If (\_SB.PCI0.RP09.CTPD != Zero) + { + Debug = "TB:UGIO - Turn off TBT GPIO" + + // TODO: force power off CIO + //SGOV (0x01070004, Zero) + //SGDO (0x01070004) + Local3 = One + } + } + } + + /** + * Disable force power to USB + */ + If (Local1 == Zero) + { + Debug = "TB:UGIO - Make sure USB is off" + + //If (GGDV (0x01070007) == One) + If (Zero) + { + // TODO: force power off USB + //SGOV (0x01070007, Zero) + //SGDO (0x01070007) + Local3 = One + } + } + + // if we did power down, wait for things to settle + If (Local3 != Zero) + { + Sleep (100) + } + + Debug = Concatenate ("TB:UGIO finished - Result: ", Local2) + + Return (Local2) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:_PS0" + + If (OSDW () && \TWIN != Zero) + { + PCEU () + + \_SB.PCI0.RP09.TBST () + } + ElseIf (CondRefOf (\_SB.PCI0.RP09.XPS0)) + { + \_SB.PCI0.RP09.XPS0 () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:_PS3" + + If (OSDW () && \TWIN != Zero) + { + If (\_SB.PCI0.RP09.POFX () != Zero) + { + \_SB.PCI0.RP09.CTBT () + } + + PCDA () + + \_SB.PCI0.RP09.TBST () + } + ElseIf (CondRefOf (\_SB.PCI0.RP09.XPS3)) + { + \_SB.PCI0.RP09.XPS3 () + } + } + + Method (TGPE, 0, Serialized) + { + Debug = "TB:TGPE" + + Notify (\_SB.PCI0.RP09, 0x02) // Device Wake + } + + Method (UTLK, 2, Serialized) + { + Debug = "TB:UTLK" + + Local0 = Zero + + // if CIO force power is zero + If (Zero) + // If ((GGOV (CPGN) == Zero) && (GGDV (CPGN) == Zero)) + // If (\_GPE.TFPS () == Zero) + { + \_SB.PCI0.RP09.PSTX = Zero + + While (One) + { + If (\_SB.PCI0.RP09.LDXX == One) + { + \_SB.PCI0.RP09.LDXX = Zero + } + + // here, we force CIO power on + // SGDI (CPGN) + // \_SB.TBFP (One) + + Local1 = Zero + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Break + } + + Sleep (0x0A) + } + + Sleep (Arg1) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Local1 = One + Break + } + + Sleep (0x0A) + } + + If (Local1 == One) + { + \_SB.PCI0.RP09.MABT = One + Break + } + + If (Local0 == 0x04) + { + Break + } + + Local0++ + + // CIO force power back to 0 + // SGOV (CPGN, Zero) + // SGDO (CPGN) + // \_SB.TBFP (Zero) + + Sleep (0x03E8) + } + } + + Debug = Concatenate ("UTLK: Up Stream VID/DID: ", \_SB.PCI0.RP09.UPSB.AVND) + Debug = Concatenate ("UTLK: Root Port VID/DID: ", \_SB.PCI0.RP09.AVND) + Debug = Concatenate ("UTLK: Root Port PRIB: ", \_SB.PCI0.RP09.PRIB) + Debug = Concatenate ("UTLK: Root Port SECB: ", \_SB.PCI0.RP09.SECB) + Debug = Concatenate ("UTLK: Root Port SUBB: ", \_SB.PCI0.RP09.SUBB) + } - Device (UPSB) - { - Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { @@ -1466,7 +1543,15 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + OperationRegion (HD94, PCI_Config, 0x0D94, 0x08) + Field (HD94, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + PLEQ, 1, + Offset (0x08) + } + + OperationRegion (A1E1, PCI_Config, 0x40, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), @@ -1482,7 +1567,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) LACR, 1, Offset (0x10), , 4, - LDIS, 1, + LDXX, 1, LRTN, 1, Offset (0x12), CSPD, 4, @@ -1496,28 +1581,36 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) TSPD, 4 } - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + OperationRegion (A1E2, PCI_Config, 0xA0, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), - PSTA, 2 + PSTX, 2 } - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + OperationRegion (OE2H, PCI_Config, 0xE2, One) + Field (OE2H, ByteAcc, NoLock, Preserve) { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.SECB */ + , 2, + L23X, 1, + L23D, 1 } - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (DMIH, PCI_Config, 0x0324, One) + Field (DMIH, ByteAcc, NoLock, Preserve) { - If (TBTS != One) - { - Return (Zero) - } + , 3, + LEDX, 1 + } - Return (0x0F) + OperationRegion (A1E3, PCI_Config, 0x0200, 0x20) + Field (A1E3, ByteAcc, NoLock, Preserve) + { + Offset (0x14), + Offset (0x16), + PSTS, 4 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -1526,880 +1619,27 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) } /** - * Enable downstream link - */ - Method (PCED, 0, Serialized) + * PXSX replaced by UPSB on OSX + */ + Scope (PXSX) { - Debug = "TB:UPSB:PCED - Enable downstream link" - // Debug = "TB:UPSB:PCED - enable GPIO" - \_SB.PCI0.RP09.GPCI = One - - // power up the controller - If (\_SB.PCI0.RP09.UGIO () != Zero) + Method (_STA, 0, NotSerialized) { - // Debug = "TB:UPSB:PCED - GPIOs changed, restored = true" - \_SB.PCI0.RP09.PRSR = One - } - - Local0 = Zero - Local1 = Zero - - If (Local1 == Zero) - { - If (\_SB.PCI0.RP09.IIP3 != Zero) + If (OSDW () && \TWIN != Zero) { - \_SB.PCI0.RP09.PRSR = One - Local0 = One - - // Debug = "TB:UPSB:PCED - Set link disable on upstream bridge" - \_SB.PCI0.RP09.LDXX = One - } - } - - Local5 = (Timer + 0x00989680) - - // Debug = "TB:UPSB:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" - // Debug = \_SB.PCI0.RP09.PRSR - - If (\_SB.PCI0.RP09.PRSR != Zero) - { - // Debug = "TB:UPSB:PCED - Wait for power up" - Sleep (0x1E) - - If ((Local0 != Zero) || (Local1 != Zero)) - { - \_SB.PCI0.RP09.TSPD = One - - If (Local1 != Zero) {} - ElseIf (Local0 != Zero) - { - // Debug = "TB:UPSB:PCED - Clear link disable on upstream bridge" - \_SB.PCI0.RP09.LDXX = Zero - } - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:PCED - Wait for link training..." - If (\_SB.PCI0.RP09.LACR == Zero) - { - If (\_SB.PCI0.RP09.LTRN != One) - { - // Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared" - Break - } - } - ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) - { - // Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared and link is active" - Break - } - - Sleep (0x0A) - } - - Sleep (0x78) - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:PCED - PEG WA - Wait for config space..." - - If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) - { - // Debug = "TB:UPSB:PCED - PEG WA - Read VID/DID - _SB.PCI0.RP09.UPSB.AVND:" - Debug = \_SB.PCI0.RP09.UPSB.AVND - - Break - } - - Sleep (0x0A) - } - - \_SB.PCI0.RP09.TSPD = 0x03 - \_SB.PCI0.RP09.LRTN = One + Return (Zero) // hidden for OSX } - // Debug = "TB:UPSB:PCED - Wait for downstream bridge to appear" - Local5 = (Timer + 0x00989680) - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:PCED - Wait for link training..." - - If (\_SB.PCI0.RP09.LACR == Zero) - { - If (\_SB.PCI0.RP09.LTRN != One) - { - // Debug = "TB:UPSB:PCED - Link training cleared" - Break - } - } - ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) - { - // Debug = "TB:UPSB:PCED - Link training cleared and link is active" - Break - } - - Sleep (0x0A) - } - - Sleep (0xFA) - } - - \_SB.PCI0.RP09.PRSR = Zero - While (Timer <= Local5) - { - // Debug = "TB:UPSB:PCED - Wait for config space..." - If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) - { - // Debug = "TB:UPSB:PCED - Read VID/DID" - Break - } - - Sleep (0x0A) - } - - If (\_SB.PCI0.RP09.CSPD != 0x03) - { - If (\_SB.PCI0.RP09.SSPD == 0x03) - { - If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) - { - If (\_SB.PCI0.RP09.TSPD != 0x03) - { - \_SB.PCI0.RP09.TSPD = 0x03 - } - - If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) - { - \_SB.PCI0.RP09.UPSB.TSPD = 0x03 - } - - \_SB.PCI0.RP09.LRTN = One - Local2 = (Timer + 0x00989680) - While (Timer <= Local2) - { - If (\_SB.PCI0.RP09.LACR == Zero) - { - If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) - { - \_SB.PCI0.RP09.PCIA = One - Local1 = One - Break - } - } - ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && - (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) - { - \_SB.PCI0.RP09.PCIA = One - Local1 = One - Break - } - - Sleep (0x0A) - } - } - Else - { - \_SB.PCI0.RP09.PCIA = One - } - } - Else - { - \_SB.PCI0.RP09.PCIA = One - } - } - Else - { - \_SB.PCI0.RP09.PCIA = One - } - - \_SB.PCI0.RP09.IIP3 = Zero - } - - /** - * Hotplug notify - Called by ACPI - */ - Method (AMPE, 0, Serialized) - { - Debug = "TB:UPSB:AMPE - Hotplug notify called by ACPI" - - Notify (\_SB.PCI0.RP09.UPSB.DSB0.NHI0, Zero) // Bus Check - } - - /** - * Hotplug notify - * - * MUST called by NHI driver indicating cable plug-in - * This passes the message to the XHC driver - */ - Method (UMPE, 0, Serialized) - { - Debug = "TB:UPSB:UMPE - Hotplug notify on cable called by NHI" - - If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2)) - { - Debug = "TB:UPSB:UMPE - Notified XHC2" - Notify (\_SB.PCI0.RP09.UPSB.DSB2.XHC2, Zero) // Bus Check - } - - If (CondRefOf (\_SB.PCI0.XHC1)) - { - Debug = "TB:UPSB:UMPE - Notified XHC1" - Notify (\_SB.PCI0.XHC1, Zero) // Bus Check + Return (0x0F) // visible for others } } - Name (MDUV, One) // plug status - - /** - * Cable status callback - * Called from NHI driver on hotplug - */ - Method (MUST, 1, Serialized) + If (\TWIN != Zero) { - // Debug = "TB:UPSB:MUST - Cable status callback from NHI" - // Debug = "TB:UPSB:MUST - Plug status Arg0: " - // Debug = Arg0 - // Debug = "TB:UPSB:MUST - Plug status MDUV: " - // Debug = MDUV - If (OSDW ()) - { - If (MDUV != Arg0) - { - If (Arg0 == One) - { - Debug = "TB:UPSB:MUST - Cable status callback from NHI - status changed - plugged (MDUV = One)" - } - Else - { - Debug = "TB:UPSB:MUST - Cable status callback from NHI - status changed - unplugged (MDUV = Zero)" - } - - MDUV = Arg0 - UMPE () - } - Else - { - Debug = "TB:UPSB:MUST - Cable status callback from NHI - status unchanged" - } - } - - Return (Zero) - } - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 - { - Debug = "TB:UPSB:_PS0" - - If (OSDW ()) - { - PCED () // enable downlink - - // some magical commands to CIO - \_SB.PCI0.RP09.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200) - \_SB.PCI0.RP09.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200) - } - } - - Method (_PS3, 0, Serialized) // _PS3: Power State 3 - { - Debug = "TB:UPSB:_PS3" - - If (!OSDW ()) - { - If (\_SB.PCI0.RP09.UPCK () == Zero) - { - // Debug = "TB:UPSB:_PS3 calling UTLK _PS3" - \_SB.PCI0.RP09.UTLK (One, 0x03E8) - } - Else - { - // Debug = "TB:UPSB:_PS3 - UTLK OK" - } - - \_SB.PCI0.RP09.TBTC (0x05) - } - } - - OperationRegion (H548, PCI_Config, 0x0548, 0x20) - Field (H548, DWordAcc, Lock, Preserve) - { - T2PC, 32, - PC2T, 32 - } - - OperationRegion (H530, PCI_Config, 0x0530, 0x0C) - Field (H530, DWordAcc, Lock, Preserve) - { - DWIX, 13, - PORT, 6, - SPCE, 2, - CMD0, 1, - CMD1, 1, - CMD2, 1, - , 6, - PROG, 1, - TMOT, 1, - WDAT, 32, - RDAT, 32 - } - - /** - * CIO write - */ - Method (CIOW, 4, Serialized) - { - // Debug = "TB:UPSB:CIOW" - - WDAT = Arg3 - // Debug = "TB:UPSB:CIOW - WDAT" - // Debug = WDAT /* \_SB_.PCI0.RP09.UPSB.WDAT */ - - DWIX = Arg0 - PORT = Arg1 - SPCE = Arg2 - CMD0 = One - CMD1 = Zero - CMD2 = Zero - TMOT = Zero - PROG = One - - Local1 = One - Local0 = 0x2710 - - While (Zero < Local0) - { - If (PROG == Zero) - { - Local1 = Zero - Break - } - - Stall (0x19) - Local0-- - } - - If (Local1 == Zero) - { - Local1 = TMOT /* \_SB_.PCI0.RP09.UPSB.TMOT */ - } - - If (Local1 != Zero) - { - Debug = "TB:UPSB:CIOW - Error" - Debug = Local1 - } - - Return (Local1) - } - - /** - * CIO read - */ - Method (CIOR, 3, Serialized) - { - // Debug = "TB:UPSB:CIOR" - - RDAT = Zero - DWIX = Arg0 - PORT = Arg1 - SPCE = Arg2 - CMD0 = Zero - CMD1 = Zero - CMD2 = Zero - TMOT = Zero - PROG = One - - Local1 = One - Local0 = 0x2710 - - While (Zero < Local0) - { - If (PROG == Zero) - { - Local1 = Zero - Break - } - - Stall (0x19) - Local0-- - } - - If (Local1 == Zero) - { - Local1 = TMOT /* \_SB_.PCI0.RP09.UPSB.TMOT */ - } - - If (Local1) - { - Debug = "TB:UPSB:CIOR - Error" - Debug = Local1 - } - - // Debug = "TB:UPSB:CIOR - RDAT" - // Debug = RDAT /* \_SB_.PCI0.RP09.UPSB.RDAT */ - - If (Local1 == Zero) - { - Return (Package (0x02) - { - Zero, - RDAT - }) - } - Else - { - Return (Package (0x02) - { - One, - RDAT - }) - } - } - - /** - * CIO Read Modify Write - */ - Method (CRMW, 5, Serialized) - { - // Debug = "TB:UPSB:CRMW" - - // Debug = "TB:UPSB:CRMW - AVND:" - // Debug = \_SB.PCI0.RP09.UPSB.AVND - - // Debug = "TB:UPSB:CRMW - GGDV (0x02060000):" - // Debug = GGDV (0x02060000) - - // Debug = "TB:UPSB:CRMW - GGDV (0x02060001):" - // Debug = GGDV (0x02060001) - - - Local1 = One - If (((GGDV (0x02060000) == One) || (GGDV (0x02060001) == One)) && - (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) - // If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) - { - // Debug = "TB:UPSB:CRMW - TBT domain is enabled" - Local3 = Zero - - While (Local3 <= 0x04) - { - Local2 = CIOR (Arg0, Arg1, Arg2) - If (DerefOf (Local2 [Zero]) == Zero) - { - Local2 = DerefOf (Local2 [One]) - // Debug = "TB:UPSB:CRMW - Read Value" - // Debug = Local2 - - Local2 &= ~Arg4 - Local2 |= Arg3 - // Debug = "TB:UPSB:CRMW - Write Value" - // Debug = Local2 - - Local2 = CIOW (Arg0, Arg1, Arg2, Local2) - - If (Local2 == Zero) - { - Local2 = CIOR (Arg0, Arg1, Arg2) - - If (DerefOf (Local2 [Zero]) == Zero) - { - Local2 = DerefOf (Local2 [One]) - // Debug = "TB:UPSB:CRMW - Read Value 2" - // Debug = Local2 - - Local2 &= Arg4 - - If (Local2 == Arg3) - { - // Debug = "TB:UPSB:CRMW - Success" - - Local1 = Zero - - Break - } - } - } - } - - Local3++ - Sleep (0x64) - } - } - - If (Local1 != Zero) - { - Debug = "TB:UPSB:CRMW - Error value" - Debug = Local1 - } - - Return (Local1) - } - - /** - * Used in PTS/WAK - */ - Method (LSTX, 2, Serialized) - { - Debug = "TB:UPSB:LSTX" - - If (T2PC != 0xFFFFFFFF) - { - Local0 = Zero - If ((T2PC & One) && One) - { - Local0 = One - } - - If (Local0 == Zero) - { - Local1 = 0x2710 - While (Zero < Local1) - { - If (T2PC == Zero) - { - Break - } - - Stall (0x19) - Local1-- - } - - If (Zero == Local1) - { - Local0 = One - } - } - - If (Local0 == Zero) - { - Local1 = One - Local1 |= 0x14 - Local1 |= (Arg0 << 0x08) - Local1 |= (Arg1 << 0x0C) - Local1 |= 0x00400000 - PC2T = Local1 - } - - If (Local0 == Zero) - { - Local1 = 0x2710 - - While (Zero < Local1) - { - If (T2PC == 0x15) - { - Break - } - - Stall (0x19) - Local1-- - } - - If (Zero == Local1) - { - Local0 = One - } - } - - Sleep (0x0A) - PC2T = Zero - } - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Name (IIP3, Zero) - Name (PRSR, Zero) - Name (PCIA, One) - - /** - * Enable Upstream link - */ - Method (PCEU, 0, Serialized) - { - Debug = "TB:UPSB:DSB0:PCEU - Enable Upstream link" - - \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero - - // Debug = "TB:UPSB:DSB0:PCEU - Put upstream bridge back into D0 " - If (\_SB.PCI0.RP09.UPSB.DSB0.PSTA != Zero) - { - // Debug = "TB:UPSB:DSB0:PCEU - exit D0, restored = true" - \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One - \_SB.PCI0.RP09.UPSB.DSB0.PSTA = Zero - } - - If (\_SB.PCI0.RP09.UPSB.DSB0.LDIS == One) - { - // Debug = "TB:UPSB:DSB0:PCEU - Clear link disable on upstream bridge" - // Debug = "TB:UPSB:DSB0:PCEU - clear link disable, restored = true" - \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One - \_SB.PCI0.RP09.UPSB.DSB0.LDIS = Zero - } - } - - /** - * Bring down PCI link - */ - Method (PCDA, 0, Serialized) - { - Debug = "TB:UPSB:DSB0:PCDA - Bring down PCI link" - - If (\_SB.PCI0.RP09.UPSB.DSB0.POFX () != Zero) - { - \_SB.PCI0.RP09.UPSB.DSB0.PCIA = Zero - - // Debug = "TB:UPSB:DSB0:PCDA - Put upstream bridge into D3" - \_SB.PCI0.RP09.UPSB.DSB0.PSTA = 0x03 - - // Debug = "TB:UPSB:DSB0:PCDA - Set link disable on upstream bridge" - \_SB.PCI0.RP09.UPSB.DSB0.LDIS = One - - Local5 = (Timer + 0x00989680) - While (Timer <= Local5) - { - // Debug = "TB:UPSB:DSB0:PCDA - Wait for link to drop..." - If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == One) - { - If (\_SB.PCI0.RP09.UPSB.DSB0.LACT == Zero) - { - // Debug = "TB:UPSB:DSB0:PCDA - No link activity" - Break - } - } - ElseIf (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND == 0xFFFFFFFF) - { - // Debug = "TB:UPSB:DSB0:PCDA - VID/DID is -1" - Break - } - - Sleep (0x0A) - } - - // Debug = "TB:UPSB:DSB0:PCDA - disable GPIO & run UGIO()" - \_SB.PCI0.RP09.GNHI = Zero - \_SB.PCI0.RP09.UGIO () - } - Else - { - // Debug = "TB:UPSB:DSB0:PCDA - Not disabling" - } - - \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = One - } - - /** - * Check if TB is idle - */ - Method (POFX, 0, Serialized) - { - If (!\_SB.PCI0.RP09.RTBT) - { - Debug = "TB:UPSB:DSB0:POFX - TB is idle (RTBT = Zero)" - } - Else - { - Debug = "TB:UPSB:DSB0:POFX - TB is active (RTBT != Zero)" - } - - Return (!\_SB.PCI0.RP09.RTBT) - } - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 - { - Debug = "TB:UPSB:DSB0:_PS0" - - If (OSDW ()) - { - PCEU () - } - } - - Method (_PS3, 0, Serialized) // _PS3: Power State 3 - { - Debug = "TB:UPSB:DSB0:_PS3" - - If (OSDW ()) - { - PCDA () - } - } - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - If (OSDW ()) - { - If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) - { - Local0 = Package (0x02) - { - "PCIHotplugCapable", - Zero - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Return (Zero) - } - - /** - * Thunderbolt NHI controller - */ - Device (NHI0) + Device (UPSB) { Name (_ADR, Zero) // _ADR: Address - Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String - - /** - * Enable downstream link - */ - Method (PCED, 0, Serialized) - { - Debug = "TB:UPSB:NHI0:PCED - Enable downstream link" - - // Debug = "TB:UPSB:NHI0:PCED - enable GPIO" - \_SB.PCI0.RP09.GNHI = One - - // we should not need to force power since - // UPSX init should already have done so! - If (\_SB.PCI0.RP09.UGIO () != Zero) - { - // Debug = "TB:UPSB:NHI0:PCED - GPIOs changed, restored = true" - \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One - } - - Local0 = Zero - Local1 = Zero - Local5 = (Timer + 0x00989680) - - // Debug = "TB:UPSB:NHI0:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" - Debug = \_SB.PCI0.RP09.UPSB.DSB0.PRSR - - If (\_SB.PCI0.RP09.UPSB.DSB0.PRSR != Zero) - { - // Debug = "TB:UPSB:NHI0:PCED - Wait for power up" - // Debug = "TB:UPSB:NHI0:PCED - Wait for downstream bridge to appear" - Local5 = (Timer + 0x00989680) - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:NHI0:PCED - Wait for link training..." - If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == Zero) - { - If (\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) - { - // Debug = "TB:UPSB:NHI0:PCED - Link training cleared" - Break - } - } - ElseIf ((\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) && (\_SB.PCI0.RP09.UPSB.DSB0.LACT == One)) - { - // Debug = "TB:UPSB:NHI0:PCED - Link training cleared and link is active" - Break - } - - Sleep (0x0A) - } - - Sleep (0x96) - } - - \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:NHI0:PCED - Wait for config space..." - If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND != 0xFFFFFFFF) - { - // Debug = "TB:UPSB:NHI0:PCED - Read VID/DID" - \_SB.PCI0.RP09.UPSB.DSB0.PCIA = One - Break - } - - Sleep (0x0A) - } - - \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = Zero - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { @@ -2414,361 +1654,1211 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } - /** - * Run Time Power Check - * Called by NHI driver when link is idle. - * Once both XHC and NHI idle, we can power down. - */ - Method (RTPC, 1, Serialized) + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Debug = "TB:UPSB:_STA()" + If (OSDW ()) { - If (Arg0 <= One) + Return (0xF) // visible for OSX + } + + Return (Zero) // hidden for others + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.SECB */ + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + /** + * Enable downstream link + */ + Method (PCED, 0, Serialized) + { + Debug = "TB:UPSB:PCED" + Debug = "TB:UPSB:PCED - Request TB-GPIO to be enabled" + \_SB.PCI0.RP09.GPCI = One + + // power up the controller + If (\_SB.PCI0.RP09.UGIO () != Zero) + { + Debug = "TB:UPSB:PCED - GPIOs changed, restored = true" + \_SB.PCI0.RP09.PRSR = One + } + + Local0 = Zero + Local1 = Zero + + If (\_SB.PCI0.RP09.IIP3 != Zero) + { + \_SB.PCI0.RP09.PRSR = One + + Local0 = One + + Debug = "TB:UPSB:PCED - Set link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = One + } + + Local5 = (Timer + 0x00989680) + + Debug = Concatenate ("TB:UPSB:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR: ", \_SB.PCI0.RP09.PRSR) + + If (\_SB.PCI0.RP09.PRSR != Zero) + { + Debug = "TB:UPSB:PCED - Wait for power up" + + Sleep (0x1E) + + If ((Local0 != Zero) || (Local1 != Zero)) { - If (Arg0 == One) + \_SB.PCI0.RP09.TSPD = One + + If (Local1 != Zero) {} + ElseIf (Local0 != Zero) { - Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - Running" + Debug = "TB:UPSB:PCED - Clear link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = Zero } - If (Arg0 == Zero) + While (Timer <= Local5) { - Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - Idle" + Debug = "TB:UPSB:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared and link is active" + Break + } + + Sleep (0x0A) } - \_SB.PCI0.RP09.RTBT = Arg0 + Sleep (0x78) + While (Timer <= Local5) + { + Debug = "TB:UPSB:PCED - PEG WA - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Debug = "TB:UPSB:PCED - UPSB UP - Read VID/DID" + Break + } + + Sleep (0x0A) + } + + \_SB.PCI0.RP09.TSPD = 0x03 + \_SB.PCI0.RP09.LRTN = One + } + + Debug = "TB:UPSB:PCED - Wait for downstream bridge to appear" + Local5 = (Timer + 0x00989680) + While (Timer <= Local5) + { + Debug = "TB:UPSB:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + Debug = "TB:UPSB:PCED - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Debug = "TB:UPSB:PCED - Link training cleared and link is active" + Break + } + + Sleep (0x0A) + } + + Sleep (0xFA) + } + + \_SB.PCI0.RP09.PRSR = Zero + + While (Timer <= Local5) + { + Debug = "TB:UPSB:PCED - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Debug = "TB:UPSB:PCED - UPSB up" + Break + } + + Sleep (0x0A) + } + + If (\_SB.PCI0.RP09.CSPD != 0x03) + { + If (\_SB.PCI0.RP09.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.TSPD != 0x03) + { + \_SB.PCI0.RP09.TSPD = 0x03 + } + + If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) + { + \_SB.PCI0.RP09.UPSB.TSPD = 0x03 + } + + \_SB.PCI0.RP09.LRTN = One + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + \_SB.PCI0.RP09.PCIA = One + Local1 = One + Break + } + } + ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && + (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + \_SB.PCI0.RP09.PCIA = One + Local1 = One + Break + } + + Sleep (0x0A) + } + } + Else + { + \_SB.PCI0.RP09.PCIA = One + } } Else { - Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - ??? - Arg0: " - Debug = Arg0 + \_SB.PCI0.RP09.PCIA = One } } + Else + { + \_SB.PCI0.RP09.PCIA = One + } + + \_SB.PCI0.RP09.IIP3 = Zero + } + + /** + * Hotplug notify + * Called by ACPI + */ + Method (AMPE, 0, Serialized) + { + Debug = "TB:UPSB:AMPE() - Hotplug notify to NHI0 by ACPI" + + Notify (\_SB.PCI0.RP09.UPSB.DSB0.NHI0, Zero) // Bus Check + } + + /** + * Hotplug notify + * + * MUST called by NHI driver indicating cable plug-in + * This passes the message to the XHC driver + */ + Method (UMPE, 0, Serialized) + { + Debug = "TB:UPSB:UMPE() - Hotplug notify XHC2 & XHC by NHI" + + Notify (\_SB.PCI0.RP09.UPSB.DSB2.XHC2, Zero) // Bus Check + + If (CondRefOf (\_SB.PCI0.XHC)) + { + Notify (\_SB.PCI0.XHC, Zero) // Bus Check + } + } + + Name (MDUV, One) // plug status + + /** + * Cable status callback + * Called from NHI driver on hotplug + */ + Method (MUST, 1, Serialized) + { + If (MDUV != Arg0) + { + Debug = Concatenate ("TB:UPSB:MUST calling Hotplug to XHC2 & XHC setting MDUV to: ", Arg0) + + MDUV = Arg0 + UMPE () + } + Else + { + Debug = Concatenate ("TB:UPSB:MUST not changed, leavin MDUV, called with args: ", Arg0) + } Return (Zero) } - /** - * Cable detection callback - * Called by NHI driver on hotplug - */ - Method (MUST, 1, Serialized) - { - Debug = "TB:UPSB:NHI0:MUST - Cable detection callback" - - Return (\_SB.PCI0.RP09.UPSB.MUST (Arg0)) - } - Method (_PS0, 0, Serialized) // _PS0: Power State 0 { - Debug = "TB:UPSB:NHI0:_PS0" + Debug = "TB:UPSB:_PS0" If (OSDW ()) { - PCED () - \_SB.PCI0.RP09.CTBT () + PCED () // enable downlink + + // some magical commands to CIO + \_SB.PCI0.RP09.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200) + \_SB.PCI0.RP09.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200) + + \_SB.PCI0.RP09.TBST () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { - Debug = "TB:UPSB:NHI0:_PS3" - } + Debug = "TB:UPSB:_PS3" - Method (TRPE, 2, Serialized) - { - Debug = "TB:UPSB:NHI0:TRPE - args:" - Debug = Arg0 - Debug = Arg1 + // If (!OSDW ()) + // { + // If (\_SB.PCI0.RP09.UPCK () == Zero) + // { + // Debug = "TB:UPSB:_PS3 - calling UTLK" + // \_SB.PCI0.RP09.UTLK (One, 0x03E8) + // } + // Else + // { + // Debug = "TB:UPSB:_PS3 - UTLK OK" + // } + + // \_SB.PCI0.RP09.TBTC (0x05) + // } If (OSDW ()) { - If (Arg0 <= One) + \_SB.PCI0.RP09.TBST () + } + } + + OperationRegion (H548, PCI_Config, 0x0548, 0x20) + Field (H548, DWordAcc, Lock, Preserve) + { + T2PC, 32, + PC2T, 32 + } + + OperationRegion (H530, PCI_Config, 0x0530, 0x0C) + Field (H530, DWordAcc, Lock, Preserve) + { + DWIX, 13, + PORT, 6, + SPCE, 2, + CMD0, 1, + CMD1, 1, + CMD2, 1, + , 6, + PROG, 1, + TMOT, 1, + WDAT, 32, + RDAT, 32 + } + + /** + * CIO write + */ + Method (CIOW, 4, Serialized) + { + WDAT = Arg3 + Debug = Concatenate ("TB:UPSB:CIOW - WDAT: ", WDAT) + + DWIX = Arg0 + PORT = Arg1 + SPCE = Arg2 + CMD0 = One + CMD1 = Zero + CMD2 = Zero + TMOT = Zero + PROG = One + Local1 = One + Local0 = 0x2710 + While (Zero < Local0) + { + If (PROG == Zero) { - If (Arg0 == Zero) + Local1 = Zero + Break + } + + Stall (0x19) + Local0-- + } + + If (Local1 == Zero) + { + Local1 = TMOT /* \_SB.PCI0.RP09.UPSB.TMOT */ + } + + If (Local1) + { + Debug = Concatenate ("TB:UPSB:CIOW - Error: ", Local1) + } + + Return (Local1) + } + + /** + * CIO read + */ + Method (CIOR, 3, Serialized) + { + RDAT = Zero + DWIX = Arg0 + PORT = Arg1 + SPCE = Arg2 + CMD0 = Zero + CMD1 = Zero + CMD2 = Zero + TMOT = Zero + PROG = One + + Local1 = One + Local0 = 0x2710 + + While (Zero < Local0) + { + If (PROG == Zero) + { + Local1 = Zero + Break + } + + Stall (0x19) + Local0-- + } + + If (Local1 == Zero) + { + Local1 = TMOT /* \_SB.PCI0.RP09.UPSB.TMOT */ + } + + If (Local1) + { + Debug = Concatenate ("TB:UPSB:CIOR - Error: ", Local1) + Debug = Concatenate ("TB:UPSB:CIOR - RDAT: ", RDAT) + } + + If (Local1 == Zero) + { + Return (Package () + { + Zero, + RDAT + }) + } + Else + { + Return (Package () + { + One, + RDAT + }) + } + } + + /** + * CIO Read Modify Write + */ + Method (CRMW, 5, Serialized) + { + Local1 = One + + // If (((GGDV (CPGN) == One) || (GGDV (0x02060001) == One)) && + // If (((GGDV (CPGN) == One)) && + // (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + // If ((\_GPE.TFPS () == One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Local3 = Zero + + While (Local3 <= 0x04) + { + Local2 = CIOR (Arg0, Arg1, Arg2) + + If (DerefOf (Local2 [Zero]) == Zero) { - \_SB.PCI0.RP09.PSTX = 0x03 - \_SB.PCI0.RP09.LDXX = One + Local2 = DerefOf (Local2 [One]) + // Debug = Concatenate ("TB:UPSB:CRMW - Read Value: ", Local2) - Local0 = (Timer + 0x00989680) + Local2 &= ~Arg4 + Local2 |= Arg3 + // Debug = Concatenate ("TB:UPSB:CRMW - Write Value: ", Local2) - While (Timer <= Local0) + Local2 = CIOW (Arg0, Arg1, Arg2, Local2) + + If (Local2 == Zero) { - If (\_SB.PCI0.RP09.LACR == One) + Local2 = CIOR (Arg0, Arg1, Arg2) + + If (DerefOf (Local2 [Zero]) == Zero) { - If (\_SB.PCI0.RP09.LACT == Zero) + Local2 = DerefOf (Local2 [One]) + // Debug = Concatenate ("TB:UPSB:CRMW - Read Value 2: ", Local2) + + Local2 &= Arg4 + + If (Local2 == Arg3) { + // Debug = "TB:UPSB:CRMW - Success" + + Local1 = Zero + Break } } - ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) + } + } + + Local3++ + + Sleep (0x64) + } + } + + If (Local1) + { + Debug = Concatenate ("TB:UPSB:CRMW - Error value: ", Local1) + } + + Return (Local1) + } + + /** + * Run on _PTS + */ + Method (LSTX, 2, Serialized) + { + Debug = "TB:UPSB:LSTX" + + If (T2PC != 0xFFFFFFFF) + { + Local0 = Zero + If ((T2PC & One) && One) + { + Local0 = One + } + + If (Local0 == Zero) + { + Local1 = 0x2710 + While (Zero < Local1) + { + If (T2PC == Zero) + { + Break + } + + Stall (0x19) + Local1-- + } + + If (Zero == Local1) + { + Local0 = One + } + } + + If (Local0 == Zero) + { + Local1 = One + Local1 |= 0x14 + Local1 |= (Arg0 << 0x08) + Local1 |= (Arg1 << 0x0C) + Local1 |= 0x00400000 + PC2T = Local1 + } + + If (Local0 == Zero) + { + Local1 = 0x2710 + While (Zero < Local1) + { + If (T2PC == 0x15) + { + Break + } + + Stall (0x19) + Local1-- + } + + If (Zero == Local1) + { + Local0 = One + } + } + + Sleep (0x0A) + PC2T = Zero + } + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + Method (PCEU, 0, Serialized) + { + Debug = "TB:DSB0:PCEU" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero + + Debug = "TB:DSB0:PCEU - Put upstream bridge back into D0 " + If (\_SB.PCI0.RP09.UPSB.DSB0.PSTA != Zero) + { + Debug = "TB:DSB0:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.PSTA = Zero + } + + If (\_SB.PCI0.RP09.UPSB.DSB0.LDIS == One) + { + Debug = "TB:DSB0:PCEU - Clear link disable on upstream bridge" + Debug = "TB:DSB0:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.LDIS = Zero + } + } + + Method (PCDA, 0, Serialized) + { + Debug = "TB:DSB0:PCDA" + + If (\_SB.PCI0.RP09.UPSB.DSB0.POFX () != Zero) + { + \_SB.PCI0.RP09.UPSB.DSB0.PCIA = Zero + Debug = "TB:DSB0:PCDA - Put upstream bridge into D3" + + \_SB.PCI0.RP09.UPSB.DSB0.PSTA = 0x03 + Debug = "TB:DSB0:PCDA - Set link disable on upstream bridge" + + \_SB.PCI0.RP09.UPSB.DSB0.LDIS = One + + Local5 = (Timer + 0x00989680) + + While (Timer <= Local5) + { + Debug = "TB:DSB0:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == One) + { + If (\_SB.PCI0.RP09.UPSB.DSB0.LACT == Zero) { + Debug = "TB:DSB0:PCDA - No link activity" + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND == 0xFFFFFFFF) + { + Debug = "TB:DSB0:PCDA - VID/DID is -1" + Break + } + + Sleep (0x0A) + } + + Debug = "TB:DSB0:PCDA - Request NHI-GPIO to be disabled" + \_SB.PCI0.RP09.GNHI = Zero + \_SB.PCI0.RP09.UGIO () + } + Else + { + Debug = "TB:DSB0:PCDA - Not disabling" + } + + \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = One + } + + Method (POFX, 0, Serialized) + { + Debug = Concatenate ("TB:DSB0:POFX - Result (!RTBT): ", (!\_SB.PCI0.RP09.RTBT)) + + Return (!\_SB.PCI0.RP09.RTBT) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:DSB0:_PS0" + + If (OSDW ()) + { + PCEU () + + \_SB.PCI0.RP09.TBST () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:DSB0:_PS3" + + If (OSDW ()) + { + PCDA () + + \_SB.PCI0.RP09.TBST () + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (OSDW ()) + { + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package () + { + "PCIHotplugCapable", + Zero + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Return (Zero) + } + + Device (NHI0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String + + /** + * Enable downstream link + */ + Method (PCED, 0, Serialized) + { + Debug = "TB:NHI0:PCED" + Debug = "TB:NHI0:PCED - Request NHI-GPIO to be enabled" + \_SB.PCI0.RP09.GNHI = One + + + // we should not need to force power since + // UPSX init should already have done so! + If (\_SB.PCI0.RP09.UGIO () != Zero) + { + Debug = "TB:NHI0:PCED - GPIOs changed, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + } + + // Do some link training + // Local0 = Zero + // Local1 = Zero + + Local5 = (Timer + 0x00989680) + Debug = Concatenate ("TB:NHI0:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR: ", \_SB.PCI0.RP09.UPSB.DSB0.PRSR) + + If (\_SB.PCI0.RP09.UPSB.DSB0.PRSR != Zero) + { + Debug = "TB:NHI0:PCED - Wait for power up" + Debug = "TB:NHI0:PCED - Wait for downstream bridge to appear" + Local5 = (Timer + 0x00989680) + While (Timer <= Local5) + { + Debug = "TB:NHI0:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == Zero) + { + If (\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) + { + Debug = "TB:NHI0:PCED - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) && (\_SB.PCI0.RP09.UPSB.DSB0.LACT == One)) + { + Debug = "TB:NHI0:PCED - Link training cleared and link is active" Break } Sleep (0x0A) } - SGOV (0x02060000, Zero) - SGDO (0x02060000) + Sleep (0x96) } - Else + + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero + + While (Timer <= Local5) { - Local0 = Zero - - // Debug = "TB:UPSB:NHI0:TRPE GGOV (0x02060000):" - // Debug = GGOV (0x02060000) - - // Debug = "TB:UPSB:NHI0:TRPE GGOV (0x02060000):" - // Debug = GGDV (0x02060000) - - If ((GGOV (0x02060000) == Zero) && (GGDV (0x02060000) == Zero)) - // If (Zero) + Debug = "TB:NHI0:PCED - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND != 0xFFFFFFFF) { - \_SB.PCI0.RP09.PSTX = Zero + Debug = "TB:NHI0:PCED - DSB0 UP - Read VID/DID" + \_SB.PCI0.RP09.UPSB.DSB0.PCIA = One + Break + } - While (One) + Sleep (0x0A) + } + + \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = Zero + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + /** + * Run Time Power Check + * + * Called by NHI driver when link is idle. + * Once both XHC and NHI idle, we can power down. + */ + Method (RTPC, 1, Serialized) + { + Debug = Concatenate ("TB:NHI0:RTPC called with args: ", Arg0) + + If (Arg0 <= One) + { + // Force TB on if usb is on - Test XXX + If (!(Arg0 == Zero && \_SB.PCI0.RP09.RUSB == One)) + { + Debug = Concatenate ("TB:NHI0:RTPC setting RTBT to: ", Arg0) + \_SB.PCI0.RP09.RTBT = Arg0 + } + Else + { + Debug = "TB:NHI0:RTPC leaving RTBT as RUSB is One" + } + } + + Return (Zero) + } + + /** + * Cable detection callback + * Called by NHI driver on hotplug + */ + Method (MUST, 1, Serialized) + { + Debug = "TB:NHI0:MUST - called Cable detection by NHI" + + Return (\_SB.PCI0.RP09.UPSB.MUST (Arg0)) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:NHI0:_PS0" + + If (OSDW ()) + { + PCED () + + \_SB.PCI0.RP09.CTBT () + + \_SB.PCI0.RP09.TBST () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:NHI0:_PS3" + } + + Method (TRPE, 2, Serialized) + { + Debug = Concatenate ("TB:NHI0:TRPE called with Arg0: ", Arg0) + Debug = Concatenate ("TB:NHI0:TRPE called with Arg1: ", Arg1) + + If (Arg0 <= One) + { + If (Arg0 == Zero) + { + \_SB.PCI0.RP09.PSTX = 0x03 + \_SB.PCI0.RP09.LDXX = One + Local0 = (Timer + 0x00989680) + While (Timer <= Local0) { - If (\_SB.PCI0.RP09.LDXX == One) + If (\_SB.PCI0.RP09.LACR == One) { - \_SB.PCI0.RP09.LDXX = Zero - } - - SGDI (0x02060000) - - Local1 = Zero - Local2 = (Timer + 0x00989680) - - While (Timer <= Local2) - { - If (\_SB.PCI0.RP09.LACR == Zero) - { - If (\_SB.PCI0.RP09.LTRN != One) - { - Break - } - } - ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + If (\_SB.PCI0.RP09.LACT == Zero) { Break } - - Sleep (0x0A) } - - Sleep (Arg1) - While (Timer <= Local2) + ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) { - If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) - { - Local1 = One - Break - } - - Sleep (0x0A) - } - - If (Local1 == One) - { - MABT = One Break } - If (Local0 == 0x04) - { - Return (Zero) - } - - Local0++ - SGOV (0x02060000, Zero) - SGDO (0x02060000) - Sleep (0x03E8) + Sleep (0x0A) } - If (\_SB.PCI0.RP09.CSPD != 0x03) + // SGOV (CPGN, Zero) + // SGDO (CPGN) + // \_SB.TBFP (Zero) + } + Else + { + Local0 = Zero + + // If ((GGOV (CPGN) == Zero) && (GGDV (CPGN) == Zero)) + // If (\_GPE.TFPS () == Zero) + If (Zero) { - If (\_SB.PCI0.RP09.SSPD == 0x03) + \_SB.PCI0.RP09.PSTX = Zero + While (One) { - If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) + If (\_SB.PCI0.RP09.LDXX == One) { - If (\_SB.PCI0.RP09.TSPD != 0x03) - { - \_SB.PCI0.RP09.TSPD = 0x03 - } + \_SB.PCI0.RP09.LDXX = Zero + } - If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) + // SGDI (CPGN) + // \_SB.TBFP (One) + Local1 = Zero + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) { - \_SB.PCI0.RP09.UPSB.TSPD = 0x03 - } - - \_SB.PCI0.RP09.LRTN = One - Local2 = (Timer + 0x00989680) - While (Timer <= Local2) - { - If (\_SB.PCI0.RP09.LACR == Zero) + If (\_SB.PCI0.RP09.LTRN != One) { - If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Break + } + + Sleep (0x0A) + } + + Sleep (Arg1) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Local1 = One + Break + } + + Sleep (0x0A) + } + + If (Local1 == One) + { + MABT = One + Break + } + + If (Local0 == 0x04) + { + Return (Zero) + } + + Local0++ + + // SGOV (CPGN, Zero) + // SGDO (CPGN) + // \_SB.TBFP (Zero) + Sleep (0x03E8) + } + + If (\_SB.PCI0.RP09.CSPD != 0x03) + { + If (\_SB.PCI0.RP09.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.TSPD != 0x03) + { + \_SB.PCI0.RP09.TSPD = 0x03 + } + + If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) + { + \_SB.PCI0.RP09.UPSB.TSPD = 0x03 + } + + \_SB.PCI0.RP09.LRTN = One + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + Local1 = One + Break + } + } + ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && + (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) { Local1 = One Break } - } - ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && - (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) - { - Local1 = One - Break - } - Sleep (0x0A) + Sleep (0x0A) + } } } } } } } + + Return (Zero) } - } - Return (Zero) - } - - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - If ((Arg2 == Zero)) - { - Return (Buffer (One) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - 0x03 // . - }) - } + Local0 = Package () + { + // Thinkpad X1 original FW, switched port 5, loading + "ThunderboltDROM", + Buffer () + { + /* 0x00 */ 0x61, // CRC8 checksum: 0x61 + /* 0x01 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x01, // Thunderbolt Bus 0, UID: 0x0109000000000000 + /* 0x09 */ 0x9a, 0x6d, 0x64, 0x0c, // CRC32c checksum: 0x0C646D9A + /* 0x0D */ 0x01, // Device ROM Revision: 1 + /* 0x0E */ 0x62, 0x00, // Length: 98 (starting from previous byte) + /* 0x10 */ 0x09, 0x01, // Vendor ID: 0x109 + /* 0x12 */ 0x06, 0x17, // Device ID: 0x1706 + /* 0x14 */ 0x01, // Device Revision: 0x1 + /* 0x15 */ 0x21, // EEPROM Revision: 33 + /* 0x16 1 */ 0x08, 0x81, 0x80, 0x02, 0x80, 0x00, 0x00, 0x00, + /* 0x1E 2 */ 0x08, 0x82, 0x90, 0x01, 0x80, 0x00, 0x00, 0x00, + /* 0x26 3 */ 0x08, 0x83, 0x80, 0x04, 0x80, 0x01, 0x00, 0x00, + /* 0x2E 4 */ 0x08, 0x84, 0x90, 0x03, 0x80, 0x01, 0x00, 0x00, + /* 0x36 5 */ 0x02, 0x85, + /* 0x38 6 */ 0x0b, 0x86, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0x43 7 */ 0x03, 0x87, 0x80, // PCIe xx:04.0 + /* 0x46 8 */ 0x05, 0x88, 0x50, 0x40, 0x00, + /* 0x4B 9 */ 0x05, 0x89, 0x50, 0x00, 0x00, + /* 0x50 A */ 0x05, 0x8a, 0x50, 0x00, 0x00, + /* 0x55 B */ 0x05, 0x8b, 0x50, 0x40, 0x00, + /* 0x5A 1 */ 0x09, 0x01, 0x4c, 0x65, 0x6e, 0x6f, 0x76, 0x6f, 0x00, // Vendor Name: "Lenovo" + /* 0x63 2 */ 0x0c, 0x02, 0x58, 0x31, 0x20, 0x43, 0x61, 0x72, 0x62, 0x6f, 0x6e, 0x00, // Device Name: "X1 Carbon" + }, - Local0 = Package (0x05) + "TBTDPLowToHigh", + Buffer (One) + { + 0x01, 0x00, 0x00, 0x00 + }, + + "TBTFlags", + Buffer () + { + 0x03, 0x00, 0x00, 0x00 + }, + + "sscOffset", + Buffer () + { + 0x00, 0x07 + }, + + "linkDetails", + Buffer () + { + 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00 + }, + + "power-save", + One, + + Buffer (One) + { + 0x00 + } + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + + /** + * Late sleep force power + * NHI driver sends a sleep cmd to TB controller + * But we might be sleeping at this time. So this will + * force the power on right before sleep. + */ + Method (SXFP, 1, Serialized) { - "ThunderboltDROM", - Buffer (0x6F) - { - /* 0x00 */ 0x61, // CRC8 checksum: 0x61 - /* 0x01 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x01, // Thunderbolt Bus 0, UID: 0x0109000000000000 - /* 0x09 */ 0x2b, 0xcc, 0xb9, 0xf7, // CRC32c checksum: 0xF7B9CC2B - /* 0x0D */ 0x01, // Device ROM Revision: 1 - /* 0x0E */ 0x62, 0x00, // Length: 98 (starting from previous byte) - /* 0x10 */ 0x09, 0x01, // Vendor ID: 0x109 - /* 0x12 */ 0x06, 0x17, // Device ID: 0x1706 - /* 0x14 */ 0x01, // Device Revision: 0x1 - /* 0x15 */ 0x2b, // EEPROM Revision: 43 - /* 0x16 1 */ 0x08, 0x81, 0x80, 0x02, 0x80, 0x00, 0x00, 0x00, - /* 0x1E 2 */ 0x08, 0x82, 0x90, 0x01, 0x80, 0x00, 0x00, 0x00, - /* 0x26 3 */ 0x08, 0x83, 0x80, 0x04, 0x80, 0x01, 0x00, 0x00, - /* 0x2E 4 */ 0x08, 0x84, 0x90, 0x03, 0x80, 0x01, 0x00, 0x00, - /* 0x36 5 */ 0x02, 0x85, - /* 0x38 6 */ 0x0b, 0x86, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 0x43 7 */ 0x03, 0x87, 0x80, // PCIe xx:04.0 - /* 0x46 8 */ 0x05, 0x88, 0x50, 0x40, 0x00, - /* 0x4B 9 */ 0x05, 0x89, 0x50, 0x00, 0x00, - /* 0x50 A */ 0x05, 0x8a, 0x50, 0x00, 0x00, - /* 0x55 B */ 0x05, 0x8b, 0x50, 0x40, 0x00, - /* 0x5A 1 */ 0x09, 0x01, 0x4c, 0x65, 0x6e, 0x6f, 0x76, 0x6f, 0x00, // Vendor Name: "Lenovo" - /* 0x63 2 */ 0x0c, 0x02, 0x58, 0x31, 0x20, 0x43, 0x61, 0x72, 0x62, 0x6f, 0x6e, 0x00, // Device Name: "X1 Carbon" - }, + Debug = "TB:NHI0:SXFP" - "power-save", - One, - Buffer (One) + If (Arg0 == Zero) { - 0x00 // . + // If (GGDV (0x02060001) == One) + // { + // SGOV (0x02060001, Zero) + // SGDO (0x02060001) + // Sleep (0x64) + // } + + // SGOV (CPGN, Zero) + // SGDO (CPGN) + // \_SB.TBFP (Zero) + + Sleep (0x64) } } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - /** - * Late sleep force power - * NHI driver sends a sleep cmd to TB controller - * But we might be sleeping at this time. So this will - * force the power on right before sleep. - */ - Method (SXFP, 1, Serialized) - { - Debug = "TB:UPSB:NHI0:SXFP - Late sleep force power - Arg0:" - Debug = Arg0 - - // Debug = "TB:UPSB:NHI0:SXFP - GGDV (0x02060001)" - // Debug = GGDV (0x02060001) - - If (Arg0 == Zero) - { - If (GGDV (0x02060001) == One) + Name (XRTE, Zero) + Method (XRST, 1, Serialized) { - SGOV (0x02060001, Zero) - SGDO (0x02060001) - Sleep (0x64) - } - - SGOV (0x02060000, Zero) - SGDO (0x02060000) - } - } - - Name (XRTE, Zero) - - Method (XRST, 1, Serialized) - { - Debug = "TB:UPSB:NHI0:XRST - Arg0:" - Debug = Arg0 - - If (Arg0 == Zero) - { - XRTE = Zero - If (XLTP == Zero) - { - // Debug = "TB:UPSB:NHI0:TRPE L23 Detect" - \_SB.PCI0.RP09.L23R = One - - Sleep (One) - - Local2 = Zero - - While (\_SB.PCI0.RP09.L23R) + Debug = "TB:NHI0:XRST - called with arg:" + Debug = Arg0 + If (Arg0 == Zero) { - If (Local2 > 0x04) + XRTE = Zero + If (XLTP == Zero) { - Break - } - - Sleep (One) - Local2++ - } - - // Debug = "TB:UPSB:NHI0:TRPE Clear LEDM" - \_SB.PCI0.RP09.LEDM = Zero - - SGDI (0x02060004) - } - } - ElseIf (Arg0 == One) - { - XRTE = One - If (XLTP == Zero) - { - \_SB.PCI0.RP09.PSTX = 0x03 - If (\_SB.PCI0.RP09.LACR == One) - { - If (\_SB.PCI0.RP09.LACT == Zero) - { - // Debug = "TB:UPSB:NHI0:XRST: Root Port LDIS - Skipping L23 Ready Request" - } - Else - { - // Debug = "TB:UPSB:NHI0:XRST Root Port Requesting L23 Ready" - \_SB.PCI0.RP09.L23E = One - + Debug = "TB:NHI0:XRST - TRPE L23 Detect" + \_SB.PCI0.RP09.L23D = One Sleep (One) - Local2 = Zero - - While (\_SB.PCI0.RP09.L23E == One) + While (\_SB.PCI0.RP09.L23D) { If (Local2 > 0x04) { @@ -2779,174 +2869,58 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Local2++ } - // Debug = "TB:UPSB:NHI0:XRST Root Port Set DMI L1 EN" - \_SB.PCI0.RP09.LEDM = One + Debug = "TB:NHI0:XRST - TRPE Clear LEDM" + \_SB.PCI0.RP09.LEDX = Zero + // SGDI (0x02060004) } } - - SGOV (0x02060004, Zero) - SGDO (0x02060004) - Sleep (0x4B) - } - } - } - } - } - - Device (DSB1) - { - Name (_ADR, 0x00010000) // _ADR: Address - Name (_SUN, One) // _SUN: Slot User Number - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) + ElseIf (Arg0 == One) { - Return (One) - } + XRTE = One + If (XLTP == Zero) + { + \_SB.PCI0.RP09.PSTX = 0x03 + If (\_SB.PCI0.RP09.LACR == One) + { + If (\_SB.PCI0.RP09.LACT == Zero) + { + Debug = "TB:NHI0:XRST: Root Port LDIS - Skipping L23 Ready Request" + } + Else + { + Debug = "TB:NHI0:XRST Root Port Requesting L23 Ready" + \_SB.PCI0.RP09.L23X = One + Sleep (One) + Local2 = Zero + While (\_SB.PCI0.RP09.L23X == One) + { + If (Local2 > 0x04) + { + Break + } - Return (Zero) + Sleep (One) + Local2++ + } + + Debug = "TB:NHI0:XRST Root Port Set DMI L1 EN" + \_SB.PCI0.RP09.LEDX = One + } + } + + // SGOV (0x02060004, Zero) + // SGDO (0x02060004) + Sleep (0x4B) + } + } } } } - Device (DSB3) + Device (DSB1) { - Name (_ADR, 0x00030000) // _ADR: Address + Name (_ADR, 0x00010000) // _ADR: Address + Name (_SUN, One) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { @@ -2961,9 +2935,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -2973,11 +2986,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) - { - Return (One) - } - Return (Zero) } @@ -3022,44 +3030,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3097,247 +3068,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) } } - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address @@ -3357,7 +3087,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3375,12 +3105,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -3392,6 +3123,236 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -3414,7 +3375,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB4.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3432,12 +3393,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -3449,6 +3411,246 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -3471,7 +3673,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB5.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3509,7 +3711,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB6.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB1.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3530,9 +3732,9 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) } } - Device (DSB5) + Device (DSB2) { - Name (_ADR, 0x00050000) // _ADR: Address + Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { @@ -3547,9 +3749,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB5.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB2.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -3559,423 +3800,141 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) - { - Return (One) - } - Return (Zero) } - } - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + /** + * Enable upstream link + */ + Method (PCEU, 0, Serialized) { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } + Debug = "TB:DSB2:PCEU" - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB6.SECB */ - } + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = Zero + Debug = "TB:DSB2:PCEU - Put upstream bridge back into D0 " - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) + If (\_SB.PCI0.RP09.UPSB.DSB2.PSTA != Zero) { - Return (One) + Debug = "TB:DSB2:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB2.PSTA = Zero } - Return (Zero) - } - } - } - } - - Device (DSB2) - { - Name (_ADR, 0x00020000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB2.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Name (IIP3, Zero) - Name (PRSR, Zero) - Name (PCIA, One) - - /** - * Enable upstream link - */ - Method (PCEU, 0, Serialized) - { - Debug = "TB:UPSB:DSB2:PCEU - Enable upstream link" - - \_SB.PCI0.RP09.UPSB.DSB2.PRSR = Zero - - // Debug = "TB:UPSB:DSB2:PCEU - Put upstream bridge back into D0 " - If (\_SB.PCI0.RP09.UPSB.DSB2.PSTA != Zero) - { - // Debug = "TB:UPSB:DSB2:PCEU - exit D0, restored = true" - \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One - \_SB.PCI0.RP09.UPSB.DSB2.PSTA = Zero - } - - If (\_SB.PCI0.RP09.UPSB.DSB2.LDIS == One) - { - // Debug = "TB:UPSB:DSB2:PCEU - Clear link disable on upstream bridge" - // Debug = "TB:UPSB:DSB2:PCEU - clear link disable, restored = true" - \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One - \_SB.PCI0.RP09.UPSB.DSB2.LDIS = Zero - } - } - - /** - * PCI disable link - */ - Method (PCDA, 0, Serialized) - { - Debug = "TB:UPSB:DSB2:PCDA - PCI disable link" - - If (\_SB.PCI0.RP09.UPSB.DSB2.POFX () != Zero) - { - \_SB.PCI0.RP09.UPSB.DSB2.PCIA = Zero - - // Debug = "TB:UPSB:DSB2:PCDA - Put upstream bridge into D3" - \_SB.PCI0.RP09.UPSB.DSB2.PSTA = 0x03 - - // Debug = "TB:UPSB:DSB2:PCDA - Set link disable on upstream bridge" - \_SB.PCI0.RP09.UPSB.DSB2.LDIS = One - - Local5 = (Timer + 0x00989680) - - While (Timer <= Local5) - { - // Debug = "TB:UPSB:DSB2:PCDA - Wait for link to drop..." - If (\_SB.PCI0.RP09.UPSB.DSB2.LACR == One) + If (\_SB.PCI0.RP09.UPSB.DSB2.LDIS == One) { - If (\_SB.PCI0.RP09.UPSB.DSB2.LACT == Zero) + Debug = "TB:DSB2:PCEU - Clear link disable on upstream bridge" + Debug = "TB:DSB2:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB2.LDIS = Zero + } + } + + /** + * PCI disable link + */ + Method (PCDA, 0, Serialized) + { + Debug = "TB:DSB2:PCDA" + + If (\_SB.PCI0.RP09.UPSB.DSB2.POFX () != Zero) + { + \_SB.PCI0.RP09.UPSB.DSB2.PCIA = Zero + + Debug = "TB:DSB2:PCDA - Put upstream bridge into D3" + \_SB.PCI0.RP09.UPSB.DSB2.PSTA = 0x03 + + Debug = "TB:DSB2:PCDA - Set link disable on upstream bridge" + \_SB.PCI0.RP09.UPSB.DSB2.LDIS = One + + Local5 = (Timer + 0x00989680) + While (Timer <= Local5) { - // Debug = "TB:UPSB:DSB2:PCDA - No link activity" - Break + Debug = "TB:DSB2:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.UPSB.DSB2.LACR == One) + { + If (\_SB.PCI0.RP09.UPSB.DSB2.LACT == Zero) + { + Debug = "TB:DSB2:PCDA - No link activity" + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND == 0xFFFFFFFF) + { + Debug = "TB:DSB2:PCDA - VID/DID is -1" + Break + } + + Sleep (0x0A) } + + Debug = "TB:DSB2:PCDA - Request USB-GPIO to be disabled" + \_SB.PCI0.RP09.GXCI = Zero + \_SB.PCI0.RP09.UGIO () } Else { - If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND)) - { - If (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND == 0xFFFFFFFF) - { - Debug = "TB:UPSB:DSB2:PCDA - VID/DID is -1" - Break - } - } - Else - { - Debug = "TB:UPSB:DSB2:PCDA - XHC2 disabled? BUG?" - } + Debug = "TB:DSB2:PCDA - Not disabling" } - Sleep (0x0A) + \_SB.PCI0.RP09.UPSB.DSB2.IIP3 = One } - // Debug = "PCDA - disable GPIO" - \_SB.PCI0.RP09.GXCI = Zero - \_SB.PCI0.RP09.UGIO () // power down if needed - } - Else - { - // Debug = "PCDA - Not disabling" - } - - \_SB.PCI0.RP09.UPSB.DSB2.IIP3 = One - } - - /** - * Is power saving requested? - */ - Method (POFX, 0, Serialized) - { - If (!\_SB.PCI0.RP09.RUSB) - { - Debug = "TB:UPSB:DSB2:POFX - USB is idle (RUSB = Zero)" - } - Else - { - Debug = "TB:UPSB:DSB2:POFX - USB is active (RUSB != Zero)" - } - - - Return (!\_SB.PCI0.RP09.RUSB) - } - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 - { - Debug = "TB:UPSB:DSB2:_PS0" - - If (OSDW ()) - { - PCEU () - } - } - - Method (_PS3, 0, Serialized) // _PS3: Power State 3 - { - Debug = "TB:UPSB:DSB2:_PS3" - - If (OSDW ()) - { - PCDA () - } - } - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - If (OSDW ()) - { - If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + /** + * Is power saving requested? + */ + Method (POFX, 0, Serialized) { - Local0 = Package (0x02) - { - "PCIHotplugCapable", - Zero - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) + Debug = Concatenate ("TB:DSB2:POFX - Result (!RUSB): ", (!\_SB.PCI0.RP09.RUSB)) + + Return (!\_SB.PCI0.RP09.RUSB) } - } - Return (Zero) - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) + Method (_PS0, 0, Serialized) // _PS0: Power State 0 { - Return (One) + Debug = "TB:DSB2:_PS0" + + If (OSDW ()) + { + PCEU () + + \_SB.PCI0.RP09.TBST () + } } - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) + Method (_PS3, 0, Serialized) // _PS3: Power State 3 { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 + Debug = "TB:DSB2:_PS3" + + If (OSDW ()) + { + PCDA () + + \_SB.PCI0.RP09.TBST () + } } - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { - Return (One) + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package () + { + "PCIHotplugCapable", + Zero + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } Return (Zero) } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } } Device (DSB3) @@ -3995,9 +3954,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4007,11 +4005,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) - { - Return (One) - } - Return (Zero) } @@ -4056,7 +4049,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB0.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4064,6 +4057,16 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (0x0F) } + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + Device (DEV0) { Name (_ADR, Zero) // _ADR: Address @@ -4071,6 +4074,16 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) { Return (0x0F) } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } } } @@ -4093,7 +4106,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4111,12 +4124,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -4128,6 +4142,236 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -4150,7 +4394,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB4.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4168,12 +4412,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -4185,6 +4430,246 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -4207,7 +4692,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB5.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4245,7 +4730,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB6.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB3.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4269,6 +4754,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address + Name (_SUN, 0x02) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { @@ -4283,9 +4769,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4295,11 +4820,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) - { - Return (One) - } - Return (Zero) } @@ -4344,7 +4864,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB0.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4352,6 +4872,16 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (0x0F) } + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + Device (DEV0) { Name (_ADR, Zero) // _ADR: Address @@ -4391,7 +4921,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB3.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4409,12 +4939,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -4426,6 +4957,236 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -4448,7 +5209,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB4.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4466,12 +5227,13 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } - Device (DEV0) + Device (UPS0) { Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (0x0F) + AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status @@ -4483,6 +5245,246 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Return (Zero) } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -4505,7 +5507,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB5.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4543,7 +5545,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB6.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB4.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4581,9 +5583,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB5.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4593,12 +5634,749 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) { - Return (One) + AVND, 16 } - Return (Zero) + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB5.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } } } @@ -4619,9 +6397,48 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) MABT, 1 } + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB6.SECB */ + Return (SECB) /* \_SB.PCI0.RP09.UPSB.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status @@ -4631,1736 +6448,31 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { - If (OSDW ()) - { - Return (One) - } - Return (Zero) } } - } - } - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - Name (_SUN, 0x02) // _SUN: Slot User Number - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { - Return (One) + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package (0x02) + { + "PCI-Thunderbolt", + One + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } Return (Zero) } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } } } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (UPS0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (ARE0, PCI_Config, Zero, 0x04) - Field (ARE0, ByteAcc, NoLock, Preserve) - { - AVND, 16 - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DSB0) - { - Name (_ADR, Zero) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1, - Offset (0x3E), - , 6, - SBRS, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB0.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB3) - { - Name (_ADR, 0x00030000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB3.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB4) - { - Name (_ADR, 0x00040000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB4.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - - Device (DEV0) - { - Name (_ADR, Zero) // _ADR: Address - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB5) - { - Name (_ADR, 0x00050000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB5.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - If (OSDW ()) - { - Return (One) - } - - Return (Zero) - } - } - } - } - - Device (DSB6) - { - Name (_ADR, 0x00060000) // _ADR: Address - OperationRegion (A1E0, PCI_Config, Zero, 0x40) - Field (A1E0, ByteAcc, NoLock, Preserve) - { - AVND, 32, - BMIE, 3, - Offset (0x18), - PRIB, 8, - SECB, 8, - SUBB, 8, - Offset (0x1E), - , 13, - MABT, 1 - } - - OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) - Field (A1E1, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - Offset (0x08), - Offset (0x0A), - , 5, - TPEN, 1, - Offset (0x0C), - SSPD, 4, - , 16, - LACR, 1, - Offset (0x10), - , 4, - LDIS, 1, - LRTN, 1, - Offset (0x12), - CSPD, 4, - CWDT, 6, - , 1, - LTRN, 1, - , 1, - LACT, 1, - Offset (0x14), - Offset (0x30), - TSPD, 4 - } - - OperationRegion (A1E2, PCI_Config, 0x80, 0x08) - Field (A1E2, ByteAcc, NoLock, Preserve) - { - Offset (0x01), - Offset (0x02), - Offset (0x04), - PSTA, 2 - } - - Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number - { - Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB6.SECB */ - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (0x0F) - } - - Method (_RMV, 0, NotSerialized) // _RMV: Removal Status - { - Return (Zero) - } - } - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - If (OSDW ()) - { - If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) - { - Local0 = Package (0x02) - { - "PCI-Thunderbolt", - One - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Return (Zero) - } } } } + diff --git a/patches/SSDT-USBX.dsl b/patches/SSDT-USBX.dsl deleted file mode 100644 index 0c67364..0000000 --- a/patches/SSDT-USBX.dsl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Fix USB Power - * https://dortania.github.io/OpenCore-Post-Install/usb/misc/power.html - */ - -DefinitionBlock ("", "SSDT", 2, "tyler", "_USBX", 0x00001000) -{ - External (DTGP, MethodObj) // 4 Arguments - External (OSDW, MethodObj) // 0 Arguments - - Scope (\_SB) - { - Device (\_SB.USBX) - { - Name (_ADR, Zero) // _ADR: Address - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package () - { - // Values from genuine macbook14,1 with same USB-controller - "kUSBSleepPortCurrentLimit", 2100, - "kUSBWakePortCurrentLimit", 2100, - "kUSBSleepPowerSupply", 9600, - "kUSBWakePowerSupply", 9600, - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - - Method (_STA, 0, NotSerialized) // _STA: Status - { - If (OSDW ()) - { - Return (0x0F) - } - - Return (Zero) - } - } - } -} diff --git a/patches/SSDT-XHC1.dsl b/patches/SSDT-XHC1.dsl index 266748d..cc1729b 100644 --- a/patches/SSDT-XHC1.dsl +++ b/patches/SSDT-XHC1.dsl @@ -1,57 +1,87 @@ -/* - * USB 2.0/ 3.0 - * Reference: https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf - * - * Depends on /patches/OpenCore Patches/ XHC1.plist - */ +// Depends on /patches/OpenCore Patches/ XHC1.plist +// +// +// Native ACPI-setup for the USB2/3-controller on x80-series Thinkpads +// +// This enables all ports to be as native as possible on OSX and only disables those devices which +// have definetly no drivers on OSX. It should be compatible with almost all thinkpad-configs. +// +// The opinion that things like cardreader, which might not be used, are adding to a significant +// power-draw is false - if one has a working USB-setup. Even if it does not hurt. +// +// This SSDT is developed with compatibility in mind and therefor all devices are enabled by default. +// +// I'm driving both of my thinkpads with ~0.7W pkg-power draw on idle with all devices enabled. +// +// Reference: https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf +// +// Credits @benbender DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) { - External (_SB_.PCI0, DeviceObj) - External (_SB_.PCI0.XHC, DeviceObj) - External (_SB_.PCI0.XHC._PS0, MethodObj) - External (_SB_.PCI0.XHC._PS3, MethodObj) - External (_SB_.PCI0.XHC._DSM, MethodObj) - External (_SB_.PCI0.XHC.RHUB._PS0, MethodObj) - External (_SB_.PCI0.XHC.RHUB._PS2, MethodObj) - External (_SB_.PCI0.XHC.RHUB._PS3, MethodObj) - External (_SB_.PCI0.XHC.XFLT, FieldUnitObj) - External (_SB_.PCI0.RP09.UPSB.DSB2.XHC2, DeviceObj) - External (_SB_.PCI0.RP09.UPSB.DSB2.XHC2.MODU, MethodObj) // 0 Arguments + // External method from SSDT-UTILS.dsl + External (OSDW, MethodObj) // 0 Arguments + External (DTGP, MethodObj) // 5 Arguments - External (U2OP, IntObj) + External (_SB.PCI0.XHC_, DeviceObj) + External (_SB.PCI0.XHC_.RHUB, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS01, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS02, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS03, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS04, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS05, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS06, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS07, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS08, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS09, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.HS10, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS01, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS02, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS03, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS04, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS05, DeviceObj) + External (_SB.PCI0.XHC_.RHUB.SS06, DeviceObj) - External (DTGP, MethodObj) // 5 Arguments - External (OSDW, MethodObj) // 0 Arguments + External (_SB.PCI0.XHC_.PDBM, FieldUnitObj) + External (_SB.PCI0.XHC_.MEMB, FieldUnitObj) - Scope (\_SB.PCI0.XHC) + External (_SB.PCI0.XHC_.XPS0, MethodObj) + External (_SB.PCI0.XHC_.XPS3, MethodObj) + + External (_SB.PCI0.RP09.UPSB.DSB2.XHC2, DeviceObj) + External (_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU, MethodObj) // 0 Arguments + External (_SB.PCI0.RP09.UPN1, IntObj) + External (_SB.PCI0.RP09.UPN2, IntObj) + + External (TBAS, IntObj) + + External (XLTP, FieldUnitObj) + External (MPMC, FieldUnitObj) + External (PMFS, FieldUnitObj) + External (UWAB, FieldUnitObj) + + + Scope (\_SB) { - Method (_STA, 0, NotSerialized) // _STA: Status + Device (USBX) { - If (OSDW ()) + Name (_ADR, Zero) // _ADR: Address + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - Return (Zero) - } - - Return (0x0F) - } - } - - Scope (\_SB.PCI0) - { - Device (XHC1) - { - Name (_ADR, 0x00140000) // _ADR: Address - Name (SDPC, Zero) - Name (_GPE, 0x6D) // _GPE: General Purpose Events - - Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake - { - Return (Package (0x02) - { - 0x6D, - 0x03 - }) + Local0 = Package () + { + "kUSBSleepPortCurrentLimit", + 3000, + "kUSBWakePortCurrentLimit", + 3000, + // "kUSBSleepPowerSupply", + // 9600, + // "kUSBWakePowerSupply", + // 9600, + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) } Method (_STA, 0, NotSerialized) // _STA: Status @@ -63,172 +93,572 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Return (Zero) } + } + + Scope (PCI0.XHC_) + { + Name (SDPC, Zero) + Name (_GPE, 0x6D) // _GPE: General Purpose Events - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + Name (SBAR, Zero) + OperationRegion (XPRX, PCI_Config, Zero, 0x0100) + Field (XPRX, AnyAcc, NoLock, Preserve) { - DEBUG = "XHC1:_DSM" - - \_SB_.PCI0.XHC._DSM (Arg0, Arg1, Arg2, Arg3) - - Local0 = Package (0x04) - { - "acpi-wake-type", - One, - "built-in", - Zero - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 - { - Debug = "XHC1:_PS0" - - \_SB_.PCI0.XHC._PS0 () - } - - Method (_PS3, 0, Serialized) // _PS3: Power State 3 - { - Debug = "XHC1:_PS3" - - \_SB_.PCI0.XHC._PS3 () - } - - Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State - { - Debug = "XHC1:_S3D" - - Return (0x03) - } - - Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State - { - Debug = "XHC1:_S4D" - - Return (0x03) - } - - Method (_S3W, 0, NotSerialized) // _S3W: S3 Device Wake State - { - Debug = "XHC1:_S3W" - - Return (0x03) - } - - Method (_S4W, 0, NotSerialized) // _S4W: S4 Device Wake State - { - Debug = "XHC1:_S4W" - - Return (0x03) - } - - Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State - { - Debug = "XHC1:_S0W" - - If ((\_SB_.PCI0.XHC.XFLT == Zero)) - { - Return (0x00) - } - Else - { - Return (0x03) - } - } - - Method (USRA, 0, Serialized) - { - Debug = "XHC1:USRA" - - Return (0x0F) - } - - Method (SSPA, 0, Serialized) - { - Debug = "XHC1:SSPA" - - Return (0x0D) - } - - Method (CUID, 1, Serialized) - { - Debug = "XHC1:CUID" - - If ((Arg0 == ToUUID ("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) - { - Return (0x01) - } - - Return (0x00) + DVIX, 16, + Offset (0x40), + , 11, + SWAI, 1, + Offset (0x44), + , 12, + SAIP, 2, + Offset (0x48), + Offset (0x50), + , 2, + STGX, 1, + Offset (0x74), + D03X, 2, + Offset (0x75), + PXEE, 1, + , 6, + PXES, 1, + Offset (0xA2), + , 2, + D3HX, 1, + Offset (0xA8), + , 13, + MW13, 1, + MW14, 1, + Offset (0xAC), + Offset (0xB0), + , 13, + MB13, 1, + MB14, 1, + Offset (0xB4), + Offset (0xD0), + PR2, 32, + PR2M, 32, + PR3, 32, + PR3M, 32 } Method (RTPC, 1, Serialized) { - Debug = "XHC1:RTPC" + Debug = Concatenate ("XHC:RTPC called with args: ", Arg0) Return (Zero) } + /** + * Return: + * kUSBTypeCCableTypeNone = 0, + * kUSBTypeCCableTypeUSB = 1, + */ Method (MODU, 0, Serialized) { - Debug = "XHC1:MODU" + // If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU, Local0)) + // { + // Local0 = \_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU () + // } + + // Local1 = Zero + + // If ((Local0 == One) || (Local1 == One)) + // { + // Local0 = One + // } + // ElseIf ((Local0 == 0xFF) || (Local1 == 0xFF)) + // { + // Local0 = 0xFF + // } + // Else + // { + // Local0 = Zero + // } + + // Debug = Concatenate ("XHC:MODU - Result: ", Local0) + + // Return (Local0) Local0 = One - // TB-Controler enabled? If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU)) { - // If enabled, check if any device is plugged in - Local0 = \_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU () + Local0 = (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU ()) } - Local1 = Zero - - If ((Local0 == One) || (Local1 == One)) - { - Local0 = One - } - ElseIf ((Local0 == 0xFF) || (Local1 == 0xFF)) - { - Local0 = 0xFF - } - Else - { - Local0 = Zero - } + Debug = Concatenate ("XHC:MODU - Result: ", Local0) Return (Local0) } - Device (RHUB) + Method (USBM, 0, Serialized) { - Name (_ADR, Zero) // _ADR: Address - - Method (_PS0, 0, Serialized) // _PS0: Power State 0 + ^D03X = Zero + Local1 = ^PDBM /* \_SB_.PCI0.XHC1.PDBM */ + Local2 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + ^PDBM = (Local1 | 0x02) + Local0 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local0 &= 0xFFFFFFFFFFFFFFF0 + OperationRegion (PSCA, SystemMemory, Local0, 0x0600) + Field (PSCA, DWordAcc, NoLock, Preserve) { - Debug = "XHC1:RHUB:_PS0" - - \_SB_.PCI0.XHC.RHUB._PS0 () + Offset (0x480), + PC01, 32, + Offset (0x490), + PC02, 32, + Offset (0x4A0), + PC03, 32, + Offset (0x4B0), + PC04, 32 } - Method (_PS2, 0, Serialized) // _PS0: Power State 2 - { - Debug = "XHC1:RHUB:_PS2" + Local6 = PC03 /* \_SB_.PCI0.XHC1.USBM.PC03 */ + Local6 = (PC03 & 0xFFFFFFFFFFFFFFFD) + PC03 = (Local6 & 0xFFFFFFFFFFFFFDFF) + Sleep (0x32) + Local6 = PC03 /* \_SB_.PCI0.XHC1.USBM.PC03 */ + ^PDBM &= 0xFFFFFFFFFFFFFFF9 + ^D03X = 0x03 + ^MEMB = Local2 + ^PDBM = Local1 + Return (Zero) + } - \_SB_.PCI0.XHC.RHUB._PS2 () + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + If (OSDW ()) + { + Local2 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local1 = ^PDBM /* \_SB_.PCI0.XHC1.PDBM */ + ^PDBM &= 0xFFFFFFFFFFFFFFF9 + ^D03X = Zero + + If (SBAR == Zero) + { + Local7 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local7 &= 0xFFFFFFFFFFFFFFF0 + + If ((Local7 == Zero) || (Local7 == 0xFFFFFFFFFFFFFFF0)) + { + ^MEMB = 0xFEAF0000 + } + } + Else + { + ^MEMB = SBAR /* \_SB_.PCI0.XHC1.SBAR */ + } + + ^PDBM = (Local1 | 0x02) + Local0 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local0 &= 0xFFFFFFFFFFFFFFF0 + + OperationRegion (MCA1, SystemMemory, Local0, 0x9000) + Field (MCA1, DWordAcc, NoLock, Preserve) + { + Offset (0x80A4), + , 28, + AX28, 1, + Offset (0x80C0), + , 10, + S0IX, 1, + Offset (0x81C4), + , 2, + CLK0, 1, + , 3, + CLK1, 1 + } + + S0IX = Zero + + AX28 = One + Stall (0x33) + AX28 = Zero + CLK0 = Zero + CLK1 = Zero + ^PDBM &= 0xFFFFFFFFFFFFFFFD + ^MEMB = Local2 + ^PDBM = Local1 + + If (UWAB && (D03X == Zero)) + { + MPMC = One + Local0 = (Timer + 0x00989680) + While (Timer <= Local0) + { + If (PMFS == Zero) + { + Break + } + + Sleep (0x0A) + } + } + } + Else + { + // NON-OSX + \_SB.PCI0.XHC_.XPS0 () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + If (OSDW ()) + { + Local1 = ^PDBM /* \_SB_.PCI0.XHC1.PDBM */ + Local2 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + ^PDBM &= 0xFFFFFFFFFFFFFFF9 + + If (XLTP == Zero) + { + ^D03X = 0x03 + Stall (0x1E) + } + + ^D03X = Zero + ^PDBM = (Local1 | 0x02) + SBAR = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + If (SBAR == Zero) + { + Local7 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local7 &= 0xFFFFFFFFFFFFFFF0 + + If ((Local7 == Zero) || (Local7 == 0xFFFFFFFFFFFFFFF0)) + { + ^MEMB = 0xFEAF0000 + } + } + + Local0 = ^MEMB /* \_SB_.PCI0.XHC1.MEMB */ + Local0 &= 0xFFFFFFFFFFFFFFF0 + + OperationRegion (MCA1, SystemMemory, Local0, 0x9000) + Field (MCA1, DWordAcc, NoLock, Preserve) + { + Offset (0x80A4), + , 28, + AX28, 1, + Offset (0x80C0), + , 10, + S0IX, 1, + Offset (0x81C4), + , 2, + CLK0, 1, + , 3, + CLK1, 1 + } + + If (XLTP == Zero) + { + S0IX = One + Stall (0x14) + } + + CLK0 = Zero + CLK1 = One + ^PDBM = Local1 + ^D03X = 0x03 + ^MEMB = Local2 + ^PDBM = Local1 + + If (UWAB && (D03X == 0x03)) + { + MPMC = 0x03 + Local0 = (Timer + 0x00989680) + While (Timer <= Local0) + { + If (PMFS == Zero) + { + Break + } + + Sleep (0x0A) + } + } + } + Else + { + // NON-OSX + \_SB.PCI0.XHC_.XPS3 () + } + } + + Scope (RHUB) + { + Scope (HS01) // Right USB-A-Port, 480 Mbit/s + { + Name (_UPC, Package () // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } - Method (_PS3, 0, Serialized) // _PS3: Power State 3 + Scope (HS02) // Left USB-A-Port, 480 Mbit/s { - Debug = "XHC1:RHUB:_PS3" + Name (_UPC, Package () // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) - \_SB_.PCI0.XHC.RHUB._PS3 () + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } } - Device (HS01) + Scope (HS03) // Upper USB-C-Port, weired config, needs investigation + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2)) + { + Debug = "XHC:U2OP - companion ports enabled" + } + + Local0 = Package (0x04) { + 0xFF, + 0x09, + Zero, + Zero + } + + Return (Local0) + } + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2)) + { + Name (SSP, Package (0x02) + { + "XHC2", + 0x03 + }) + Name (SS, Package (0x02) + { + "XHC2", + 0x03 + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + + If (CondRefOf (\_SB.PCI0.RP09.UPN2)) + { + Local0 = Package (0x02) { + "UsbCPortNumber", + \_SB.PCI0.RP09.UPN1 + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + } + + Scope (HS04) // Lower USB-C-Port, weired config, needs investigation + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Local0 = Package (0x04) { + 0xFF, + 0x09, + Zero, + Zero + } + + Return (Local0) + } + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2)) + { + Name (SSP, Package (0x02) + { + "XHC2", + 0x04 + }) + Name (SS, Package (0x02) + { + "XHC2", + 0x04 + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + + If (CondRefOf (\_SB.PCI0.RP09.UPN2)) + { + Local0 = Package (0x02) { + "UsbCPortNumber", + \_SB.PCI0.RP09.UPN2 + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + } + + Scope (HS05) // internal, ir-webcam, deactivated + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (Zero) // disabled on OSX + } + + Return (0xF) // enabled on others + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (HS06) // internal, unused + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (HS07) // Bluetooth, internal + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (HS08) // Webcam, internal + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (HS09) // Fingerprint reader, internal, deactivated + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (Zero) // disabled on OSX + } + + Return (0xF) // enabled on others + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (HS10) // Touchscreen, internal + { + Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + { + Return (Package (0x04) { + 0xFF, + 0xFF, + Zero, + Zero + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (SS01) // Right USB-A-Port, 5 Gbit/s { - Name (_ADR, 0x01) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -236,37 +666,73 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (SS02) // Left USB-A-Port, 5 Gbit/s + { + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x01) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Scope (SS03) // Cardreader, internal + { + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (0x00) + } + + Name (BERT, 0x0C) + Name (IGNR, 0x00) + Method (SBHV, 1, Serialized) + { + If (Arg0) + { + Store (0x01, IGNR) + } + Else + { + Store (0x00, IGNR) + } + } + + Method (GBHV, 0, Serialized) + { + Return (IGNR) + } + + Name (U3SD, 0x0FBE) + Name (S104, 0x00) + Name (S050, 0x00) + Name (S025, 0x00) + Name (_GPE, 0x3B) // _GPE: General Purpose Events + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Local0 = Package (0x02) {} @@ -275,201 +741,8 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) } } - Device (HS02) + Scope (SS04) // Unused, internal { - Name (_ADR, 0x02) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0x03, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS03) - { - Name (_ADR, 0x03) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0x08, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) - - If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) - { - Name (SSP, Package (0x02) - { - "XHC2", - 0x03 - }) - Name (SS, Package (0x02) - { - "XHC2", - 0x03 - }) - } - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - - If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) - { - Local0 = Package (0x02) - { - "NoNumber", - Zero - } - } - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS04) - { - Name (_ADR, 0x04) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0x08, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) - - If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) - { - Name (SSP, Package (0x02) - { - "XHC2", - 0x04 - }) - Name (SS, Package (0x02) - { - "XHC2", - 0x04 - }) - } - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - - If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) - { - Local0 = Package (0x02) - { - "NoNumber", - Zero - } - } - - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS05) - { - Name (_ADR, 0x05) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -477,47 +750,17 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - Local0 = Package (0x00) {} + Local0 = Package (0x01) {} DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } - Device (HS06) + Scope (SS05) // Unused, internal { - Name (_ADR, 0x06) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -525,47 +768,17 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - Local0 = Package (0x00) {} + Local0 = Package (0x01) {} DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } - Device (HS07) + Scope (SS06) // Unused, internal { - Name (_ADR, 0x07) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -573,375 +786,10 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS08) - { - Name (_ADR, 0x08) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0xFF, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS09) - { - Name (_ADR, 0x09) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0xFF, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (HS10) - { - Name (_ADR, 0x0A) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0xFF, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (SS01) - { - Name (_ADR, 0x0D) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0x03, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (SS02) - { - Name (_ADR, 0x0E) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0x03, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - }) - - - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (SS03) - { - Name (_ADR, 0x0F) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - 0xFF, - 0xFF, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } - - Device (SS04) - { - Name (_ADR, 0x10) // _ADR: Address - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities - { - Zero, - Zero, - Zero, - Zero - }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device - { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x0, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0) - - }) - Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method - { - Local0 = Package (0x00) {} + Local0 = Package (0x01) {} DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } @@ -950,10 +798,20 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) Method (MBSD, 0, NotSerialized) { - DEBUG = "XHC1:MBSD" - Return (One) } + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2)) + { + Name (SSP, Package (0x01) + { + "XHC2" + }) + Name (SS, Package (0x01) + { + "XHC2" + }) + } } } -} +} \ No newline at end of file diff --git a/patches/SSDT-XHC2.dsl b/patches/SSDT-XHC2.dsl index 282d811..f2d0330 100644 --- a/patches/SSDT-XHC2.dsl +++ b/patches/SSDT-XHC2.dsl @@ -1,6 +1,15 @@ -/* - * USB 3.1 - */ +// +// USB-C 3.1 Gen2-controller +// +// The controller is part of the alpine ridge Thunderbolt-controller. +// +// At the moment there is no known way to have - or at least I haven't found it yet - +// to have native Thunderbolt incl. power-management and USB-C 3.1 Gen2-hotplug at the +// same time. For the moment I opted for thunderbolt and the runtime power saving. +// +// So sadly, this is broken on runtime for the moment :( +// +// Credits @benbender DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) { @@ -9,8 +18,11 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) External (OSDW, MethodObj) // OS Is Darwin? External (_SB.PCI0.RP09.RUSB, IntObj) - External (_SB.PCI0.RP09.GXCI, FieldUnitObj) + External (_SB.PCI0.RP09.RTBT, IntObj) + External (_SB.PCI0.RP09.GXCI, IntObj) + External (_SB.PCI0.RP09.GNHI, IntObj) External (_SB.PCI0.RP09.UGIO, MethodObj) + External (_SB.PCI0.RP09.TBST, MethodObj) External (_SB.PCI0.RP09.UPSB.DSB2, DeviceObj) External (_SB.PCI0.RP09.UPSB.PCED, MethodObj) External (_SB.PCI0.RP09.UPSB.MDUV, IntObj) @@ -21,14 +33,12 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) External (_SB.PCI0.RP09.UPSB.DSB2.LACT, FieldUnitObj) External (_SB.PCI0.RP09.UPSB.DSB2.LTRN, FieldUnitObj) - External (_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD, MethodObj) - External (_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC, MethodObj) + External (_SB.PCI0.RP09.UPN1, IntObj) + External (_SB.PCI0.RP09.UPN2, IntObj) External (TBSE, IntObj) External (TBTS, IntObj) External (TBAS, IntObj) - External (UPT1, IntObj) - External (UPT2, IntObj) External (USME, IntObj) Name (U2OP, One) // Companion controller present? @@ -55,73 +65,68 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) } /** - * PCI Enable downstream - */ + * PCI Enable downstream + */ Method (PCED, 0, Serialized) { - Debug = "TB:UPSB:DSB2:XHC2:PCED - PCI Enable downstream" - // Debug = "TB:UPSB:DSB2:XHC2:PCED - enable GPIO" - + Debug = "TB:DSB2:XHC2:PCED" + Debug = "TB:DSB2:XHC2:PCED - Request USB-GPIO to be enabled & force TBT-GPIO" \_SB.PCI0.RP09.GXCI = One + \_SB.PCI0.RP09.GNHI = One // this powers up both TBT and USB when needed If (\_SB.PCI0.RP09.UGIO () != Zero) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - GPIOs changed, restored = true" + Debug = "TB:DSB2:XHC2:PCED - GPIOs changed, restored = true" \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One } - // Do some link training - Local0 = Zero - Local1 = Zero - Local5 = (Timer + 10000000) + // Local0 = Zero + // Local1 = Zero + Local5 = (Timer + 0x00989680) - // Debug = "TB:UPSB:DSB2:XHC2:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" - // Debug = \_SB.PCI0.RP09.UPSB.DSB2.PRSR + Debug = Concatenate ("TB:DSB2:XHC2:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR: ", \_SB.PCI0.RP09.UPSB.DSB2.PRSR) If (\_SB.PCI0.RP09.UPSB.DSB2.PRSR != Zero) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for power up" - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for downstream bridge to appear" - - Local5 = (Timer + 10000000) - + Debug = "TB:DSB2:XHC2:PCED - Wait for power up" + Debug = "TB:DSB2:XHC2:PCED - Wait for downstream bridge to appear" + Local5 = (Timer + 0x00989680) While (Timer <= Local5) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for link training..." + Debug = "TB:DSB2:XHC2:PCED - Wait for link training..." If (\_SB.PCI0.RP09.UPSB.DSB2.LACR == Zero) { If (\_SB.PCI0.RP09.UPSB.DSB2.LTRN != One) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Link training cleared" + Debug = "TB:DSB2:XHC2:PCED - Link training cleared" Break } } ElseIf ((\_SB.PCI0.RP09.UPSB.DSB2.LTRN != One) && (\_SB.PCI0.RP09.UPSB.DSB2.LACT == One)) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Link training cleared and link is active" + Debug = "TB:DSB2:XHC2:PCED - Link training cleared and link is active" Break } - Sleep (10) + Sleep (0x0A) } - Sleep (150) + Sleep (0x96) } \_SB.PCI0.RP09.UPSB.DSB2.PRSR = Zero - While (Timer <= Local5) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for config space..." + Debug = "TB:DSB2:XHC2:PCED - Wait for config space..." If (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND != 0xFFFFFFFF) { - // Debug = "TB:UPSB:DSB2:XHC2:PCED - Read VID/DID" + Debug = "TB:DSB2:XHC2:PCED - DSB2 Up - Read VID/DID" \_SB.PCI0.RP09.UPSB.DSB2.PCIA = One Break } - Sleep (10) + Sleep (0x0A) } \_SB.PCI0.RP09.UPSB.DSB2.IIP3 = Zero @@ -129,28 +134,15 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - If (U2OP == One) - { - Local0 = Package (0x06) - { - "USBBusNumber", - Zero, - "AAPL,xhci-clock-id", - One, - "UsbCompanionControllerPresent", - One - } - } - Else - { - Local0 = Package (0x04) - { - "USBBusNumber", - Zero, - "AAPL,xhci-clock-id", - One - } - } + Local0 = Package (0x06) + { + "USBBusNumber", + Zero, + "AAPL,xhci-clock-id", + One, + "UsbCompanionControllerPresent", + One + } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) @@ -158,20 +150,22 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Name (HS, Package (0x01) { - "XHC1" + "XHC" }) + Name (FS, Package (0x01) { - "XHC1" + "XHC" }) + Name (LS, Package (0x01) { - "XHC1" + "XHC" }) Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake { - Return (Package (0x02) + Return (Package () { 0x6D, 0x03 @@ -180,53 +174,45 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Method (_PS0, 0, Serialized) // _PS0: Power State 0 { - Debug = "TB:UPSB:DSB2:XHC2:_PS0" - // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - USME: " // One - // Debug = USME - // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBTS: " // One - // Debug = TBTS - // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBSE: " // 0x09 - // Debug = TBSE - // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBAS: " // Zero - // Debug = TBAS + Debug = "TB:DSB2:XHC2:_PS0" If (OSDW ()) { PCED () + + \_SB.PCI0.RP09.TBST () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { - Debug = "TB:UPSB:DSB2:XHC2:_PS3" + Debug = "TB:DSB2:XHC2:_PS3" + + If (OSDW ()) + { + \_SB.PCI0.RP09.TBST () + } } /** - * Run Time Power Check - * Called by XHC driver when idle - */ + * Run Time Power Check + * Called by XHC driver when idle + */ Method (RTPC, 1, Serialized) { - If (OSDW ()) + Debug = Concatenate ("TB:DSB2:XHC2:RTPC called with Arg0: ", Arg0) + + If (Arg0 <= One) { - If (Arg0 <= One) - { - If (Arg0 == One) - { - Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - Enabling" - } + Debug = Concatenate ("TB:NHI0:RTPC setting RUSB to: ", Arg0) - If (Arg0 == Zero) - { - Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - Disabling" - } + \_SB.PCI0.RP09.RUSB = Arg0 - \_SB.PCI0.RP09.RUSB = Arg0 - } - Else + // Force TB on + If (Arg0 == One) { - Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - ??? - Arg0: " - Debug = Arg0 + Debug = Concatenate ("TB:NHI0:RTPC forcing RTBT to: ", Arg0) + \_SB.PCI0.RP09.RTBT = One } } @@ -234,25 +220,17 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) } /** - * USB cable check - * Called by XHC driver to check cable status - * Used as idle hint. - */ + * USB cable check + * Called by XHC driver to check cable status + * Used as idle hint. + * + * Return: + * kUSBTypeCCableTypeNone = 0, + * kUSBTypeCCableTypeUSB = 1, + */ Method (MODU, 0, Serialized) { - If (\_SB.PCI0.RP09.UPSB.MDUV == Zero) - { - Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - unplugged (MDUV = Zero)" - } - ElseIf (\_SB.PCI0.RP09.UPSB.MDUV == One) - { - Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - plugged (MDUV = One)" - } - Else - { - Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - ??? - MDUV: " - Debug = \_SB.PCI0.RP09.UPSB.MDUV - } + Debug = Concatenate ("TB:DSB2:XHC2:MODU - return: ", \_SB.PCI0.RP09.UPSB.MDUV) Return (\_SB.PCI0.RP09.UPSB.MDUV) } @@ -264,31 +242,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Device (SSP1) { Name (_ADR, 0x03) // _ADR: Address - - // Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities - // { - // If ((USME == Zero)) - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x09)) - // } - // Else - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x0A)) - // } - // } - - // Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device - // { - // If ((USME == Zero)) - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, One)) - // } - // Else - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, UPT1)) - // } - // } - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -296,72 +249,34 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + + Name (HS, Package () { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "UPPER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) - }) - Name (HS, Package (0x02) - { - "XHC1", + "XHC", 0x03 }) - Name (FS, Package (0x02) + + Name (FS, Package () { - "XHC1", + "XHC", 0x03 }) - Name (LS, Package (0x02) + + Name (LS, Package () { - "XHC1", + "XHC", 0x03 }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - If (U2OP == One) - { - Local0 = Package (0x04) - { - "UsbCPortNumber", - 0x02, - "UsbCompanionPortPresent", - One - } - } - Else - { - Local0 = Package (0x02) - { - "UsbCPortNumber", - 0x02, - } - } + Local0 = Package () + { + "UsbCPortNumber", + \_SB.PCI0.RP09.UPN1, + "UsbCompanionPortPresent", + One + } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) @@ -371,31 +286,6 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Device (SSP2) { Name (_ADR, 0x04) // _ADR: Address - - // Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities - // { - // If ((USME == Zero)) - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x09)) - // } - // Else - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x0A)) - // } - // } - - // Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device - // { - // If ((USME == Zero)) - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, 0x02)) - // } - // Else - // { - // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, UPT2)) - // } - // } - Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, @@ -403,74 +293,34 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) Zero, Zero }) - Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + + Name (HS, Package () { - ToPLD ( - PLD_Revision = 0x1, - PLD_IgnoreColor = 0x1, - PLD_Red = 0x0, - PLD_Green = 0x0, - PLD_Blue = 0x0, - PLD_Width = 0x0, - PLD_Height = 0x0, - PLD_UserVisible = 0x1, - PLD_Dock = 0x0, - PLD_Lid = 0x0, - PLD_Panel = "UNKNOWN", - PLD_VerticalPosition = "LOWER", - PLD_HorizontalPosition = "LEFT", - PLD_Shape = "UNKNOWN", - PLD_GroupOrientation = 0x0, - PLD_GroupToken = 0x0, - PLD_GroupPosition = 0x0, - PLD_Bay = 0x0, - PLD_Ejectable = 0x0, - PLD_EjectRequired = 0x0, - PLD_CabinetNumber = 0x0, - PLD_CardCageNumber = 0x0, - PLD_Reference = 0x0, - PLD_Rotation = 0x0, - PLD_Order = 0x0, - PLD_VerticalOffset = 0x0, - PLD_HorizontalOffset = 0x0) + "XHC", + 0x04 }) - Name (HS, Package (0x02) + Name (FS, Package () { - "XHC1", + "XHC", 0x04 }) - Name (FS, Package (0x02) + + Name (LS, Package () { - "XHC1", - 0x04 - }) - Name (LS, Package (0x02) - { - "XHC1", + "XHC", 0x04 }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { - If (U2OP == One) - { - Local0 = Package (0x04) - { - "UsbCPortNumber", - One, - "UsbCompanionPortPresent", - One - } - } - Else - { - Local0 = Package (0x02) - { - "UsbCPortNumber", - One, - } - } + Local0 = Package () + { + "UsbCPortNumber", + \_SB.PCI0.RP09.UPN2, + "UsbCompanionPortPresent", + One + } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) @@ -479,4 +329,5 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) } } } + } \ No newline at end of file