diff --git a/.github/README.md b/.github/README.md new file mode 100644 index 0000000..cd400b7 --- /dev/null +++ b/.github/README.md @@ -0,0 +1,250 @@ +# macOS on Thinkpad X1 Carbon 6th Generation, Model 20KH\* + +[![macOS](https://img.shields.io/badge/macOS-Catalina-yellow.svg)](https://www.apple.com/macos/catalina/) +[![version](https://img.shields.io/badge/10.15.7-yellow)](https://support.apple.com/en-us/HT210642) +[![BIOS](https://img.shields.io/badge/BIOS-1.45-blue)](https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x1-carbon-6th-gen-type-20kh-20kg/downloads/driver-list/component?name=BIOS%2FUEFI) +[![MODEL](https://img.shields.io/badge/Model-20KH*-blue)](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) +[![OpenCore](https://img.shields.io/badge/OpenCore-0.6.2-green)](https://github.com/acidanthera/OpenCorePkg) +[![LICENSE](https://img.shields.io/badge/license-MIT-green.svg)](https://github.com/996icu/996.ICU/blob/master/LICENSE) + +Critter + +### Check out my blog [tylerspaper.com](https://tylerspaper.com/) + +#### READ THE ENTIRE README.MD BEFORE YOU START. + +#### I am not responsible for any damages you may cause. + +### Should you find an error, or improve anything, be it in the config itself or in the my documentation, please consider opening an issue or a pull request to contribute. + +`I AM A ONE MAN TEAM, AND A FULL TIME STUDENT. SO, I MIGHT NOT BE ABLE TO RESPOND OR HELP YOU IN A TIMELY MANNER. BUT, I PROMISE I WILL GET TO YOU EVENTUALLY. PLEASE UNDERSTAND.` + +`Lastly, if my work here helped you. Please consider donating, it would mean a lot to me.` + +> ## Update + +##### Recent | [Changelog Archive](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/CHANGELOG.md) + +> ### 2020-10-6 + +#### Changed + +- Updated `config.plsit`: + - Removed depricated ACPI renames in accordance with new ACPI patches. + - Added `Arch` value to each kext entry in accordance with new OpenCore doc. + - Added Thunderbolt 3 Device Properties. + - Added `ExtendBTFeatureFlags` value to replace `BT4LEContinuityFixup` +- Reorganized subdirectories within `/patches/` to make things easier to find and understand. +- Renamed `3_README-POSTinstallation.md` to `SUMMARY.md` since it's not really a step but more of an overview of what patches what. +- More readble and better writing of `SSDT-Keyboard` +- New `SSDT-PNLF` to accomodate `AppleBacklightSmoother.kext` +- New battery patch `SSDT-Battery` that fixes accesses to 16byte-EC-field HWAC (Issue #82). +- `SSDT-Sleep` is an all-in-one sleep patch over `SSDT-PTSWAK`, `SSDT-GPRW`, `SSDT-EXT*` + - It is no longer necessary to set sleep mode to `Linux` in BIOS as it is now indepently set by `SSDT-Sleep` +- `If (_OSI ("Darwin"))` and `SSDT-DTPG` are now replaced in favor of `SSDT-Darwin` and `OSDW`, just like in genuine Macs. +- Removed `USBPorts.kext` in favor of patching/mapping via ACPI with `SSDT-XHC1`, `SSDT-XHC2`, and `SSDT-USBX` +- `README.md`: + - Turned different sections into menus for better readability. + - Merged `3_README-POSTinstallation.md` into the `SUMMARY` section. + +#### Added + +- `update.sh` script to automatically build and replace all ACPI patches +- `SSDT-HWAC` to patch access to 16byte-EC-field HWAC +- `SSDT-EC` to patch embedded controller for use with `YogaSMC` +- `SSDT-Debug`, `SSDT-HOOKS`, and `Debug.plist` for debugging if needed +- `SSDT-INIT` to configure system values: `HPET`, `DYTC`, and `DPTF` +- `YogaSMC.kext` to interface with the device's EC. Make sure to also install the [app and pref pane](https://github.com/zhen-zen/YogaSMC/releases). +- `AppleBacklightSmoother.kext` is just as its name implies. +- `BrightnessKeys.kext` to handle Fn keys with ACPI renames. +- Documentation of modding the Thunderbolt 3 controller. + +#### Removed + +- `SSDT-HPET`, similar to genuine Macs, HPET is now disabled within `SSDT-INIT` + +#### Remark +- A large of these changes are due to the hardwork of [@benbender](https://github.com/benbender), who debugged and authored many of the new ACPI patches. Thank you for your hard work! + +
+ SUMMARY +
+ +> ### Non-Fuctional: +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Fingerprint Reader | ❌ | `DISABLED` in BIOS to save power if not used in other OSes. | Linux support was only recently added | +| Wireless WAN | ❌ | `DISABLED` in BIOS to save power if not used in other OSes. | Unable to investigate as I have no need and my model did not come with WWAN. | + +> ### Video and Audio +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Full Graphics Accleration (QE/CI) | ✅ | `WhateverGreen.kext` | - | +| Audio Recording | ✅ | `AppleALC.kext` with Layout ID = 21 | - | +| Audio Playback | ✅ | `AppleALC.kext` with Layout ID = 21 | - | +| Automatic Headphone Output Switching | ✅ | `AppleALC.kext` with Layout ID = 21 | - | + +> ### Power, Charge, Sleep and Hibernation +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Battery Percentage Indication | ✅ | `SSDT-Battery.aml` and `/patches/OpenCore Patches/Battery.plist` | +| CPU Power Management (SpeedShift) | ✅ | `XCPM` and `CPUFriend.kext`, generate your own `CPUFriendDataProvider` with [CPUFriendFriend](https://github.com/corpnewt/CPUFriendFriend_) or [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). | +| iGPU Power Management | ✅ | `XCPM`, enabled by `SSDT-PLUG.aml` | +| NVMe Drive Battery Management | ✅ | `NVMeFix.kext` | In my experience, NVMe drives will drain more power than SATA drives. | +| S3 Sleep/ Hibernation Mode 3 | ✅ | `SSDT-Sleep.aml` | | +| Hibernation Mode 25 | ✅ | `RTCMemoryFixup.kext` and `HibernationFixup.kext` | Supported, macOS uses mode 3 by default. Change to mode 25 via `pmset`. | +| Custom Charge Threshold | ✅ | `SSDT-EC.aml`, [YogaSMC.kext](https://github.com/zhen-zen/YogaSMC), and [YogaSMCPane](https://github.com/zhen-zen/YogaSMC)| Adjust with YogaSMCPane in System Preferences +| Battery Life | ✅ | Native, comparable to Windows/Linux. Biggest impact is TB3, see [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) | + +> ### Input/ Output +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| WiFi | ✅ | Native with BCM94360CS2. See `/patches/ Network Patches/` otherwise. | See `/patches/OpenCore Patches/` for specific network card. | +| Bluetooth | ✅ | Native with BCM94360CS2. See `/patches/ Network Patches/` otherwise. | See `/patches/Network Patches/` for specific network card. | +| Ethernet | ✅ | `IntelMausi.kext` | Needs Lenovo Ethernet adapter: [Item page](https://www.lenovo.com/us/en/accessories-and-monitors/cables-and-adapters/adapters/CABLE-BO-Ethernet-Extension-Adapter-2/p/4X90Q84427) | +| HDMI hotplug | ✅ | Custom EDID Override `/patches/Internal Displays/` | Refer to [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) if one does not exist already for your display. | +| 4K UHD output via HDMI/ DisplayPort **(Modded BIOS)** | ✅ | See `DMVT Pre-Allocated` to `64M` | See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) for information about modding the BIOS. | +| 4K UHD output via HDMI/ DisplayPort **(Vanilla BIOS)** | ✅ | See `/patches/OpenCore Patches/4K-Output-wo-BIOSmod.plist` | - | +| USB 2.0, USB 3.0, and Micro SD Card Reader | ✅ | `SSDT-XHC1.aml` | - | +| USB 3.1 | ⚠️ | `SSDT-XHC2.aml` | - | +| USB Power Properties in macOS | ✅ | `SSDT-USBX.aml` | - | +| Thunderbolt 3 **(Cold Boot)** | ✅ | `SSDT-TB3.aml`, | TB3 device must be plugged in before boot. | +| Thunderbolt 3 Hotplug **(Modded Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | +| Thunderbolt 3 Hotplug **(Modded Controller and Vanilla BIOS)** | ⚠️ | `SSDT-TB3.aml` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | +| Thunderbolt 3 Hotplug **(Vanilla Controller and Modded BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | +| Thunderbolt 3 Hotplug **(Vanilla Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext`, and `TbtForcePower.efi` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | + +> ### Display, TrackPad, TrackPoint, and Keyboard +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Brightness Adjustments | ✅ | `WhateverGreen.kext`, `SSDT-PNLF.aml`, `AppleBacklightSmoother.kext`, and `BrightnessKeys.kext`| `AppleBacklightSmoother.kext` is optional for smoother birghtness adjustments | +| HiDPI _(Optional)_ | ✅ | [xzhih/one-key-hidpi](https://github.com/xzhih/one-key-hidpi) | Scaling issues post-sleep fixed with AAPL, ig-platform `BAAnWQ==` | +| TrackPoint | ✅ | `VoodooPS2Controller.kext` | - | +| TrackPad | ✅ | `VoodooPS2Controller.kext` or `VoodooRMI.kext` | I prefer `VoodooRMI.kext` so that is the repository default. | +| Built-in Keyboard | ✅ | `VoodooPS2Controller.kext` | Optimizations recommended, see [`docs/4_README-other.md`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-other.md) | +| Multimedia Keys | ✅ | [YogaSMC](https://github.com/zhen-zen/YogaSMC) or [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) | - | + +> ### macOS Continuity +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| iCloud, iMessage, FaceTime | ✅ | Whitelisted Apple ID, Valid SMBIOS | See [dortania /OpenCore-Install-Guide](https://dortania.github.io/OpenCore-Post-Install/universal/iservices.html) | +| Continuty | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. | See `/patches/Network Patches/` for specific network card. | +| AirDrop | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. | See `/patches/Network Patches/` for specific network card. | +| Sidecar | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. iPad with >= `iPadOS 13` | Tested with iPad Mini with iPadOS 13.1.2 | +| FileVault | ✅ | as configured in `config.plsit` per [Dortania's Post-Install](https://dortania.github.io/OpenCore-Post-Install/universal/security/filevault.html)| | +| Time Machine | ✅ | Native | TimeMachine only backups your Macintosh partition. Manually backup your EFI partition using another method. | + +
+ +
+ REFERENCES +
+ +* Read these before you start: +- [dortania's Hackintosh guides](https://github.com/dortania) +- [dortania's OpenCore Install Guide](https://dortania.github.io/OpenCore-Install-Guide/) +- [dortania's OpenCore Post Install Guide](https://dortania.github.io/OpenCore-Post-Install/) +- [dortania/ Getting Started with ACPI](https://dortania.github.io/Getting-Started-With-ACPI/) +- [dortania/ opencore `multiboot`](https://github.com/dortania/OpenCore-Multiboot) +- [dortania/ `USB map` guide](https://dortania.github.io/OpenCore-Post-Install/usb/) +- [WhateverGreen Intel HD Manual](https://github.com/acidanthera/WhateverGreen/blob/master/Manual/FAQ.IntelHD.en.md) +- `Configuration.pdf` and `Differences.pdf` in each `OpenCore` releases. +- Additionally, references specific to the x1c6 are located in `docs/references/` + +* ### No seriously, please read those. +
+ +
+ NEEDED +
+ +- A macOS machine(optional): to create the macOS installer. +- Flash drive, 12GB or more, for the above purpose. +- Xcode works fine for editing plist files on macOS, but I prefer [PlistEdit Pro](https://www.fatcatsoftware.com/plisteditpro/). +- [ProperTree](https://github.com/corpnewt/ProperTree) if you need to edit plist files on Windows. +- [MaciASL](https://github.com/acidanthera/MaciASL), for patching ACPI tables and editing ACPI patches. +- [MountEFI](https://github.com/corpnewt/MountEFI) to quickly mount EFI partitions. +- [IORegistryExplorer](https://developer.apple.com/downloads), for diagnosis. +- [Hackintool](https://www.insanelymac.com/forum/topic/335018-hackintool-v286/), for diagnostic ONLY, Hackintool should not be used for patching, it is outdated. +- [SPI Programmer CH341a and SOIC8 connector](https://www.amazon.com/Organizer-Socket-Adpter-Programmer-CH341A/dp/B07R5LPTYM) are needed if you are going to mod your BIOS/TB3 controller for optimizations and a better and more native macOS experience. +- Patience and time, especially if this is your first time Hackintosh-ing. + +
+ +
+ SPECIFICATIONS +
+- These are relevant components on my machine which may differ from yours, keep these in ind as you will need to adjust accordingly, depending on your machine's configuration. + +| Category | Component | +| --------- | ------------------------------------ | +| CPU | [i7-8650U](https://ark.intel.com/content/www/us/en/ark/products/124968/intel-core-i7-8650u-processor-8m-cache-up-to-4-20-ghz.html) | +| GPU | Intel UHD 620 | +| SSD | Seagate Firecuda 520 500GB | +| Display | 14.0" (355mm) HDR WQHD (2560x1440) | +| WiFi & BT | BCM94360CS2 | +| WWAN | None | + +- Refer to [/docs/references/x1c6-Platform_Specifications](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) for possible stock ThinkPad X1 6th Gen configurations. + +
+ +
+ GETTING STARTED +
+ +Before you do anything, please familiarize yourself with basic Hackintosh terminologies and the basic Hackintosh process by throughly reading Dortania guides as linked in `REFERENCES` + +- Creating a macOS installer: refer to [Dortania's OpenCore Install Guide](https://dortania.github.io/OpenCore-Install-Guide/installer-guide/) +- [**1_README-HARDWAREandBIOS**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md): Requirements before installing. +- [**2_README-ACPIpatching**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-ACPIpatching.md): Notes and explainations for ACPI hotpatches. +- [**3_README-other.md**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-other.md): for post installation settings and other remarks. + +
+ +
+ OTHER REPOSITORIES +
+ +- x1c6-hackintosh repositories: + - [benbender/x1c6-hackintosh](https://github.com/benbender/x1c6-hackintosh) + - [zhtengw/EFI-for-X1C6-hackintosh](https://github.com/zhtengw/EFI-for-X1C6-hackintosh) +- t480-hackintosh repositories: + - [EETagent/T480-OpenCore-Hackintosh](https://github.com/EETagent/T480-OpenCore-Hackintosh) +Create a pull request if you like to be added, final decision at my discreation. +
+ +> ## CONTACT + +https://tylerspaper.com/contact +Signal: +1 (202)-644-9951 \*This is a Signal ONLY number. You will not get a reply of you text me at this number. + +> ## SUPPORT + +https://tylerspaper.com/support/ + +
+ CREDITS +
+ +- [@benbender](https://github.com/benbender) for your hardwork. Much of this repo comes from your research and code. Thank you! +- [@Fewtarius](https://github.com/fewtarius) for your help with patching audio. +- [@Colton-Ko](https://github.com/Colton-Ko/macOS-ThinkPad-X1C6) for the great features template. +- [@stevezhengshiqi](https://github.com/stevezhengshiqi) for the one-key-cpufriend script. +- [@corpnewt](https://github.com/corpnewt) for [GibMacOS](https://github.com/corpnewt/gibMacOS) and [EFIMount](https://github.com/corpnewt/MountEFI). +- [@xzhih](https://github.com/xzhih) for one-key-hidpi. +- [daliansky/OC-little](https://github.com/daliansky/OC-little) for various ACPI hotpatch samples. +- [@velaar](https://github.com/velaar) for your continual support and contributions. +- [@Porco-Rosso](https://github.com/Porco-Rosso) putting up with my requests to test repo changes. +- [@MSzturc](https://github.com/MSzturc) for adding my requested features to ThinkpadAssistant. +paranoidbashthot and \x for the BIOS mod to unlocked Intel Advance Menu. +- [@zhen-zen](https://github.com/zhen-zen) for YogaSMC +- [CaseySJ](https://www.tonymacx86.com/members/caseysj.2134452/) for the custom Thunderbolt 3 firmware. + +The greatest thank you and appreciation to the [Acidanthera](https://github.com/acidanthera) team. + +And to everyone else who supports and uses my project. + +Please let me know if I missed you. + +
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diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml index 26093c0..d7f1e4a 100644 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Keyboard.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-LED.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-LED.aml deleted file mode 100644 index ea38620..0000000 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-LED.aml and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-OCBAT0-TP_tx80_x1c6th.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-OCBAT0-TP_tx80_x1c6th.aml deleted file mode 100644 index 214bb54..0000000 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-OCBAT0-TP_tx80_x1c6th.aml and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-PLUG-_PR.PR00.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-PLUG-_PR.PR00.aml deleted file mode 100644 index a1ed4f0..0000000 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-PLUG-_PR.PR00.aml and /dev/null differ diff --git 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0000000..4e284b7 Binary files /dev/null and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Sleep.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml new file mode 100644 index 0000000..368b560 Binary files /dev/null and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-TB3.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml new file mode 100644 index 0000000..8a879f6 Binary files /dev/null and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-USBX.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml new file mode 100644 index 0000000..854f75f Binary files /dev/null and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC1.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml new file mode 100644 index 0000000..a6b2cba Binary files /dev/null and b/EFI-OpenCore/EFI/OC/ACPI/SSDT-XHC2.aml differ diff --git a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Z390-TB3HP.aml b/EFI-OpenCore/EFI/OC/ACPI/SSDT-Z390-TB3HP.aml deleted file mode 100755 index b235c82..0000000 Binary files a/EFI-OpenCore/EFI/OC/ACPI/SSDT-Z390-TB3HP.aml and /dev/null differ diff --git a/EFI-OpenCore/EFI/OC/Drivers/AudioDxe.efi b/EFI-OpenCore/EFI/OC/Drivers/AudioDxe.efi index 857465b..5915701 100644 Binary files a/EFI-OpenCore/EFI/OC/Drivers/AudioDxe.efi and b/EFI-OpenCore/EFI/OC/Drivers/AudioDxe.efi differ diff --git a/EFI-OpenCore/EFI/OC/Drivers/OpenCanopy.efi b/EFI-OpenCore/EFI/OC/Drivers/OpenCanopy.efi index db302de..200b90a 100644 Binary files a/EFI-OpenCore/EFI/OC/Drivers/OpenCanopy.efi and b/EFI-OpenCore/EFI/OC/Drivers/OpenCanopy.efi differ diff --git a/EFI-OpenCore/EFI/OC/Drivers/OpenRuntime.efi b/EFI-OpenCore/EFI/OC/Drivers/OpenRuntime.efi index 11158ab..42cfc13 100644 Binary files a/EFI-OpenCore/EFI/OC/Drivers/OpenRuntime.efi and b/EFI-OpenCore/EFI/OC/Drivers/OpenRuntime.efi differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/Info.plist index 6466b02..d2c1248 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 20A5384c + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -29,21 +29,36 @@ DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild - 12A7300 - DTPlatformName - macosx + 11E708 DTPlatformVersion - 10.15.6 + GM DTSDKBuild 19G68 DTSDKName macosx10.15 DTXcode - 1201 + 1160 DTXcodeBuild - 12A7300 + 11E708 IOKitPersonalities + ALCUserClientProvider + + CFBundleIdentifier + as.vit9696.AppleALC + IOClass + ALCUserClientProvider + IOMatchCategory + ALCUserClientProvider + IOProbeScore + 1000 + IOProviderClass + IOResources + IOResourceMatch + IOKit + IOUserClientClass + ALCUserClient + HDA Hardware Config Resource CFBundleIdentifier @@ -898,14 +913,20 @@ ConfigData ASccEAEnHQABJx6gAScfkAFHHCABRx0AAUce - FwFHH5ABlxwwAZcdEAGXHosBlx8EAhccQAIX - HRACFx4rAhcfBAE3HFABNx0AATceAAE3H0AB - 1xxgAdcdsAHXHmYB1x9AAUcMAgGXDAI= + FwFHH5ABRwwCAZccMAGXHRABlx6BAZcfBAIX + HEACFx0QAhceKwIXHwQCFwwCATccUAE3HQAB + Nx4AATcfQAHXHGAB1x2wAdceZgHXH0A= FuncGroup 1 LayoutID 13 + WakeConfigData + + AUcMAgIXDAIBlwcl + + WakeVerbReinit + AFGLowPowerState @@ -918,9 +939,9 @@ 283902512 ConfigData - AhccEAIXHRACFx4rAhcfBAFHHCABRx0BAUce - FwFHH5ABJxwwAScdAQEnHqABJx+QAZccQAGX - HRABlx6LAZcfBAFHDAI= + AUccEAFHHQEBRx4XAUcfkAFHDAICFxwgAhcd + EAIXHiECFx8TAhcMAgEnHDABJx0BASceoAEn + H5ABlxxAAZcdEQGXHoEBlx+T FuncGroup 1 @@ -928,7 +949,7 @@ 20 WakeConfigData - AZcHJQ== + AUcMAgIXDAIBlwcl WakeVerbReinit @@ -1486,6 +1507,36 @@ WakeVerbReinit + + AFGLowPowerState + + AwAAAA== + + Codec + Realtek ALC235 for Lenovo Qitian M420 by Cryse Hillmes + CodecID + 283902517 + ConfigData + + AScc8AEnHQABJx4AAScfQAFHHBABRx0BAUce + FwFHH5ABdxzwAXcdAAF3HgABdx9AAYcc8AGH + HQABhx4AAYcfQAGXHHABlx0QAZceoQGXHwIB + pxwgAacdEAGnHoEBpx8CAbccgAG3HRABtx4B + AbcfAQHXHPAB1x0AAdceAAHXH0AB5xzwAecd + AAHnHgAB5x9AAhccUAIXHRACFx4hAhcfAgFH + DAIBtwwCAhcMAgIXB8ACFwiCAZcHJA== + + FuncGroup + 1 + LayoutID + 35 + WakeConfigData + + AUcMAgG3DAICFwwCAhcHwAIXCIIBlwck + + WakeVerbReinit + + AFGLowPowerState @@ -4460,6 +4511,32 @@ WakeVerbReinit + + AFGLowPowerState + + AwAAAA== + + Codec + Realtek ALC 272 for Lenovo Y470 by amu_1680c + CodecID + 283902578 + ConfigData + + ASccEAEnHQEBJx6gAScfkAGHHCABhx0AAYce + gQGHHwEBRxwwAUcdAQFHHhABRx+QAhccQAIX + HRACFx4hAhcfAQFHDAI= + + FuncGroup + 1 + LayoutID + 12 + WakeConfigData + + AUcMAg== + + WakeVerbReinit + + AFGLowPowerState @@ -5766,6 +5843,33 @@ WakeVerbReinit + + AFGLowPowerState + + AwAAAA== + + CodecID + 283902608 + Comment + ALC3241 - HP Envy 15t-k200 Beats Audio 2.1 + ConfigData + + AaccEAGnHRABpx6BAacfAAEnHCABJx0AASce + owEnH5ABRxwwAUcdAQFHHhABRx+QAXccMQF3 + HQEBdx4QAXcfkAFXHFABVx0QAVceIQFXHwAB + RwwC + + FuncGroup + 1 + LayoutID + 10 + WakeConfigData + + AUcMAg== + + WakeVerbReinit + + AFGLowPowerState @@ -9086,6 +9190,38 @@ LayoutID 99 + + AFGLowPowerState + + AwAAAA== + + CodecID + 283904146 + Comment + Custom ALC892 for MSI Z370-A PRO by GeorgeWan + ConfigData + + ARcc8AEXHQABFx4AARcfQAEnHPABJx0AASce + AAEnH0ABRxwQAUcdQAFHHhEBRx+QAUcMAgFX + HCABVx0QAVceAQFXHwEBZxwwAWcdYAFnHgEB + Zx8BAXccQAF3HSABdx4BAXcfAQGHHFABhx2Q + AYceoAGHH5ABlxxwAZcdkAGXHoEBlx8CAacc + YAGnHTABpx6BAacfAQG3HIABtx1AAbceIQG3 + HwIBtwwCAccc8AHHHQABxx4AAccfQAHXHPAB + 1x0AAdceAAHXH0AB5xzwAecdAAHnHgAB5x9A + Afcc8AH3HQAB9x4AAfcfQA== + + FuncGroup + 1 + LayoutID + 100 + WakeConfigData + + AUcMAgG3DAI= + + WakeVerbReinit + + AFGLowPowerState @@ -10223,6 +10359,36 @@ WakeVerbReinit + + AFGLowPowerState + + AwAAAA== + + CodecID + 283904768 + CodecName + GeorgeWan - ALCS1200A for ASROCK Z490 Steel Legend + ConfigData + + ARcc8AEXHQABFx4AARcfQAFHHBABRx1AAUce + EQFHH5ABRwwCAVccIAFXHRABVx4BAVcfAQFn + HDABZx1gAWceAQFnHwEBdxzwAXcdAAF3HgAB + dx9AAYccQAGHHZABhx6gAYcfkAGXHGABlx2Q + AZcegQGXHwIBpxxQAacdMAGnHoEBpx8BAbcc + cAG3HUABtx4hAbcfAgG3DAIB5xyAAecdYQHn + HksB5x8B + + FuncGroup + 1 + LayoutID + 51 + WakeConfigData + + AUcMAgG3DAI= + + WakeVerbReinit + + AFGLowPowerState @@ -12229,6 +12395,33 @@ WakeVerbReinit + + AFGLowPowerState + + AwAAAA== + + Codec + ALC662v3 for Lenovo M415-D339 by Eric + CodecID + 283903586 + ConfigData + + AUccEAFHHUABRx4RAUcfAQFHDAIBtxwgAbcd + EAG3HiEBtx8CAbcMAgGHHDABhx2QAYcegAGH + HwEBlxxAAZcdEAGXHoABlx8CAaccXwGnHTAB + px6BAacfAQ== + + FuncGroup + 1 + LayoutID + 66 + WakeConfigData + + AUcMAg== + + WakeVerbReinit + + IOClass AppleHDAHardwareConfigDriver diff --git a/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/MacOS/AppleALC b/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/MacOS/AppleALC index 888fd58..b9fd22f 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/MacOS/AppleALC and b/EFI-OpenCore/EFI/OC/Kexts/AppleALC.kext/Contents/MacOS/AppleALC differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/Info.plist new file mode 100644 index 0000000..32d4fa8 --- /dev/null +++ b/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/Info.plist @@ -0,0 +1,85 @@ + + + + + BuildMachineOSBuild + 19F101 + CFBundleDevelopmentRegion + en + CFBundleExecutable + AppleBacklightSmoother + CFBundleIdentifier + com.hieplpvip.AppleBacklightSmoother + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + AppleBacklightSmoother + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.0.2 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 11E708 + DTPlatformVersion + GM + DTSDKBuild + 19G68 + DTSDKName + macosx10.15 + DTXcode + 1160 + DTXcodeBuild + 11E708 + IOKitPersonalities + + AppleBacklightSmoother + + CFBundleIdentifier + com.hieplpvip.AppleBacklightSmoother + IOClass + AppleBacklightSmoother + IOMatchCategory + AppleBacklightSmoother + IOProviderClass + IOResources + IOResourceMatch + IOKit + + + LSMinimumSystemVersion + 10.8 + NSHumanReadableCopyright + Copyright © 2020 Le Bao Hiep. All rights reserved. + OSBundleCompatibleVersion + 1.0 + OSBundleLibraries + + as.vit9696.Lilu + 1.2.0 + com.apple.iokit.IOPCIFamily + 1.0.0b1 + com.apple.kpi.bsd + 12.0.0 + com.apple.kpi.dsep + 12.0.0 + com.apple.kpi.iokit + 12.0.0 + com.apple.kpi.libkern + 12.0.0 + com.apple.kpi.mach + 12.0.0 + com.apple.kpi.unsupported + 12.0.0 + + OSBundleRequired + Root + + diff --git a/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/MacOS/AppleBacklightSmoother b/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/MacOS/AppleBacklightSmoother new file mode 100644 index 0000000..8087404 Binary files /dev/null and b/EFI-OpenCore/EFI/OC/Kexts/AppleBacklightSmoother.kext/Contents/MacOS/AppleBacklightSmoother differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/Info.plist new file mode 100644 index 0000000..860a818 --- /dev/null +++ b/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/Info.plist @@ -0,0 +1,79 @@ + + + + + BuildMachineOSBuild + 19H2 + CFBundleDevelopmentRegion + en + CFBundleExecutable + BrightnessKeys + CFBundleIdentifier + as.acidanthera.BrightnessKeys + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + BrightnessKeys + CFBundlePackageType + KEXT + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.0.1 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 11E708 + DTPlatformVersion + GM + DTSDKBuild + 19G68 + DTSDKName + macosx10.15 + DTXcode + 1160 + DTXcodeBuild + 11E708 + IOKitPersonalities + + BrightnessKeys + + CFBundleIdentifier + as.acidanthera.BrightnessKeys + IOClass + BrightnessKeys + IOMatchCategory + BrightnessKeys + IOProviderClass + IOResources + IOResourceMatch + IOKit + + + LSMinimumSystemVersion + 10.11 + OSBundleLibraries + + as.vit9696.Lilu + 1.2.0 + com.apple.iokit.IOACPIFamily + 1.0.0d1 + com.apple.iokit.IOHIDFamily + 1.0.0b1 + com.apple.kpi.bsd + 8.0.0 + com.apple.kpi.iokit + 8.0.0 + com.apple.kpi.libkern + 8.0.0 + com.apple.kpi.mach + 8.0.0 + com.apple.kpi.unsupported + 8.0.0 + + OSBundleRequired + Console + + diff --git a/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/MacOS/BrightnessKeys b/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/MacOS/BrightnessKeys new file mode 100644 index 0000000..113901f Binary files /dev/null and b/EFI-OpenCore/EFI/OC/Kexts/BrightnessKeys.kext/Contents/MacOS/BrightnessKeys differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/Info.plist index 5ef942e..3d0f2b2 100755 --- a/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.3.6 + 1.3.7 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 1.3.6 + 1.3.7 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/MacOS/HibernationFixup b/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/MacOS/HibernationFixup index 6634bd1..0259bf0 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/MacOS/HibernationFixup and b/EFI-OpenCore/EFI/OC/Kexts/HibernationFixup.kext/Contents/MacOS/HibernationFixup differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/Info.plist index e7df6fe..415e5e5 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.4.8 + 1.4.9 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 1.4.8 + 1.4.9 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/MacOS/Lilu b/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/MacOS/Lilu index fb2027f..a5862cb 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/MacOS/Lilu and b/EFI-OpenCore/EFI/OC/Kexts/Lilu.kext/Contents/MacOS/Lilu differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/Info.plist index ea28edb..fdf60fa 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,13 +17,13 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.1.7 + 1.1.8 CFBundleSupportedPlatforms MacOSX CFBundleVersion - 1.1.7 + 1.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/MacOS/SMCBatteryManager b/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/MacOS/SMCBatteryManager index 92e31c3..b4558e0 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/MacOS/SMCBatteryManager and b/EFI-OpenCore/EFI/OC/Kexts/SMCBatteryManager.kext/Contents/MacOS/SMCBatteryManager differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/Info.plist index a0b6063..9ee0422 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,13 +17,13 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.1.7 + 1.1.8 CFBundleSupportedPlatforms MacOSX CFBundleVersion - 1.1.7 + 1.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/MacOS/SMCLightSensor b/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/MacOS/SMCLightSensor index 72d1fb5..3fa1653 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/MacOS/SMCLightSensor and b/EFI-OpenCore/EFI/OC/Kexts/SMCLightSensor.kext/Contents/MacOS/SMCLightSensor differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/Info.plist index 88719a6..4ba63a5 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.1.7 + 1.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 1.1.7 + 1.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/MacOS/SMCProcessor b/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/MacOS/SMCProcessor index 3517585..fd30330 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/MacOS/SMCProcessor and b/EFI-OpenCore/EFI/OC/Kexts/SMCProcessor.kext/Contents/MacOS/SMCProcessor differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/USBPorts.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/USBPorts.kext/Contents/Info.plist deleted file mode 100755 index 84df123..0000000 --- a/EFI-OpenCore/EFI/OC/Kexts/USBPorts.kext/Contents/Info.plist +++ /dev/null @@ -1,140 +0,0 @@ - - - - - CFBundleDevelopmentRegion - English - CFBundleGetInfoString - 1.0 Copyright © 2018 Headsoft. All rights reserved. - CFBundleIdentifier - com.Headsoft.USBPorts - CFBundleInfoDictionaryVersion - 6.0 - CFBundleName - USBPorts - CFBundlePackageType - KEXT - CFBundleShortVersionString - 1.0 - CFBundleSignature - ???? - CFBundleVersion - 1.0 - IOKitPersonalities - - MacBookPro14,1-XHC - - CFBundleIdentifier - com.apple.driver.AppleUSBMergeNub - IOClass - AppleUSBMergeNub - IONameMatch - XHC - IOProbeScore - 5000 - IOProviderClass - AppleUSBXHCIPCI - IOProviderMergeProperties - - port-count - DwAAAA== - ports - - HS01 - - UsbConnector - 3 - port - AQAAAA== - - HS02 - - UsbConnector - 3 - port - AgAAAA== - - HS03 - - UsbConnector - 3 - port - AwAAAA== - - HS04 - - UsbConnector - 3 - port - BAAAAA== - - HS07 - - UsbConnector - 255 - port - BwAAAA== - - HS08 - - UsbConnector - 255 - port - CAAAAA== - - HS09 - - UsbConnector - 255 - port - CQAAAA== - - SS01 - - UsbConnector - 9 - port - DQAAAA== - - SS02 - - UsbConnector - 9 - port - DgAAAA== - - SS03 - - UsbConnector - 255 - port - DwAAAA== - - - - model - MacBookPro14,1 - - MacBookPro14,1 - - CFBundleIdentifier - com.apple.driver.AppleUSBHostMergeProperties - IOClass - AppleUSBHostMergeProperties - IOProviderClass - AppleBusPowerController - IOProviderMergeProperties - - kUSBSleepPortCurrentLimit - 3000 - kUSBWakePortCurrentLimit - 3000 - - model - MacBookPro14,1 - - - OSBundleRequired - Root - - diff --git a/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/Info.plist index 1987018..d643755 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.1.7 + 1.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 1.1.7 + 1.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/MacOS/VirtualSMC b/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/MacOS/VirtualSMC index c0fb626..684239c 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/MacOS/VirtualSMC and b/EFI-OpenCore/EFI/OC/Kexts/VirtualSMC.kext/Contents/MacOS/VirtualSMC differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/Info.plist index 13d769f..23ca4a3 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/Info.plist @@ -3,11 +3,11 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleExecutable VoodooPS2Controller CFBundleGetInfoString - 2.1.7, Copyright Apple Computer, Inc. 2000-2003, David Elliot 2007, RehabMan 2012-2013 + 2.1.8, Copyright Apple Computer, Inc. 2000-2003, David Elliot 2007, RehabMan 2012-2013 CFBundleIdentifier as.acidanthera.voodoo.driver.PS2Controller CFBundleInfoDictionaryVersion @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 2.1.7 + 2.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 2.1.7 + 2.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild @@ -137,7 +137,7 @@ LSMinimumSystemVersion 10.11 OSBundleCompatibleVersion - 2.1.7 + 2.1.8 OSBundleLibraries com.apple.iokit.IOACPIFamily diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/MacOS/VoodooPS2Controller b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/MacOS/VoodooPS2Controller index 3850400..f42e4aa 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/MacOS/VoodooPS2Controller and b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/MacOS/VoodooPS2Controller differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/Info.plist index 303f9a9..e0c4dae 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/Info.plist @@ -3,11 +3,11 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleExecutable VoodooPS2Keyboard CFBundleGetInfoString - 2.1.7, Copyright Apple Computer, Inc. 2000-2003, RehabMan 2012-2013 + 2.1.8, Copyright Apple Computer, Inc. 2000-2003, RehabMan 2012-2013 CFBundleIdentifier as.acidanthera.voodoo.driver.PS2Keyboard CFBundleInfoDictionaryVersion @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 2.1.7 + 2.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 2.1.7 + 2.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild @@ -598,7 +598,7 @@ OSBundleLibraries as.acidanthera.voodoo.driver.PS2Controller - 2.1.7 + 2.1.8 com.apple.iokit.IOHIDFamily 1.0.0b1 com.apple.kpi.bsd diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/MacOS/VoodooPS2Keyboard b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/MacOS/VoodooPS2Keyboard index c6e27c6..db77b2e 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/MacOS/VoodooPS2Keyboard and b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Keyboard.kext/Contents/MacOS/VoodooPS2Keyboard differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/Info.plist index 4a21ff2..6b5ea16 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/Info.plist @@ -3,11 +3,11 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleExecutable VoodooPS2Mouse CFBundleGetInfoString - 2.1.7, Copyright Apple Computer, Inc. 2000-2004, Slice 2010, RehabMan 2012-2013 + 2.1.8, Copyright Apple Computer, Inc. 2000-2004, Slice 2010, RehabMan 2012-2013 CFBundleIdentifier as.acidanthera.voodoo.driver.PS2Mouse CFBundleInfoDictionaryVersion @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 2.1.7 + 2.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 2.1.7 + 2.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild @@ -180,7 +180,7 @@ OSBundleLibraries as.acidanthera.voodoo.driver.PS2Controller - 2.1.7 + 2.1.8 com.apple.iokit.IOHIDFamily 1.0.0b1 com.apple.kpi.iokit diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/MacOS/VoodooPS2Mouse b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/MacOS/VoodooPS2Mouse index abb486d..b9910fb 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/MacOS/VoodooPS2Mouse and b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Mouse.kext/Contents/MacOS/VoodooPS2Mouse differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/Info.plist index a7efc84..f72fbc5 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/Info.plist @@ -3,11 +3,11 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleExecutable VoodooPS2Trackpad CFBundleGetInfoString - 2.1.7, Copyright Apple Computer, Inc. 2002-2003, mackerintel 2008, RehabMan 2012-2013 + 2.1.8, Copyright Apple Computer, Inc. 2002-2003, mackerintel 2008, RehabMan 2012-2013 CFBundleIdentifier as.acidanthera.voodoo.driver.PS2Trackpad CFBundleInfoDictionaryVersion @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 2.1.7 + 2.1.8 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 2.1.7 + 2.1.8 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild @@ -490,7 +490,7 @@ OSBundleLibraries as.acidanthera.voodoo.driver.PS2Controller - 2.1.7 + 2.1.8 com.apple.iokit.IOHIDFamily 1.0.0b1 com.apple.kpi.iokit diff --git a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/MacOS/VoodooPS2Trackpad b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/MacOS/VoodooPS2Trackpad index a8f357f..6e2c09d 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/MacOS/VoodooPS2Trackpad and b/EFI-OpenCore/EFI/OC/Kexts/VoodooPS2Controller.kext/Contents/PlugIns/VoodooPS2Trackpad.kext/Contents/MacOS/VoodooPS2Trackpad differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/Info.plist index a437a39..1d73ee7 100644 --- a/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/Info.plist +++ b/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/Info.plist @@ -3,7 +3,7 @@ BuildMachineOSBuild - 19F101 + 19H2 CFBundleDevelopmentRegion en CFBundleExecutable @@ -17,7 +17,7 @@ CFBundlePackageType KEXT CFBundleShortVersionString - 1.4.3 + 1.4.4 CFBundleSignature ???? CFBundleSupportedPlatforms @@ -25,7 +25,7 @@ MacOSX CFBundleVersion - 1.4.3 + 1.4.4 DTCompiler com.apple.compilers.llvm.clang.1_0 DTPlatformBuild diff --git a/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/MacOS/WhateverGreen b/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/MacOS/WhateverGreen index 10ce2d9..03c923c 100755 Binary files a/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/MacOS/WhateverGreen and b/EFI-OpenCore/EFI/OC/Kexts/WhateverGreen.kext/Contents/MacOS/WhateverGreen differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist new file mode 100644 index 0000000..f0e63d5 --- /dev/null +++ b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/Info.plist @@ -0,0 +1,168 @@ + + + + + BuildMachineOSBuild + 19H2 + CFBundleDevelopmentRegion + en + CFBundleExecutable + YogaSMC + CFBundleIdentifier + org.zhen.YogaSMC + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + YogaSMC + CFBundlePackageType + KEXT + CFBundleShortVersionString + 1.2.1 + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.2.1 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 12A7300 + DTPlatformName + macosx + DTPlatformVersion + 10.15.6 + DTSDKBuild + 19G68 + DTSDKName + macosx10.15 + DTXcode + 1201 + DTXcodeBuild + 12A7300 + IOKitPersonalities + + IdeaVPC + + CFBundleIdentifier + org.zhen.YogaSMC + IOClass + IdeaVPC + IONameMatch + VPC2004 + IOProbeScore + 200 + IOProviderClass + IOACPIPlatformDevice + IOUserClientClass + YogaSMCUserClient + Sensors + + Airflow Left + + Airflow Right + + CPU Core PECI + CPEC + CPU System Agent Core + CTMP + Memory Proximity + MEM1 + Platform Controller Hub Die + RSEN + SO-DIMM 1 Proximity + MEM1 + SO-DIMM 2 Proximity + MEM2 + SO-DIMM 3 Proximity + + SO-DIMM 4 Proximity + + + + ThinkVPC + + CFBundleIdentifier + org.zhen.YogaSMC + IOClass + ThinkVPC + IOProbeScore + 200 + IOPropertyMatch + + + name + LEN0268 + + + name + LEN0068 + + + IOProviderClass + IOACPIPlatformDevice + IOUserClientClass + YogaSMCUserClient + Sensors + + Airflow Left + + Airflow Right + + CPU Core PECI + + CPU System Agent Core + TMP0 + Memory Proximity + + Platform Controller Hub Die + ESTA + SO-DIMM 1 Proximity + + SO-DIMM 2 Proximity + + SO-DIMM 3 Proximity + + SO-DIMM 4 Proximity + + + + YogaWMI + + CFBundleIdentifier + org.zhen.YogaSMC + IOClass + YogaWMI + IONameMatch + PNP0C14 + IOProbeScore + 100 + IOProviderClass + IOACPIPlatformDevice + + + LSMinimumSystemVersion + 10.12 + NSHumanReadableCopyright + Copyright © 2020 Zhen. All rights reserved. + OSBundleLibraries + + as.vit9696.Lilu + 1.4.5 + as.vit9696.VirtualSMC + 1.1.4 + com.apple.iokit.IOACPIFamily + 1.0.0d1 + com.apple.kpi.bsd + 8.0.0 + com.apple.kpi.iokit + 8.0.0 + com.apple.kpi.libkern + 8.0.0 + com.apple.kpi.mach + 8.0.0 + com.apple.kpi.unsupported + 8.0.0 + + + diff --git a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC new file mode 100644 index 0000000..c8aea93 Binary files /dev/null and b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/MacOS/YogaSMC differ diff --git a/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/_CodeSignature/CodeResources b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/_CodeSignature/CodeResources new file mode 100644 index 0000000..d5d0fd7 --- /dev/null +++ b/EFI-OpenCore/EFI/OC/Kexts/YogaSMC.kext/Contents/_CodeSignature/CodeResources @@ -0,0 +1,115 @@ + + + + + files + + files2 + + rules + + ^Resources/ + + ^Resources/.*\.lproj/ + + optional + + weight + 1000 + + ^Resources/.*\.lproj/locversion.plist$ + + omit + + weight + 1100 + + ^Resources/Base\.lproj/ + + weight + 1010 + + ^version.plist$ + + + rules2 + + .*\.dSYM($|/) + + weight + 11 + + ^(.*/)?\.DS_Store$ + + omit + + weight + 2000 + + ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ + + nested + + weight + 10 + + ^.* + + ^Info\.plist$ + + omit + + weight + 20 + + ^PkgInfo$ + + omit + + weight + 20 + + ^Resources/ + + weight + 20 + + ^Resources/.*\.lproj/ + + optional + + weight + 1000 + + ^Resources/.*\.lproj/locversion.plist$ + + omit + + weight + 1100 + + ^Resources/Base\.lproj/ + + weight + 1010 + + ^[^/]+$ + + nested + + weight + 10 + + ^embedded\.provisionprofile$ + + weight + 20 + + ^version\.plist$ + + weight + 20 + + + + diff --git a/EFI-OpenCore/EFI/OC/OpenCore.efi b/EFI-OpenCore/EFI/OC/OpenCore.efi index 1d7f18a..91ea05a 100644 Binary files a/EFI-OpenCore/EFI/OC/OpenCore.efi and b/EFI-OpenCore/EFI/OC/OpenCore.efi differ diff --git a/EFI-OpenCore/EFI/OC/config.plist b/EFI-OpenCore/EFI/OC/config.plist index 976234c..09c94a4 100755 --- a/EFI-OpenCore/EFI/OC/config.plist +++ b/EFI-OpenCore/EFI/OC/config.plist @@ -8,11 +8,35 @@ Comment - Battery (Needs TPbattery.plist) + Detect Darwin for other patches Enabled Path - SSDT-OCBAT0-TP_tx80_x1c6th.aml + SSDT-Darwin.aml + + + Comment + Initialize system variables + Enabled + + Path + SSDT-INIT.aml + + + Comment + Patch Battery + Enabled + + Path + SSDT-Battery.aml + + + Comment + Battery: fix access to 16byte-EC-field HWAC: depends on / patches/ OpenCore Patches/ HWAC.plist + Enabled + + Path + SSDT-HWAC.aml Comment @@ -20,15 +44,31 @@ Enabled Path - SSDT-PLUG-_PR.PR00.aml + SSDT-PLUG.aml Comment - Brightness Adjustment + Embedded Controller (EC): depends on YogaSMC.kext Enabled Path - SSDT-PNLF-SKL_KBL.aml + SSDT-EC.aml + + + Comment + S3 Sleep: depends on / patches/ OpenCore Patches/ Sleep.plist + Enabled + + Path + SSDT-Sleep.aml + + + Comment + Smooth Brightness Adjustment: depends on AppleBacklightSmoother.kext + Enabled + + Path + SSDT-PNLF.aml Comment @@ -40,7 +80,7 @@ Comment - Thinkpad Keyboard (Need x1c6-keyboard.plist) + Keyboard : depends on / patches/ OpenCore Patches/ Keyboard.plist Enabled Path @@ -48,39 +88,7 @@ Comment - Comprehensive Sleep/ Wake Patch (Needs PTSWAK.plist) - Enabled - - Path - SSDT-PTSWAK.aml - - - Comment - Fix Reboot after Shutdown - Enabled - - Path - SSDT-EXT1-FixShutdown.aml - - - Comment - TP Light Sleep/Wake Fix - Enabled - - Path - SSDT-LED.aml - - - Comment - PTSWAK EXT4 - Enabled - - Path - SSDT-EXT4-WakeScreen.aml - - - Comment - Fake DMAC (Completeness) + Fake DMAC (Fix up memory controller) Enabled Path @@ -104,27 +112,35 @@ Comment - TB3 Hotplug Support + Thunderbolt 3: depends on / patches/ OpenCore Patches/ Thunderbolt3.plist Enabled Path - SSDT-DTPG.aml + SSDT-TB3.aml Comment - TB3 Hotplug + USB 3.1 Enabled Path - SSDT-Z390-TB3HP.aml + SSDT-XHC2.aml Comment - HPET _CRS (Needs HPET.plist) + USB 2.0/3.0: depends on / patches/ OpenCore Patches/ XHC1.plist Enabled Path - SSDT-HPET.aml + SSDT-XHC1.aml + + + Comment + Patch USB Power + Enabled + + Path + SSDT-USBX.aml Delete @@ -133,14 +149,14 @@ Comment - HPET _CRS to XCRS Rename + Battery: Change HWAC to XWAC EC reads Count 0 Enabled Find - X0NSUwig + RUNfX0hXQUM= Limit 0 @@ -149,11 +165,10 @@ OemTableId - AAAAAA== Replace - WENSUwig + RUNfX1hXQUM= ReplaceMask @@ -164,19 +179,19 @@ 0 TableSignature - AAAAAA== + RFNEVA== Comment - RTC IRQ 8 Patch + S3 Sleep: GRPW to ZRPW Count 0 Enabled Find - IgABeQA= + BkdQUlcCcA== Limit 0 @@ -185,11 +200,10 @@ OemTableId - AAAAAA== Replace - IgAAeQA= + BlpQUlcCcA== ReplaceMask @@ -200,283 +214,18 @@ 0 TableSignature - AAAAAA== + RFNEVA== Comment - TIMR IRQ 0 Patch + S3 Sleep: _WAK to ZWAK(1,S) Count 0 Enabled Find - IgEAeQA= - - Limit - 0 - Mask - - - OemTableId - - AAAAAA== - - Replace - - IgAAeQA= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - AAAAAA== - - - - Comment - Name6D-03 to 00 - Count - 0 - Enabled - - Find - - Cm0KAw== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - Cm0KAA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - Name6D-04 to 00 - Count - 0 - Enabled - - Find - - Cm0KBA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - Cm0KAA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - TP-BAT:GBIF03 to XBIF03 - Count - 0 - Enabled - - Find - - R0JJRgM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJJRgM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:GBIX03 to XBIX03 - Count - 0 - Enabled - - Find - - R0JJWAM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJJWAM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:GBST04 to XBST04 - Count - 0 - Enabled - - Find - - R0JTVAQ= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEJTVAQ= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - - - Comment - TP-BAT:AJTP03 to XJTP03 - Count - 0 - Enabled - - Find - - QUpUUAM= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEpUUAM= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _PTS to ZPTS(1,N) - Count - 1 - Enabled - - Find - - X1BUUwE= - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WlBUUwE= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _WAK to ZWAK(1,S) - Count - 1 - Enabled - - Find - X1dBSwk= Limit @@ -500,18 +249,19 @@ 0 TableSignature + RFNEVA== Comment - _Q6A to XQ6A (F4 - Microphone Mute) + XHC1: Notify(XHC_, 0x02) to XHC1 Count - 1 + 0 Enabled Find - X1E2QQ== + hlhIQ18K Limit 0 @@ -523,7 +273,7 @@ Replace - WFE2QQ== + hlhIQzEK ReplaceMask @@ -534,18 +284,19 @@ 0 TableSignature + RFNEVA== Comment - _Q15 to XQ15 (F5 - Brightness Down) + Thunderbolt 3: _L27 to XL27 Count - 1 + 0 Enabled Find - X1ExNQ== + X0wyNw== Limit 0 @@ -557,7 +308,7 @@ Replace - WFExNQ== + WEwyNw== ReplaceMask @@ -568,18 +319,19 @@ 0 TableSignature + RFNEVA== Comment - _Q14 to XQ14 (F6 - Brightness Up) + Thunderbolt 3: RP09:_PS0 to RP09:XPS0 Count 1 Enabled Find - X1ExNA== + X1BTMA== Limit 0 @@ -588,10 +340,11 @@ OemTableId + UlZQN1J0ZDM= Replace - WFExNA== + WFBTMA== ReplaceMask @@ -599,21 +352,22 @@ Skip 0 TableLength - 0 + 7453 TableSignature + U1NEVA== Comment - _Q16 to XQ16 (F7 - Dual Display) + Thunderbolt 3: RP09:_PS3 to RP09:XPS3 Count 1 Enabled Find - X1ExNg== + X1BTMw== Limit 0 @@ -622,10 +376,11 @@ OemTableId + UlZQN1J0ZDM= Replace - WFExNg== + WFBTMw== ReplaceMask @@ -633,258 +388,21 @@ Skip 0 TableLength - 0 + 7453 TableSignature + U1NEVA== Comment - _Q64 to XQ64 (F8 - Network) + Thunderbolt 3: _L6F to XL6F (Thunderbolt 3 Hotplug GPE) Count - 1 + 0 Enabled Find - X1E2NA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2NA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q66 to XQ66 (F9 - Settings) - Count - 1 - Enabled - - Find - - X1E2Ng== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2Ng== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q60 to XQ60 (F10 - Bluetooth) - Count - 1 - Enabled - - Find - - X1E2MA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2MA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q61 to XQ61 (F11 - Keyboard) - Count - 1 - Enabled - - Find - - X1E2MQ== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2MQ== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q62 to XQ62 (F12 - Star) - Count - 1 - Enabled - - Find - - X1E2Mg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE2Mg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q1F to XQ1F (Keyboard backlight - Fn + Space) - Count - 1 - Enabled - - Find - - X1ExRg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFExRg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _Q74 to XQ74 (FnLock - Fn + Esc) - Count - 1 - Enabled - - Find - - X1E3NA== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WFE3NA== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - _L6F to XL6F (Thunderbolt 3 Hotplug GPE) - Count - 0 - Enabled - - Find - X0w2Rg== Limit @@ -912,7 +430,7 @@ Comment - RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) + Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) Count 1 Enabled @@ -944,6 +462,41 @@ + + Comment + Thunderbolt 3: _PTS to ZPTS(1,N) + Count + 0 + Enabled + + Find + + X1BUUwE= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WlBUUwE= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + Quirks @@ -1005,12 +558,39 @@ Add + PciRoot(0x0)/Pci(0x1D,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0) + + ThunderboltUUID + + bYT/DabNYl2Vq0VgT/Xr3w== + + built-in + + AA== + + device_type + Thunderbolt 3 Controller + linkDetails + + CAAAAAMAAAA= + + model + JHL6540 Thunderbolt 3 NHI (C step) [Alpine Ridge 4C 2016] + PciRoot(0x0)/Pci(0x1f,0x3) + AAPL,slot-name + Internal@0,31,3 + device_type + Audio device + hda-gfx + onboard-1 layout-id FQAAAA== + model + Sunrise Point-LP HD Audio PciRoot(0x0)/Pci(0x2,0x0) @@ -1052,10 +632,12 @@ Add + Arch + x86_64 BundlePath Lilu.kext Comment - + Patch engine Enabled ExecutablePath @@ -1068,10 +650,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath VirtualSMC.kext Comment - + SMC emulator Enabled ExecutablePath @@ -1084,6 +668,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath SMCBatteryManager.kext Comment @@ -1100,6 +686,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath SMCProcessor.kext Comment @@ -1116,6 +704,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath SMCLightSensor.kext Comment @@ -1132,10 +722,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath WhateverGreen.kext Comment - Video card + Video patches Enabled ExecutablePath @@ -1148,10 +740,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath AppleALC.kext Comment - Sound + Audio patches Enabled ExecutablePath @@ -1164,6 +758,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath IntelMausi.kext Comment @@ -1180,22 +776,8 @@ Contents/Info.plist - BundlePath - USBPorts.kext - Comment - USB Ports - Enabled - - ExecutablePath - - MaxKernel - - MinKernel - - PlistPath - Contents/Info.plist - - + Arch + x86_64 BundlePath VoodooSMBus.kext Comment @@ -1212,6 +794,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooRMI.kext/Contents/PlugIns/VoodooInput.kext Comment @@ -1228,6 +812,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooRMI.kext Comment @@ -1244,6 +830,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooRMI.kext/Contents/PlugIns/RMISMBus.kext Comment @@ -1260,6 +848,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooRMI.kext/Contents/PlugIns/VoodooTrackpoint.kext Comment @@ -1276,6 +866,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooRMI.kext/Contents/PlugIns/RMII2C.kext Comment @@ -1292,6 +884,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooPS2Controller.kext/Contents/Plugins/VoodooInput.kext Comment @@ -1308,6 +902,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooPS2Controller.kext Comment @@ -1324,6 +920,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooPS2Controller.kext/Contents/Plugins/VoodooPS2Mouse.kext Comment @@ -1340,6 +938,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooPS2Controller.kext/Contents/Plugins/VoodooPS2Trackpad.kext Comment @@ -1356,6 +956,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath VoodooPS2Controller.kext/Contents/Plugins/VoodooPS2Keyboard.kext Comment @@ -1372,6 +974,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath CPUFriend.kext Comment @@ -1388,6 +992,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath CPUFriendDataProvider.kext Comment @@ -1404,10 +1010,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath HibernationFixup.kext Comment - + For support of Hibernation Mode 25 Enabled ExecutablePath @@ -1420,10 +1028,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath NVMeFix.kext Comment - + Improve macOS compatibility of non-Apple SSDs Enabled ExecutablePath @@ -1436,6 +1046,8 @@ Contents/Info.plist + Arch + x86_64 BundlePath ThunderboltReset.kext Comment @@ -1452,10 +1064,12 @@ Contents/Info.plist + Arch + x86_64 BundlePath RTCMemoryFixup.kext Comment - + For support of Hibernation Mode 25 Enabled ExecutablePath @@ -1467,6 +1081,60 @@ PlistPath Contents/Info.plist + + Arch + x86_64 + BundlePath + AppleBacklightSmoother.kext + Comment + For smoother backlight adjustments (Need SSDT-PNLF) + Enabled + + ExecutablePath + Contents/MacOS/AppleBacklightSmoother + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + + + Arch + x86_64 + BundlePath + YogaSMC.kext + Comment + System Management Controller (SMC) Driver + Enabled + + ExecutablePath + Contents/MacOS/YogaSMC + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + + + Arch + x86_64 + BundlePath + BrightnessKeys.kext + Comment + Dynamic handling of Fn keys without ACPI renames + Enabled + + ExecutablePath + Contents/MacOS/BrightnessKeys + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + Block @@ -1503,6 +1171,8 @@ DisableRtcChecksum + ExtendBTFeatureFlags + ExternalDiskIcons IncreasePciBarSize @@ -1530,7 +1200,7 @@ ConsoleAttributes 0 HibernateMode - Auto + NVRAM HideAuxiliary PickerAudioAssist @@ -1602,6 +1272,12 @@ Ag== + 4D1FDA02-38C7-4A6A-9CC6-4BCCA8B30102 + + rtc-blacklist + + + 7C436110-AB2A-4BBB-A880-FE41995C9F82 SystemAudioVolume @@ -1624,6 +1300,10 @@ UIScale + 4D1FDA02-38C7-4A6A-9CC6-4BCCA8B30102 + + rtc-blacklist + 7C436110-AB2A-4BBB-A880-FE41995C9F82 boot-args @@ -1759,6 +1439,8 @@ DirectGopRendering + ForceResolution + IgnoreTextInGraphics ProvideConsoleGop diff --git a/EFI-OpenCore/EFI/OC/config_unmoddedBIOS.plist b/EFI-OpenCore/EFI/OC/config_unmoddedBIOS.plist index 8bb438c..2b92200 100644 --- a/EFI-OpenCore/EFI/OC/config_unmoddedBIOS.plist +++ b/EFI-OpenCore/EFI/OC/config_unmoddedBIOS.plist @@ -9,96 +9,11 @@ PciRoot(0x0)/Pci(0x2,0x0) framebuffer-fbmem - - AACQAA== - + AACQAA== framebuffer-stolenmem - - AAAwAQ== - + AAAwAQ== - Kernel - - Patch - - - Base - - Comment - KBL-DVMTpatch-10.15-10.15.1-10.15.2-10.15.3 (Enable 4K UHD HDMI/DisplayPort Output) - Count - 0 - Enabled - - Find - - D4KnAwAA - - Identifier - com.apple.driver.AppleIntelKBLGraphicsFramebuffer - Limit - 0 - Mask - - - MaxKernel - 19.3.0 - MinKernel - - Replace - - D4IAAAAA - - ReplaceMask - - - Skip - 0 - - - Base - - Comment - KBL-DVMTpatch-10.15.4 (Enable 4K UHD HDMI/DisplayPort Output) - Count - 0 - Enabled - - Find - - D4KPAwAA - - Identifier - com.apple.driver.AppleIntelKBLGraphicsFramebuffer - Limit - 0 - Mask - - - MaxKernel - - MinKernel - 19.4.0 - Replace - - D4IAAAAA - - ReplaceMask - - - Skip - 0 - - - - UEFI - - Drivers - - TbtForcePower.efi - - diff --git a/EFI-OpenCore/README.md b/EFI-OpenCore/README.md index 8d32509..e34951a 100644 --- a/EFI-OpenCore/README.md +++ b/EFI-OpenCore/README.md @@ -2,11 +2,7 @@ Critter -## OpenCore is better than Clover in [many ways](https://khronokernel-2.gitbook.io/opencore-vanilla-desktop-guide/). But since it is still in its infancy, OpenCore still requires a lot of time and personal confgurations to work. So even though I have posted my EFI-OpenCore folder, there are still some work which you have to do before you are able to get it working on your machine. - -### Fortunately, [acidanthera](https://github.com/acidanthera) has done a great job documenting OpenCore. And while it can be greatly time consuming, I really recommend taking a look at it and starting a `config.plist` from scratch. Doing so will allow you to personalize and understand OpenCore configurations. More importantly, by starting an `config.plist` from scratch, you may catch a mistake in my own config.plist or find a better setting variable. - -I do, however, understand if you are strapped for time. So here are the necessary changes to my uploaded configs that would get your machine working. In most cases, your machine should boot with OpenCore after these changes. However, if it does not. please refer to acidanthera's OpenCore documentation. +## Even though I have posted my OpenCore EFI folder here, there are still some work which you have to do before you are able to get it working on your machine. It is **NEVER** a good idea to use someone else's EFI without throughly examining it. ``` * SystemUUID: Can be generated with MacSerial or use pervious from Clover's config.plist. @@ -15,9 +11,8 @@ I do, however, understand if you are strapped for time. So here are the necessar * SystemSerialNumber: Can be generated with MacSerial or use pervious from Clover's config.plist. ``` -See [`docs/5_README-other`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/5_README-other.md) for more details regarding PlatformInfo settings. - -`CPUFriendDataProvider` can be generated with [CPUFriendFriend](https://github.com/corpnewt/CPUFriendFriend_) or [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). This is especially important if you have a different CPU than mine. Even if you have the same CPU as me, you may prefer a different Energy Performance Preference (EPP) so do generate your own CPUFriendDataProvider. +- See [`docs/3_README-other`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md) for more details regarding PlatformInfo settings. +- `CPUFriendDataProvider` can be generated with [CPUFriendFriend](https://github.com/corpnewt/CPUFriendFriend_) or [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). This is especially important if you have a different CPU than mine. Even if you have the same CPU as me, you may prefer a different Energy Performance Preference (EPP) so do generate your own CPUFriendDataProvider. > ## Checking your OpenCore config.plist @@ -25,7 +20,7 @@ It is important to keep your OpenCore config.plist properly up-to-spec, as OpenC > ## `config.plist` Comments: * There are two `plist` files. Default `config.plist` is meant who those with a modded BIOS and have made the approiate settings as detailed in [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) while `config_unmoddedBIOS.plist` is meant for those without a modded BIOS. If you have a modded BIOS and have made the adjustments detailed in my docs, `config.plist` should suffice. If your BIOS is unmodded, simply add the contents of `config_unmoddedBIOS.plist` to the main `config.plist`. -* Notes on kexts and ACPI patches are on the respective Add OpenCore entry. Additionally, notes on ACPI patches can be found at [docs/4_README-ACPIpatching.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-ACPIpatching.md). +* Notes on kexts and ACPI patches are on the respective OpenCore entries. Additionally, notes on ACPI patches can be found in [docs/2_README-ACPIpatching.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/2_README-ACPIpatching.md) as well as comments inside the patch. * Audio patches: `Device Properties` > `PciRoot(0x0)/Pci(0x1f,0x3)` > `layout-id`: Injects AppleALC layout-id `21` * Intel iGPU and HDMI patches: @@ -37,7 +32,6 @@ It is important to keep your OpenCore config.plist properly up-to-spec, as OpenC * `framebuffer-con1-type` to set connector 1 type to HDMI (per IOReg) * `framebuffer-patch-enable` tells WEG to patch framebuffer. * `AAPL00,override-no-connect` to override EDID (dependent on display models). See `patches/Internal Displays/`. This is necessary to fix HDMI hotplug. To create your own, see [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) - * Addtionally, `config_unmoddedBIOS.plist` constains two more variables meant to work around the stock BIOS DVMT `Pre-Allocated` being locked at `32M`. * FileVault compatibility: * Misc -> Boot * `PollAppleHotKeys` set to `YES`(While not needed can be helpful) @@ -54,9 +48,21 @@ It is important to keep your OpenCore config.plist properly up-to-spec, as OpenC * `AppleSmcIo` set to `YES`(this replaces VirtualSMC.efi) * UEFI -> Quirks * `RequestBootVarRouting` set to `YES` +* Hibernation Mode 25 support: + * Booter -> Quirks + * `DiscardHibernateMap` set to `YES` + * NVRAM -> Add -> 7C436110-AB2A-4BBB-A880-FE41995C9F82 + * `boot-args` includes `-hbfx-dump-nvram rtcfx_exclude=80-AB` + * Misc -> Boot + * `HibernateMode` set to `NVRAM` + * UEFI -> ReservedMemory + * Address: `569344` + * Size: `4096` + * Type: `RuntimeCode` * Personalization: - * `ShowPicker` is `NO`. Use `Esc` during boot to show picker when needed. + * `ShowPicker` is `No`. Use `Esc` during boot to show picker when needed. * `PickerMode` is `External` to use `OpenCanopy` boot menu. If you prefer a lighter `EFI`, delete `Resources` and switch variable to `Builtin`. + * `PlayChime` is `No`. Set this to `Yes` if you want the native chime to play upon boot. * OpenCanopy Support: I prefer OpenCanopy for its looks. However, it is completely optional and can take up space in your EFI. If you would rather use OpenCore's built in picker. Change `PickerMode` to `Builtin` and remove `OpenCanopy.efi` from `UEFI` > `Drivers`. diff --git a/EFI-install_USB/EFI/OC/Drivers/OpenCanopy.efi b/EFI-install_USB/EFI/OC/Drivers/OpenCanopy.efi index db302de..200b90a 100644 Binary files a/EFI-install_USB/EFI/OC/Drivers/OpenCanopy.efi and b/EFI-install_USB/EFI/OC/Drivers/OpenCanopy.efi differ diff --git a/EFI-install_USB/EFI/OC/Drivers/OpenRuntime.efi b/EFI-install_USB/EFI/OC/Drivers/OpenRuntime.efi index 11158ab..42cfc13 100644 Binary files a/EFI-install_USB/EFI/OC/Drivers/OpenRuntime.efi and b/EFI-install_USB/EFI/OC/Drivers/OpenRuntime.efi differ diff --git a/EFI-install_USB/EFI/OC/OpenCore.efi b/EFI-install_USB/EFI/OC/OpenCore.efi index 1d7f18a..91ea05a 100644 Binary files a/EFI-install_USB/EFI/OC/OpenCore.efi and b/EFI-install_USB/EFI/OC/OpenCore.efi differ diff --git a/EFI-install_USB/EFI/OC/config.plist b/EFI-install_USB/EFI/OC/config.plist index 3289a72..1cd062d 100755 --- a/EFI-install_USB/EFI/OC/config.plist +++ b/EFI-install_USB/EFI/OC/config.plist @@ -573,6 +573,8 @@ DirectGopRendering + ForceResolution + IgnoreTextInGraphics ProvideConsoleGop diff --git a/README.md b/README.md index 3c126f3..f97b0d4 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ [![version](https://img.shields.io/badge/10.15.7-yellow)](https://support.apple.com/en-us/HT210642) [![BIOS](https://img.shields.io/badge/BIOS-1.45-blue)](https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x1-carbon-6th-gen-type-20kh-20kg/downloads/driver-list/component?name=BIOS%2FUEFI) [![MODEL](https://img.shields.io/badge/Model-20KH*-blue)](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) -[![OpenCore](https://img.shields.io/badge/OpenCore-0.6.2-green)](https://github.com/acidanthera/OpenCorePkg) +[![OpenCore](https://img.shields.io/badge/OpenCore-0.6.3-green)](https://github.com/acidanthera/OpenCorePkg) [![LICENSE](https://img.shields.io/badge/license-MIT-green.svg)](https://github.com/996icu/996.ICU/blob/master/LICENSE) Critter @@ -12,7 +12,7 @@ ### Check out my blog [tylerspaper.com](https://tylerspaper.com/) #### READ THE ENTIRE README.MD BEFORE YOU START. -() + #### I am not responsible for any damages you may cause. ### Should you find an error, or improve anything, be it in the config itself or in the my documentation, please consider opening an issue or a pull request to contribute. @@ -25,66 +25,127 @@ ##### Recent | [Changelog Archive](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/CHANGELOG.md) -> ### 2020-10-6 - -#### Notice - -- Just getting back to my rountine and maintaining this project. There has been many developments lately, especially with Thunderbolt 3 ACPI patches and [YogaSMC](https://github.com/zhen-zen/YogaSMC). It will take some time for me to review all these developments and understand them. Meanwhile, it seems @benbender has taken matters to his own hand while I was away :) -- His experimental fork: https://github.com/benbender/x1c6-hackintosh -- I will create an issue to specfically to discuss YogaSMC usage and config on this machine. -- Looking forward, Big Sur is almost here so I want to get this project back onto the latest stable build before it comes out. +> ### 2020-11-3 #### Changed -- Support for Hibernation Mode 25. As with normal macOS machines, mode 3 is default, but if you want, mode 25 is now also an option. -- There seems to be a bug with the GitHub release version of `ThunderboltReset.kext` so I replaced it one built by @benbender. You can monitor the issue here [osy86/ThunderboltReset/issues/7](https://github.com/osy86/ThunderboltReset/issues/7). Thank you @benbender for noticing this. -- OC to 0.6.2 -- Upgraded various Acidanthera kexts as well as `VoodooRMI` +- OC to 0.6.3 and upgrade various Acidanthera kexts +- Restructured docs: depricated legacy things and combined duplicates. +- `YogaSMC` is now the preferred method to handle Fn keys instead of ThinkpadAssisstant. + - Note that `YogaSMC` is still in its infancy, so you still prefer ThinkpadAssistant, use `SSDT-Keyboard-Legacy.dsl` and `/patches/OpenCore Patches/ Keyboard-Legacy.plist` + - Thank you @zhen-zen for the great kext and app. +- Updated `config.plsit`: + - Removed depricated ACPI renames in accordance with new ACPI patches. + - Added `Arch` value to each kext entry in accordance with new OpenCore doc. + - Added Thunderbolt 3 Device Properties. + - Added `ExtendBTFeatureFlags` value to replace `BT4LEContinuityFixup` +- Reorganized subdirectories within `/patches/` to make things easier to find and understand. +- Renamed `3_README-POSTinstallation.md` to `SUMMARY.md` since it's not really a step but more of an overview of what patches what. +- More readble and better writing of `SSDT-Keyboard` +- New `SSDT-PNLF` to accomodate `AppleBacklightSmoother.kext` +- New battery patch `SSDT-Battery` that fixes accesses to 16byte-EC-field HWAC (Issue #82). +- `SSDT-Sleep` is an all-in-one sleep patch over `SSDT-PTSWAK`, `SSDT-GPRW`, `SSDT-EXT*` + - It is no longer necessary to set sleep mode to `Linux` in BIOS as it is now indepently set by `SSDT-Sleep` +- `If (_OSI ("Darwin"))` and `SSDT-DTPG` are now replaced in favor of `SSDT-Darwin` and `OSDW`, just like in genuine Macs. +- Removed `USBPorts.kext` in favor of patching/mapping via ACPI with `SSDT-XHC1`, `SSDT-XHC2`, and `SSDT-USBX` +- `README.md`: + - Turned different sections into menus for better readability. + - Merged `3_README-POSTinstallation.md` into the `SUMMARY` section. +- Set `HibernateMode` to `NVRAM` instead of `Auto` #### Added -- Added `RTCMemoryFixUp` for support of Hibernation Mode 25. -- OpenCore config patch for FHD Touchscreen. -- OpenCore config patch for Intel wireless. +- `update.sh` script to automatically build and replace all ACPI patches +- `SSDT-HWAC` to patch access to 16byte-EC-field HWAC +- `SSDT-EC` to patch embedded controller for use with `YogaSMC` +- `SSDT-Debug`, `SSDT-HOOKS`, and `Debug.plist` for debugging if needed +- `SSDT-INIT` to configure system values: `HPET`, `DYTC`, and `DPTF` +- `YogaSMC.kext` to interface with the device's EC. Make sure to also install the [app and pref pane](https://github.com/zhen-zen/YogaSMC/releases). +- `AppleBacklightSmoother.kext` is just as its name implies. +- `BrightnessKeys.kext` to handle Fn keys with ACPI renames. +- Documentation of modding the Thunderbolt 3 controller. #### Removed -- ALCPlugFix is now deprecated and is replaced by new AppleALC (per issue #75). Please run `uninstall.sh` from the previous commit to remove ALCPlugFix. -- Delete legacy DiskImage voice from OC `Resources` -- `GPRW` ACPI patch to fix Bluetooth wake. Make sure that your Wake-on-LAN is disabled in BIOS to prevent sleep problems. -- Removed advice to disable DPTF in modded BIOS as it can break methods in ACPI. Thanks @benbender -- `SMCSuperIO` as it was unnecessary. +- `SSDT-HPET`, similar to genuine Macs, HPET is now disabled within `SSDT-INIT` -> # table of contents - - [summary](#summary) - - [before you start](#references) - - [needed](#needed) - - [my specs for comparison and ref](#specifications) - - [getting started ](#start) - - [other x1c6 repos](#other) - - [contact](#contact) - - [donate and support](#support) - - [credits and thank you](#credits) +#### Remark +- A large of these changes are due to the hardwork of [@benbender](https://github.com/benbender), who debugged and authored many of the new ACPI patches. Thank you for your hard work! -> ## SUMMARY +
+ SUMMARY +
-**`In short, x1c6-hackintosh is very stable and is currently my daily driver. I fully recommend this project to anyone looking for a MacBook alternative.`** +> ### Non-Fuctional: +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Fingerprint Reader | ❌ | `DISABLED` in BIOS to save power if not used in other OSes. | Linux support was only recently added | +| Wireless WAN | ❌ | `DISABLED` in BIOS to save power if not used in other OSes. | Unable to investigate as I have no need and my model did not come with WWAN. | -| Fully functional | Non-functional | Semi-functional. Additional pulls needed and welcomed. | -| ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------ | -------------------------------------------------------------------------------------------------------------------------------------------- | -| Native Power Mangemenet ✅ \*need BIOS mod, see [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) | Wireless WAN ❌ (DISABLED at BIOS) | Thunderbolt 3 hotplug *with some caveats. See [docs/5_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/5_README-other.md) and [Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) ⚠️ | -| WiFi, Bluetooth, Apple Continuity, iCloud suite: App Store, iMessage, FaceTime, iCloud Drive, etc... ✅ \*need [network card replacement](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) | Fingerprint Reader ❌ (not needed, DISABLED at BIOS) | | -| USB A, USB C, Webcam, Audio Playback/Recording Sleep, Ethernet, Intel Graphics, TrackPoint and Trackpad, MicroSD card reader ✅ | | | -| BIOS Mod, giving access to `Advance` menu.✅ See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) and [Issue #68](https://github.com/tylernguyen/x1c6-hackintosh/issues/68) | | | -| Multimedia Fn keys ✅ \*need [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) | | | -| PM981 installation. ✅ See [Issue #43](https://github.com/tylernguyen/x1c6-hackintosh/issues/43) | | | -| 4K UHD via HDMI/DisplayPort. ✅ Install `patches/OpenCore patches/4K-Output.plist` if your BIOS is unmodded (follow [Issue #40](https://github.com/tylernguyen/x1c6-hackintosh/issues/40#issuecomment-659370165) when upgrading macOS with this patch enabled). If you have a modded BIOS, simply set `DMVT Pre-Allocated` to `64M` (Refer to [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md))| | | -| HDMI hotplug(requires a custom EDID override). ✅ See `patches/Internal Displays/` for pre-made ones and [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) if one does not exist already for your display.| | -| Hibernation Mode 25 ✅|| +> ### Video and Audio +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Full Graphics Accleration (QE/CI) | ✅ | `WhateverGreen.kext` | - | +| Audio Recording | ✅ | `AppleALC.kext` with Layout ID = 21 | - | +| Audio Playback | ✅ | `AppleALC.kext` with Layout ID = 21 | - | +| Automatic Headphone Output Switching | ✅ | `AppleALC.kext` with Layout ID = 21 | - | -**For more information regarding certain features, please refer to [`docs/3_README-POSTinstallation.md`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-POSTinstallation.md)** +> ### Power, Charge, Sleep and Hibernation +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Battery Percentage Indication | ✅ | `SSDT-Battery.aml` and `/patches/OpenCore Patches/Battery.plist` | +| CPU Power Management (SpeedShift) | ✅ | `XCPM` and `CPUFriend.kext`, generate your own `CPUFriendDataProvider` with [CPUFriendFriend](https://github.com/corpnewt/CPUFriendFriend_) or [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). | +| iGPU Power Management | ✅ | `XCPM`, enabled by `SSDT-PLUG.aml` | +| NVMe Drive Battery Management | ✅ | `NVMeFix.kext` | In my experience, NVMe drives will drain more power than SATA drives. | +| S3 Sleep/ Hibernation Mode 3 | ✅ | `SSDT-Sleep.aml` | | +| Hibernation Mode 25 | ✅ | `RTCMemoryFixup.kext` and `HibernationFixup.kext` | Supported, macOS uses mode 3 by default. Change to mode 25 via `pmset`. | +| Custom Charge Threshold | ✅ | `SSDT-EC.aml`, [YogaSMC.kext](https://github.com/zhen-zen/YogaSMC), and [YogaSMCPane](https://github.com/zhen-zen/YogaSMC)| Adjust with YogaSMCPane in System Preferences +| Battery Life | ✅ | Native, comparable to Windows/Linux. Biggest impact is TB3, see [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) | Will need a modded BIOS to disable `CFG Lock` + +> ### Input/ Output +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| WiFi | ✅ | Native with BCM94360CS2. See `/patches/ Network Patches/` otherwise. | See `/patches/OpenCore Patches/` for specific network card. | +| Bluetooth | ✅ | Native with BCM94360CS2. See `/patches/ Network Patches/` otherwise. | See `/patches/Network Patches/` for specific network card. | +| Ethernet | ✅ | `IntelMausi.kext` | Needs Lenovo Ethernet adapter: [Item page](https://www.lenovo.com/us/en/accessories-and-monitors/cables-and-adapters/adapters/CABLE-BO-Ethernet-Extension-Adapter-2/p/4X90Q84427) | +| HDMI hotplug | ✅ | Custom EDID Override `/patches/Internal Displays/` | Refer to [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) if one does not exist already for your display. | +| 4K UHD output via HDMI/ DisplayPort **(Modded BIOS)** | ✅ | See `DMVT Pre-Allocated` to `64M` | See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) for information about modding the BIOS. | +| 4K UHD output via HDMI/ DisplayPort **(Vanilla BIOS)** | ✅ | See `/patches/OpenCore Patches/4K-Output-wo-BIOSmod.plist` | - | +| USB 2.0, USB 3.0, and Micro SD Card Reader | ✅ | `SSDT-XHC1.aml` | - | +| USB 3.1 | ⚠️ | `SSDT-XHC2.aml` | - | +| USB Power Properties in macOS | ✅ | `SSDT-USBX.aml` | - | +| Thunderbolt 3 **(Cold Boot)** | ✅ | `SSDT-TB3.aml`, | TB3 device must be plugged in before boot. | +| Thunderbolt 3 Hotplug **(Modded Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md), [Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | +| Thunderbolt 3 Hotplug **(Modded Controller and Vanilla BIOS)** | ⚠️ | `SSDT-TB3.aml` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | +| Thunderbolt 3 Hotplug **(Vanilla Controller and Modded BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext`, `GPIO3 Force Pwr` and `GPIO3 Force Pwr for PR05` checked in BIOS | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | +| Thunderbolt 3 Hotplug **(Vanilla Controller and BIOS)** | ⚠️ | `SSDT-TB3.aml`, `ThunderboltReset.kext`, and `TbtForcePower.efi` | [3_README-other.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md),[Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) | + +> ### Display, TrackPad, TrackPoint, and Keyboard +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| Brightness Adjustments | ✅ | `WhateverGreen.kext`, `SSDT-PNLF.aml`, `AppleBacklightSmoother.kext`, and `BrightnessKeys.kext`| `AppleBacklightSmoother.kext` is optional for smoother birghtness adjustments | +| HiDPI _(Optional)_ | ✅ | [xzhih/one-key-hidpi](https://github.com/xzhih/one-key-hidpi) | Scaling issues post-sleep fixed with AAPL, ig-platform `BAAnWQ==` | +| TrackPoint | ✅ | `VoodooPS2Controller.kext` | - | +| TrackPad | ✅ | `VoodooPS2Controller.kext` or `VoodooSMBus.kext` and `VoodooRMI.kext` | I prefer `VoodooRMI.kext` so that is the repository default. | +| Built-in Keyboard | ✅ | `VoodooPS2Controller.kext` | Optimizations recommended, see [`docs/3_README-other.md`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-other.md) | +| Multimedia Keys | ✅ | `BrightnessKeys.kext` and [YogaSMC](https://github.com/zhen-zen/YogaSMC) or [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) with legacy patches | YogaSMC is the repo default, `SSDT-Keyboard-Legacy.aml`, `patches/OpenCore Patches/ Keyboard-Legacy.plist` if you want to use [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) instead | + +> ### macOS Continuity +| Feature | Status | Dependency | Remarks | +| :----------------------------------- | ------ | ------------------- | ---------------------------- | +| iCloud, iMessage, FaceTime | ✅ | Whitelisted Apple ID, Valid SMBIOS | See [dortania /OpenCore-Install-Guide](https://dortania.github.io/OpenCore-Post-Install/universal/iservices.html) | +| Continuty | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. | See `/patches/Network Patches/` for specific network card. | +| AirDrop | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. | See `/patches/Network Patches/` for specific network card. | +| Sidecar | ✅ | Native with `BCM94360CS2`. `ExtendBTFeatureFlags` to `True` otherwise. iPad with >= `iPadOS 13` | Tested with iPad Mini with iPadOS 13.1.2 | +| FileVault | ✅ | as configured in `config.plsit` per [Dortania's Post-Install](https://dortania.github.io/OpenCore-Post-Install/universal/security/filevault.html)| | +| Time Machine | ✅ | Native | TimeMachine only backups your Macintosh partition. Manually backup your EFI partition using another method. | + +
+ +
+ REFERENCES +
-> ## REFERENCES * Read these before you start: - [dortania's Hackintosh guides](https://github.com/dortania) - [dortania's OpenCore Install Guide](https://dortania.github.io/OpenCore-Install-Guide/) @@ -96,64 +157,67 @@ - `Configuration.pdf` and `Differences.pdf` in each `OpenCore` releases. - Additionally, references specific to the x1c6 are located in `docs/references/` -* ### No seriously, please read those. +* ### No seriously, please read those. +
-> ## NEEDED +
+ REQUIREMENTS +
-A macOS machine would be VERY useful: to create install drives, and for when your ThinkPad cannot boot. Though it is not completely necessary. -Flash drive, 12GB or more. -Xcode works fine for editing plist files on macOS, but I prefer [PlistEdit Pro](https://www.fatcatsoftware.com/plisteditpro/). -[ProperTree](https://github.com/corpnewt/ProperTree) if you need to edit plist files on Windows. -[MaciASL](https://github.com/acidanthera/MaciASL), for patching ACPI tables. -[MountEFI](https://github.com/corpnewt/MountEFI) to quickly mount EFI partitions. -[IOJones](https://github.com/acidanthera/IOJones), for diagnosis. -[Hackintool](https://www.insanelymac.com/forum/topic/335018-hackintool-v286/), for diagnostic ONLY, Hackintool should not be used for patching, it is outdated. +- A macOS machine(optional): to create the macOS installer. +- Flash drive, 12GB or more, for the above purpose. +- Xcode works fine for editing plist files on macOS, but I prefer [PlistEdit Pro](https://www.fatcatsoftware.com/plisteditpro/). +- [ProperTree](https://github.com/corpnewt/ProperTree) if you need to edit plist files on Windows. +- [MaciASL](https://github.com/acidanthera/MaciASL), for patching ACPI tables and editing ACPI patches. +- [MountEFI](https://github.com/corpnewt/MountEFI) to quickly mount EFI partitions. +- [IORegistryExplorer](https://developer.apple.com/downloads), for diagnosis. +- [Hackintool](https://www.insanelymac.com/forum/topic/335018-hackintool-v286/), for diagnostic ONLY, Hackintool should not be used for patching, it is outdated. +- [SPI Programmer CH341a and SOIC8 connector](https://www.amazon.com/Organizer-Socket-Adpter-Programmer-CH341A/dp/B07R5LPTYM) are needed if you are going to mod your BIOS/TB3 controller for optimizations and a better and more native macOS experience. +- Patience and time, especially if this is your first time Hackintosh-ing. -> ## SPECIFICATIONS +
-Refer to [x1c6-Platform_Specifications](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) for possible stock ThinkPad X1 6th Gen configurations. +
+ HARDWARE +
+- These are relevant components on my machine which may differ from yours, keep these in mind as you will need to adjust accordingly, depending on your machine's configuration. -| Processor Number | # of Cores | # of Threads | Base Frequency | Max Turbo Frequency | Cache | Memory Types | Graphics | -| :--------------------------------------------------------------------------------------------------------------------------------- | :--------- | :----------- | :------------- | :------------------ | :---- | :----------- | :------------ | -| [i7-8650U](https://ark.intel.com/content/www/us/en/ark/products/124968/intel-core-i7-8650u-processor-8m-cache-up-to-4-20-ghz.html) | 4 | 8 | 1.9 GHz | 4.2 GHz | 8 MB | LPDDR3-2133 | Intel UHD 620 | +| Category | Component | Remarks | +| --------- | ------------------------------------ | ------------ | +| CPU | [i7-8650U](https://ark.intel.com/content/www/us/en/ark/products/124968/intel-core-i7-8650u-processor-8m-cache-up-to-4-20-ghz.html) | Generate your own `CPUFriendDataProvider.kext`. See `SUMMARY` +| SSD | Seagate Firecuda 520 500GB | [Dortania's Anti Hackintosh Buyers Guide](https://dortania.github.io/Anti-Hackintosh-Buyers-Guide/Storage.html) +| Display | 14.0" (355mm) HDR WQHD (2560x1440) | `/patches/ Internal Displays/` and [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) +| WiFi & BT | BCM94360CS2 | `/patches/ Network Patches/` if non-native. +| WWAN | None | Unless needed in other OSes, disable at BIOS to save power -**Peripherals:** +- Refer to [/docs/references/x1c6-Platform_Specifications](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) for possible stock ThinkPad X1 6th Gen configurations. -``` -Two USB 3.1 Gen 1 (Right USB Always On) -Two USB 3.1 Type-C Gen 2 / Thunderbolt 3 (Max 5120x2880 @60Hz) -HDMI 1.4b (Max 4096x2160 @30Hz) -Ethernet via ThinkPad Ethernet Extension Cable Gen 2: I219-LM Ethernet (vPro) -No WWAN -TrackPoint: PS/2 -TrackPad: PS/2 -``` +
-**Display:** -`14.0" (355mm) HDR WQHD (2560x1440)` -**Audio:** -`ALC285 Audio Codec` -**Thunderbolt:** -`Intel JHL6540 (Alpine Ridge 4C) Thunderbolt 3 Bridge` +
+ GETTING STARTED +
-> ## START +Before you do anything, please familiarize yourself with basic Hackintosh terminologies and the basic Hackintosh process by throughly reading Dortania guides as linked in `REFERENCES` -Explore links included this README, especially those in references and other x1c6-hackintosh repos. +- Creating a macOS installer: refer to [Dortania's OpenCore Install Guide](https://dortania.github.io/OpenCore-Install-Guide/installer-guide/) +- [**1_README-HARDWAREandBIOS**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md): Requirements before installing. +- [**2_README-ACPIpatching**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-ACPIpatching.md): Notes and explainations for ACPI hotpatches. +- [**3_README-other.md**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-other.md): for post installation settings and other remarks. -Once you are ready, follow the series of README files included `docs/`. -[**1_README-HARDWAREandBIOS**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md): Requirements before starting. -[**2_README-installMEDIA**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/2_README-installMEDIA.md): Creating the macOS install drive. -[**3_README-POSTinstallation**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-POSTinstallation.md): Settings and tweaks post installation. -[**4_README-ACPIpatching**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-ACPIpatching.md): The hardest and most time consuming part, patching the system ACPI table for battery status, brightness, sleep, thunderbolt, thunderbolt hotplugging, etc... -[**5_README-other.md**](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/5_README-other.md): for other notices +
-- While you can plug-and-play most of my hotpatches if you have an x1c6, I still suggest that you dump and disassemble your own DSDT. This is imprortant as your DSDT maybe different from mine. And furthermore, you get to learn more about what's actually going on. +
+ OTHER REPOSITORIES +
-> ## OTHER - -[zhtengw/EFI-for-X1C6-hackintosh](https://github.com/zhtengw/EFI-for-X1C6-hackintosh) -[Colton-Ko/macOS-ThinkPad-X1C6](https://github.com/Colton-Ko/macOS-ThinkPad-X1C6) +- x1c6-hackintosh repositories: + - [benbender/x1c6-hackintosh](https://github.com/benbender/x1c6-hackintosh) + - [zhtengw/EFI-for-X1C6-hackintosh](https://github.com/zhtengw/EFI-for-X1C6-hackintosh) +- t480-hackintosh repositories: + - [EETagent/T480-OpenCore-Hackintosh](https://github.com/EETagent/T480-OpenCore-Hackintosh) Create a pull request if you like to be added, final decision at my discreation. +
> ## CONTACT @@ -164,22 +228,28 @@ Signal: +1 (202)-644-9951 \*This is a Signal ONLY number. You will not get a rep https://tylerspaper.com/support/ -> ## CREDITS +
+ CREDITS +
-[@Colton-Ko](https://github.com/Colton-Ko/macOS-ThinkPad-X1C6) for the great features template. -[@stevezhengshiqi](https://github.com/stevezhengshiqi) for the one-key-cpufriend script. -[@corpnewt](https://github.com/corpnewt) for GibMacOS, EFIMount, and USBMap. -[@xzhih](https://github.com/xzhih) for one-key-hidpi. -[@daliansky](https://github.com/daliansky) for various hotpatches. -[@velaar](https://github.com/velaar) for your continual support and contributions. -[@benbender](https://github.com/benbender) for your various issue contributions. -[@Porco-Rosso](https://github.com/Porco-Rosso) putting up with my requests to test repo changes. -[@MSzturc](https://github.com/MSzturc) for adding my requested features to ThinkpadAssistant. +- [@benbender](https://github.com/benbender) for your hardwork. Much of this repo comes from your research and code. Thank you! +- [@Fewtarius](https://github.com/fewtarius) for your help with patching audio. +- [@Colton-Ko](https://github.com/Colton-Ko/macOS-ThinkPad-X1C6) for the great features template. +- [@stevezhengshiqi](https://github.com/stevezhengshiqi) for the one-key-cpufriend script. +- [@corpnewt](https://github.com/corpnewt) for [GibMacOS](https://github.com/corpnewt/gibMacOS) and [EFIMount](https://github.com/corpnewt/MountEFI). +- [@xzhih](https://github.com/xzhih) for one-key-hidpi. +- [daliansky/OC-little](https://github.com/daliansky/OC-little) for various ACPI hotpatch samples. +- [@velaar](https://github.com/velaar) for your continual support and contributions. +- [@Porco-Rosso](https://github.com/Porco-Rosso) putting up with my requests to test repo changes. +- [@MSzturc](https://github.com/MSzturc) for adding my requested features to ThinkpadAssistant. paranoidbashthot and \x for the BIOS mod to unlocked Intel Advance Menu. +- [@zhen-zen](https://github.com/zhen-zen) for YogaSMC +- [CaseySJ](https://www.tonymacx86.com/members/caseysj.2134452/) for the custom modded Thunderbolt 3 firmware. - -The greatest thank you and appreciation to [@Acidanthera](https://github.com/acidanthera), without whom's work, none of this would be possible. +The greatest thank you and appreciation to the [Acidanthera](https://github.com/acidanthera) team. And to everyone else who supports and uses my project. Please let me know if I missed you. + +
\ No newline at end of file diff --git a/docs/1_README-HARDWAREandBIOS.md b/docs/1_README-HARDWAREandBIOS.md index 9bd7ef9..463b2a7 100644 --- a/docs/1_README-HARDWAREandBIOS.md +++ b/docs/1_README-HARDWAREandBIOS.md @@ -21,7 +21,6 @@ At the minimum, these BIOS settings must be made to install and run macOS withou | Main Menu | Sub 1 | Sub 2 | Sub 3 | | --------- | ----------- | --------------------------------------------- | ------------------------------------------------------------------ | -| | | >> Power | Sleep State `Linux` | | | >> Security | >> Security Chip | Security Chip `DISABLED` | | | | >> Fingerprint | Predesktop Authentication `DISABLED` | | | | >> Secure Boot Configuration | Secure Boot `DISABLED` | @@ -34,7 +33,7 @@ At the minimum, these BIOS settings must be made to install and run macOS withou | | >> Startup | UEFI/Legacy Boot `UEFI Only` | | | | | CSM Support `No` (per OpenCore Documentation) | | -* You should also disable hardware devices you do not need to save power: +* You should also disable hardware devices you do not need to save power, some examples are: | Main Menu | Sub 1 | Sub 2 | Sub 3 | | --------- | ----------- | --------------------------------------------- | ------------------------------------------------------------------ | @@ -58,20 +57,25 @@ At the minimum, these BIOS settings must be made to install and run macOS withou | | | | Thunderbolt(TM) Device `Enabled` | -> ## Modding your BIOS: +> ## Modding the BIOS: ### A modded BIOS will allow for more optimizations to be made for macOS and will overall make your hackintosh better. I am a BIOS modding novice myself, but with these instructions, I was able to mod my x1c6 BIOS in less than one hour. I fully recommend doing this for all who think themselves capable. Furthermore, the default `config.plist` for this repository is meant to accommodate a modded BIOS with appropriate settings. If you cannot mod your BIOS or is unwilling to do so, use `config_unmoddedBIOS.plist`. +SPI_Programmer_CH341a.jpg +[SPI Programmer CH341a and SOIC8 connector](https://www.amazon.com/Organizer-Socket-Adpter-Programmer-CH341A/dp/B07R5LPTYM) are needed. + Here are the steps to mod your BIOS (credits to paranoidbashthot and \x): -* Refer to http://paranoid.anal-slavery.com/biosmods/skylake.html -* Use `xx_80_patches-v*.txt`, I commented out WWAN patches since I do not need it. -* [@notthebee](https://github.com/notthebee) also has a useful video to follow: https://www.youtube.com/watch?v=ce7kqUEccUM -* Confirmed working `BIOS-v1.45`, I cannot be sure about other BIOS versions. Though they will most likely work as well. -* The modded BIOS does not need to be signed by `thinkpad-eufi-sign`. Just **remember to replace 4C 4E 56 42 42 53 45 43 FB with 4C 4E 56 42 42 53 45 43 FF on the patched BIOS.** -* On the `x1c6`, the BIOS chip is located just on top of the CPU, under the sticker shield: ![IMG_0571-compressor](https://user-images.githubusercontent.com/3349081/87883762-38686380-c9cf-11ea-9e9d-c400f7b5407b.jpg) -* Successfully modding your BIOS will reveal the `Advance Menu` tab: ![IMG_0572-compressor](https://user-images.githubusercontent.com/3349081/87883767-3d2d1780-c9cf-11ea-9fb0-f250590a3f28.jpg) -* It goes without saying, after doing this, do not update your BIOS unless you want to do this again. -* **It is important that you backup your BIOS twice and `diff` the two dumps to make sure that it was done properly. Do not lose your backup! If anything ever goes wrong, you can flash this image and return to a vanilla state.** +- Refer to http://paranoid.anal-slavery.com/biosmods/skylake.html +- Use `xx_80_patches-v*.txt`, I commented out WWAN patches since I do not need it. +- [@notthebee](https://github.com/notthebee) also has a useful video to follow: https://www.youtube.com/watch?v=ce7kqUEccUM +- Remember to **dump the vanilla twice and use `diff` to make sure things were dumped properly**, store this backup somewhere safe. +- Confirmed working `BIOS-v1.45`, I cannot be sure about other BIOS versions. Though they will most likely work as well. +- The modded BIOS does not need to be signed by `thinkpad-eufi-sign`. Just **remember to replace 4C 4E 56 42 42 53 45 43 FB with 4C 4E 56 42 42 53 45 43 FF on the patched BIOS.** +- The BIOS chip is located above the CPU, under the sticker shield: +BIOS Chip +- Successfully modding your BIOS will reveal the `Advance Menu` tab: +BIOS Advance Menu +- It goes without saying, after doing this, do not update your BIOS unless you want to do this again. ### Finally, make sure to backup your pre-modded BIOS twice and compare the two to make sure that it was dumped properly. Furthermore, attempt this at your own risk, I am not responsible for any damages you may cause. @@ -128,8 +132,18 @@ The following are further optimization settings that can be figured once your BI * Native macOS Thunderbolt interfacing, at the expense of TB3 hotplugging on other OSes: If macOS is your only OS on the machine, or if you only need to use Thunderbolt 3 hotplug on macOS. There is a custom modded firmware that can be flashed onto the Thunderbolt 3 controller that allows for native Thunderbolt interfacing in macOS: https://www.tonymacx86.com/threads/success-gigabyte-designare-z390-thunderbolt-3-i7-9700k-amd-rx-580.267551/page-2452#post-2160674 -![Native TB3 interface in macOS](https://user-images.githubusercontent.com/30384331/89741356-2a62ab80-da80-11ea-8c76-e1f3aaa1d41d.png) + - Screenshot/testing courtesy of @nottthebee * The Thunderbolt chip is located on the top right of the motherboard. * A note before you do this, however, the modded thunderbolt firmware will still require that you disable Thunderbolt BIOS assist, so again, TB3 hotplug will come at the cost of power consumption. -* Secondly, as far as I can tell, this mod is really to make things look cleaner and more native within macOS, and doesn't have any real improvements versus the TB3 method currently in this repo. \ No newline at end of file +* Secondly, as far as I can tell, this mod is really to make things look cleaner and more native within macOS, and doesn't have any real improvements versus the TB3 method currently in this repo. + +> ## Modding the Thunderbolt 3 Controller: +The `Intel JHL6540 (Alpine Ridge 4C)` TB3 chip is labeled as `Winbond` and `W25Q80DVS` is located on the top right of the motherboard. + +- Download [macOS compatible firmware](https://www.tonymacx86.com/attachments/lenovo-x1-carbon-nvm-43-mod-1-caseysj-bin-zip.483524/) +- Again, [@notthebee](https://github.com/notthebee) also has a useful video to follow: https://www.youtube.com/watch?v=ce7kqUEccUM +- Remember to dump the vanilla twice and use `diff` to make sure things were dumped properly, store this backup somewhere safe. +- Once the vanilla firmware has been safely dumped and backed up, you can flash the custom firmware onto the controller. +- Successfully modding your Thunderbolt 3 controller can be confirmed via macOS's System Report: +macOS native TB3 \ No newline at end of file diff --git a/docs/4_README-ACPIpatching.md b/docs/2_README-ACPIpatching.md similarity index 62% rename from docs/4_README-ACPIpatching.md rename to docs/2_README-ACPIpatching.md index 321e8c9..6c9b73b 100644 --- a/docs/4_README-ACPIpatching.md +++ b/docs/2_README-ACPIpatching.md @@ -35,18 +35,23 @@ See highlighted example: > ### Non-native WiFi and Bluetooth -`OpenCore Patches/ Config-DW1560.plist` for DW1560 model cards. -`OpenCore Patches/ Config-DW1820A.plist` for WD1820A model cards. +`/patches/Network Patches/ DW1560.plist` for DW1560 model cards. +`/patches/Network Patches/ DW1820A.plist` for WD1820A model cards. +`/patches/Network Patches/ Intel.plist` for Intel branded cards. \*Notice that these patches require additional kexts to be installed. See them in `Kernel/Add/` -> ### SSDT-OCBAT0-TP_tx80_x1c6th - Enables Battery Status in macOS +> ### SSDT-Darwin - Detects macOS to enable other patches -**Need `OpenCore Patches/ TPbattery.plist`** +> ### SSDT-Battery-Legacy - Enables Battery Status in macOS (Lgeacy) +**Need `OpenCore Patches/ Battery-Legacy.plist`** - Single battery system: only `BAT0` in ACPI, no `BAT1`. -> ### SSDT-PLUG-\_PR.PR00 - Enables Native Intel Power Managements +> ### SSDT-HWAC - Fix axxess to 16byte-EC-field HWAC +- Thanks @benbender + +> ### SSDT-PLUG - Enables Native Intel Power Managements Why?: `Processor` search in DSDT, rename `PR` to other variables as needed. @@ -72,62 +77,74 @@ Why?: `Processor` search in DSDT, rename `PR` to other variables as needed. } ``` -> ### SSDT-PNLF-SKL_KBL - Enables Brightness Management in macOS +> ### SSDT-PNLF - Enables Brightness Management in macOS and Smooth Adjustments with AppleBacklightSmoother.kext iGPU is `PCI0.GFX0` Why?: `Skylake/ KabyLake/ KabyLake-R` CPU. -Used in conjunction with `WhateverGreen.kext` +Used in conjunction with `WhateverGreen.kext` and `AppleBacklightSmoother.kext` (Optional) +> ### SSDT-INIT - Initialize System Variables -> ### SSDT-HPET +Disables: +- HPET +- DPTF +Enables: +- DYTC -- Patch out IRQ conflicts. Credits to [corpnewt/SSDTTime](https://github.com/corpnewt/SSDTTime). -**Needs `OpenCore Patches/ HPET.plist`** +> ### SSDT-Keyboard - Remap PS2 Keys, EC Keys are handled by `BrightnessKeys.kext` -> ### SSDT-Keyboard - Remapping Fn and PrtSc Keys - - Keyboard path is `\ _SB.PCI0.LPCB.KBD`.   -For multimedia functions: - -- Remap 1: F4 (Network) to F20 (for use with ThinkpadAssistant) -- Remap 2: F5 (Brightness Down) -- Remap 3: F6 (Brightness Up) -- Remap 4: F7 (Dual Display) to F16 (for use with ThinkpadAssistant) -- Remap 5: F8 (Network) to F17 (for use with ThinkpadAssistant) -- Remap 6: F9 (Settings) to F18 (for use with ThinkpadAssistant) -- Remap 7: F10 (Bluetooth) to [Left Shift + F8] ((for use with ThinkpadAssistant)) -- Remap 8: F11 (Keyboard) to [Shift+Up] -- Remap 9: F12 (Star) to F19 (for use with ThinkpadAssistant) -- Remap 10: PrtSc to F13 -- Remap 11: Fn + K to Deadkey -- Remap 12: Fn + P to Deadkey +- Configures TrackPoint +- Configures TrackPad (if handled by `VoodooPS2Controller.kext`) +- Remap 1: PrtSc to F13 +- Remap 2: Fn + K to Deadkey +- Remap 3: Fn + P to Deadkey For Fn 1-12 functions, check the following option within `Preferences/Keyboard`: ![Fn keys](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/fnkeys.png) -**Needs `OpenCore Patches/ x1c6-keyboard.plist`** +
+ SSDT-Keyboard-Legacy +
-> ### SSDT-LED -- Fix ThinkPad `i` LED after sleep. -- Persist F4 Mute LED after sleep. - -> ### SSDT-PTSWAK +**Needs `OpenCore Patches/ Keyboard-Legacy.plist`** +- Legacy patch to be used if you prefer [ThinkpadAssisstant](https://github.com/MSzturc/ThinkpadAssistant) over [YogaSMC](https://github.com/zhen-zen/YogaSMC) and `BrightnessKeys.kext` +- Keyboard path is `\ _SB.PCI0.LPCB.KBD`.   +- For multimedia functions: + - Remap 1: F4 (Network) to F20 (for use with ThinkpadAssistant) + - Remap 2: F5 (Brightness Down) + - Remap 3: F6 (Brightness Up) + - Remap 4: F7 (Dual Display) to F16 (for use with ThinkpadAssistant) + - Remap 5: F8 (Network) to F17 (for use with ThinkpadAssistant) + - Remap 6: F9 (Settings) to F18 (for use with ThinkpadAssistant) + - Remap 7: F10 (Bluetooth) to [Left Shift + F8] ((for use with ThinkpadAssistant)) + - Remap 8: F11 (Keyboard) to [Shift+Up] + - Remap 9: F12 (Star) to F19 (for use with ThinkpadAssistant) + - Remap 10: PrtSc to F13 + - Remap 11: Fn + K to Deadkey + - Remap 12: Fn + P to Deadkey +- For Fn 1-12 functions, check the following option within `Preferences/Keyboard`: + ![Fn keys](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/fnkeys.png) +
+> ### SSDT-Sleep - Patch macOS Sleep, S3 - Comprehensive sleep/wake patch. -**Needs `OpenCore Patches/ PTSWAK.plist`** +**Needs `OpenCore Patches/ Sleep.plist`** -Look up `_PTS` and `_WAK` in source DSDT and confirm the following, modify if different: -`_PTS` is `NotSerialized` in my DSDT -`_WAK` is `Serialized` in my DSDT +> ### SSDT-EC - Alow Reads/Write and Provide an Interface with Embedded Controller via YogaSMC +Two parts: +- Allow access to EC +- Sample SSDT from YogaSMC -### SSDT-EXT1-FixShutdown +> ### SSDT-XHC1 - USB 2.0/3.0 +**Needs `OpenCore Patches/ XHC1.plist`** +- Map USB 2.0/3.0 +- Fix Restart on Shutdown -- PTSWAK extension patch. Fixes reboot after shutdown. +> ### SSDT-XHC2 - USB 3.1 +- Patch USB 3.1 -### SSDT-EXT4-WakeScreen +> ### SSDT-USBX - USB Power Properties -- PTSWAK extension patch. Solve the problem that some machines need to press any key to light up the screen after waking up. When using, you should inquire whether the `PNP0C0D` device name and path already exist in the patch file, such as`_SB.PCI0.LPCB.LID0`. If not, add it yourself. - -> ### SSDT-DMAC +> ### SSDT-DMAC - Patch Memory Controller Why?: `PNP0200` is missing in DSDT. @@ -144,10 +161,6 @@ Why?: `PNP0C0C` missing in DSDT. Starting with Catalina, an ambient light sensor device is required for brightness preservation. This patch fakes an ambient light sensor device `ALS0` since the x1c6 does not have one. Why?: `ACPI0008` missing in DSDT. -> ### SSDT-GPRW - -Why?: Fix instant wake by hooking GPRW (0D/6D Patch) - ``` -Special thanks to [daliansky](https://github.com/daliansky). +Special thanks to [@benbender](https://github.com/benbender) and [@daliansky](https://github.com/daliansky). ``` diff --git a/docs/2_README-installMEDIA.md b/docs/2_README-installMEDIA.md deleted file mode 100644 index b75bd57..0000000 --- a/docs/2_README-installMEDIA.md +++ /dev/null @@ -1,23 +0,0 @@ -> ## Partitioning to dual-boot on one drive: -Please refer to [dortania/ opencore `multiboot`](https://github.com/dortania/OpenCore-Multiboot). -*Note that on the x1c6, it is possible, and better to dual boot off of a second drive in the WWAN slot. - -> ## Creating a macOS Installation Media: - -> ### If you have a macOS machine: -1. Download macOS installer from the App Store. -2. Erase the installation media as GUID Partition Map, Mac OS Extended "Journaled". Name it "Install macOS (MacOS version)" - Example: "Install macOS Catalina". -3. Use 'createinstallermedia' command to copy installer to install media. [guide](https://support.apple.com/en-us/ht201372) -4. Install CLOVER bootloader onto the installation media. Use its latest daily build from GitHub. [Download](https://github.com/Dids/clover-builder/releases) - **Though we will not be using Clover, I've found that using the Clover installer is the most convinient way to create an EFI paritition on the installation drive.** -5. After Clover has been installed onto the macOS install drive, its EFI parition should be mounted. Proceed to delete the Clover EFI folder and replace with the EFI folder inside my `EFI-install_USB` folder. -6. Boot into the installation media. -7. Format the intended drive as APFS. -8. Complete the installation. -9. Boot into the newly installed Hackintosh partition using the installation media. That is to say, boot into the installtion media for OpenCore to boot into the installed Hackintosh partition. -10. Proceed with post installation configurations. - -> ### If you do not have a macOS machine: -Use [gibMacOS](https://github.com/corpnewt/gibMacOS) to create installation media on Windows/Linux. I prefer an offline installation as opposed to the recovery method. - -> ## **Refer to [Dortania](https://github.com/dortania) for more detailed documentations.** \ No newline at end of file diff --git a/docs/3_README-POSTinstallation.md b/docs/3_README-POSTinstallation.md deleted file mode 100644 index 35a5c7c..0000000 --- a/docs/3_README-POSTinstallation.md +++ /dev/null @@ -1,51 +0,0 @@ -> ## Post Installtion: - -1. Install OpenCore on the main boot EFI partition to enable boot without the installation media. A good utility to mount your EFI folder is [corpnewt/MountEFI](https://github.com/corpnewt/MountEFI). -2. Please reference my uploaded EFI folder to determine my current bootloader configurations as well as which kexts I am currently using. Note that for CPUFriend, please generate your own DataProvider kexts per different machine specifications and desired configurations. Use [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). -3. Copy the kexts you will be using to their respective directories, per bootloaders: - -- OpenCore: `EFI/OC/Kexts/` - -For the kexts you will be using, make sure to create matching entries within `OpenCore.plist`'s `Kernel/Add/` section. - -\*Refer to my uploaded EFI folder for my current kext list. - -5. Refer to the table below for the other post installtion configurations for each particular issue. Some issues are easy to fix, simply requiring a kext installtion or running a script, while others are my involved and require SSDT patching. -6. For those other, more complicated issues, proceed to `4_README-ACPIpatching.md` - -| Feature | Status | Dependency | Remarks | -| :----------------------------------- | ------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ---------------------------------------------------------------------------------------------------------------------------- | -| macOS (10.14.x or 10.15.x) | ✅ | `VirtualSMC.kext`, `Lilu.kext`, Clover or OpenCore Bootloader | OpenCore is preferred. | -| iMessage/ FaceTime | ✅ | Whitelisted Apple ID, Valid SMBIOS | See `docs/5_README-other.md` | -| Siri | ✅ | Apple ID, Working audio recorder | Needs `AppleALC` | -| iTunes Video Playback | ✅ | `WhateverGreen.kext`, Apple ID (_Optional_) | - | -| Sidecar | ✅ | iPad with iPadOS 13 | Tested with iPad Mini with iPadOS 13.1.2 | -| WiFi | ✅ | Native with BCM94360CS2. `AirportBrcmFixup` otherwise. | See `patches/OpenCore Patches/` for specific network card. | -| Bluetooth | ✅ | Native with BCM94360CS2. `BrcmFirmwareRepo.kext`, `BrcmPatchRAM3.kext`, and `BrcmBluetoothInjector.kext` otherwise. | See `patches/OpenCore Patches/` for specific network card. | -| Continuty | ✅ | Native with BCM94360CS2. `BT4LEContiunityFixup.kext` otherwise. Working Blutetooth and WiFi setup | See `patches/OpenCore Patches/` for specific network card. | -| AirDrop | ✅ | Native with BCM94360CS2. `BT4LEContiunityFixup.kext` otherwise. Working Blutetooth and WiFi setup | See `patches/OpenCore Patches/` for specific network card. | -| TrackPoint | ✅ | `VoodooPS2Controller.kext` | - | -| TrackPad | ✅ | `VoodooPS2Controller.kext` or `VoodooRMI.kext` I prefer `VoodooRMI.kext` so that is the repository default. | - | -| Built-in Keyboard | ✅ | `VoodooPS2Controller.kext` and [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant). Optimizations recommended, see [`docs/5_README-other.md`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/5_README-other.md) | - | -| Battery Percentage Indication | ✅ | `SSDT-OCBAT0-TP_tx80_x1c6th.aml` | Use [MaciASL](https://bitbucket.org/RehabMan/os-x-maciasl-patchmatic/downloads/) | -| CPU Power Management (SpeedShift) | ✅ | `XCPM` and `CPUFriend.kext`, generate your own CPUFriendDataProvider with [CPUFriendFriend](https://github.com/corpnewt/CPUFriendFriend_) or [one-key-cpufriend](https://github.com/stevezhengshiqi/one-key-cpufriend). | -| IGPU Power Management | ✅ | `XCPM`, enabled by `SSDT-PLUG-_PR.PR00.aml` | - | -| PCIe Ethernet | ✅ | `IntelMausi.kext` | Needs Lenovo Ethernet adapter | | -| Audio Recording | ✅ | `AppleALC.kext` with Layout ID = 21 | - | -| Audio Playback | ✅ | `AppleALC.kext` with Layout ID = 21 | - | -| Automatic Headphone Output Switching | ✅ | [ALCPlugFix](https://github.com/tylernguyen/x1c6-hackintosh/tree/master/patches/ALCPlugFix) | - | -| Full Graphics Accleration (QE/CI) | ✅ | `WhateverGreen.kext` | - | -| Brightness Adjustments | ✅ | `WhateverGreen.kext` and `SSDT-PNLF-SKL_KBL.aml` | - | -| Micro SD Card Reader | ✅ | Custom `USBPorts.kext` See current OpenCore-EFI kext folder. You can create your own with [USBMap](https://github.com/corpnewt/USBMap). | - | -| USB 3.1 | ✅ | Custom `USBPorts.kext` See current OpenCore-EFI kext folder. You can create your own with [USBMap](https://github.com/corpnewt/USBMap). | - | -| DisplayPort on Thunderbolt 3 Dock | ⚠️ | `SSDT-TB3.aml`, `IOElectrify.kext` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | -| Thunderbolt 3 Dock (Port Replicator) | ✅ | `SSDT-TB3.aml`, `IOElectrify.kext` | - | -| Thunderbolt 3 Hotplug | ⚠️ | `SSDT-TB3.aml`, `IOElectrify.kext` | [More details](https://github.com/tylernguyen/x1c6-hackintosh/issues/24#issuecomment-603183002) | -| ThinkPad TB3 Dock (40AC) Ethernet | ✅ | `AppleRTL815XComposite109.kext`, `AppleRTL815XEthernet109.kext` | [Item page](https://support.lenovo.com/au/en/solutions/acc100356) | -| CalDigit TS3 Plus Dock | ✅ | | [Item page](https://www.apple.com/shop/product/HMX12ZM/A/caldigit-ts3-plus-dock) | -| HiDPI _(Optional)_ | ✅ | [xzhih/one-key-hidpi](https://github.com/xzhih/one-key-hidpi) | Scaling issues post-sleep fixed with AAPL, ig-platform `BAAnWQ==` | -| Battery life | ✅ | Native, comparable to Windows/Linux. See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) | -| NVMe Drive Battery Management | ✅ | `NVMeFix.kext` | | -| FileVault, Time Machine | ✅ | | Note that TimeMachine only backups your Macintosh partition. Please manually backup your EFI partition using another method. (This repo is mine) | -| Hibernation | ❌ | [DISABLED](https://www.tonymacx86.com/threads/guide-native-power-management-for-laptops.175801/) | With the developement of acidanthera/HibernationFixup and OpenCore, hibernation may be fixed in the future. | -| Sierra Wireless EM7455 | ❌ | `Legacy_Sierra_QMI.kext` | No internet | diff --git a/docs/5_README-other.md b/docs/3_README-other.md similarity index 62% rename from docs/5_README-other.md rename to docs/3_README-other.md index 701a734..14de93e 100644 --- a/docs/5_README-other.md +++ b/docs/3_README-other.md @@ -2,8 +2,7 @@ - macOS minor version upgrade works just as any Mac would. - It is generally a good idea to hold off on new major macOS releases until kexts and other dependencies have been tested. -- Upon upgrading macOS, even minor releases, it is recommended to clear NVRAM to reduce problems. -- Upon changing SSDT patches and/or changing BIOS settings, it is also recommended to clear NVRAM variables. +- The macOS version of my machine is displayed on a badge in `README.md` > ## Configuring PlatformInfo for iMessage/iCloud/FaceTime: @@ -14,11 +13,11 @@ - I recommend that you dual boot using another drive in the WAN slot (I have the WDC PC SN520 NVMe 2242). This makes installation much easier, and lets the BIOS F12 option act as your boot manager. - I've found that dual booting with OpenCore on a single can be quite troublesome. Instead, what I recommend is to use rEFInd Boot Manager should you need to dual boot Windows or Linux. -- It is possible to share Bluetooth pairing keys between Windows and macOS when dual booting. See [oc-laptop-guide](https://dortania.github.io/oc-laptop-guide/extras/dual-booting-with-bluetooth-devices.html). Addtonally, the `.reg` for macOS connected devices can be exported using Hackintool's Utilities section. This key can then be imported to Windows. +- It is possible to share Bluetooth pairing keys between Windows and macOS when dual booting. + - The `.reg` for Bluetooth connected devices in macOS can be exported using Hackintool's Utilities section. This key can then be imported to Windows. > ## Sleep: -- Make sure that sleep mode is set to `Linux` within BIOS. - Disable Power Nap for both [`Battery`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/Battery_powernap.png) and [`Power Adapter`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/Poweradt_powernap.png). - Disable [`Wake for Network Access`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/Poweradt_powernap.png) in `Power Adapter`. - Uncheck [`Allow Bluetooth devices to wake this computer`](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/Bluetooth_wake.png) if you do not need it. @@ -26,40 +25,57 @@ - `sudo pmset -a tcpkeepalive 0` to disable Network while sleeping. - `sudo pmset -a proximitywake 0` to disable peripheral wake agent. +> ## HiDPI, specfically, HiDPI for the WQHD-HDR 1440p Display: + +- Run [xzhih/one-key-hidpi](https://github.com/xzhih/one-key-hidpi) + > ## EDID Override: - This is necessary to fix HDMI hotplug. -- See current available patches in `patches/Internal Displays/` +- See current available patches in `/patches/Internal Displays/`, merge them with `config.plist` - If a patch is not yet created for your display model. Please see [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) to create your own EDID override. Please create a pull request to add your EDID override for different displays. -> ## Thunderbolt 3 Hotplug a.k.a The Big Boss: +> ## Thunderbolt 3 Hotplug a.k.a The Big Boss (Work in Progress): Summary, TB3 hotplug works perfectly, but with some caveats: - Firstly, refer to [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md) for BIOS configurations having to do with TB3 hotplug. -- If you want to hotplug TB3 on the power port, you need an unlocked BIOS to force power to `PR05` (`TbtForcePower.efi` only forces power on `PR09` which is the Ethernet TB3 port.) -- `Thunderbolt BIOS Assist` needs to be disabled which rises idle CPU power consumption to 2W as opposed to ~0.8W with the option enabled. +- `Thunderbolt BIOS Assist` needs to be disabled which raises idle CPU power consumption to 2W as opposed to ~0.8W with the option enabled. - See the ongoing issue/discussion [Issue #24](https://github.com/tylernguyen/x1c6-hackintosh/issues/24) With those done, there are two scenarios: - You want to use TB3 hotplug on both macOS and another OS, such as Linux or Windows. In this case, stick with the current TB3 hotplug setup in this repo. As my repo is currently designed around compatibility with other OSes as I need Windows for work. - You only need TB3 hotplug on macOS. In this case, it is possible to reflash the Thunderbolt controller chip on the machine with a modded firmware designed to allow native Thunderbolt interfacing with macOS. See [docs/1_README-HARDWAREandBIOS.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/1_README-HARDWAREandBIOS.md). -> ## Multimedia Fn Keys: +With Thunderbolt 3 Hotplug, these are the possible scenarios: +- **Modded Controller and BIOS:** + - No additional kexts or drivers needed. (You can remove TB3 related kexts and drivers from your EFI) + - TB3 Hotplug will work natively in macOS. + - TB3 Hotplug will NOT work in Windows or other OS'es. +- **Modded Controller and Vanilla BIOS:** + - No additional kexts or drivers needed. (You can remove TB3 related kexts and drivers from your EFI) + - TB3 Hotplug will work natively in macOS. + - TB3 Hotplug will NOT work in Windows or other OS'es. +- **Vanilla Controller and Modded BIOS:** + - Use `ThunderboltReset.kext` + - Use modded BIOS to force power on `PR09` and `PR05` +- **Vanilla Controller and BIOS:** + - Use `ThunderboltReset.kext` and `TbtForcePower.efi` + - Hotplug will not work on Power port (`PR05`) -Since macOS doesn't not natively support some multimedia Fn key actions. [ThinkpadAssistant](https://github.com/MSzturc/ThinkpadAssistant) is required for the Fn actions to be implemented. Additionally, my settings are: +- Regardless, current TB3 hotplug implementations are not perfect. Current conflicts include getting USB 3.1 gen2, pm, tb - in osx + win all working at the same time. +For a more detailed, and better explaination, refer to [osy86's Thunderbolt Hotplug Docs](https://github.com/osy86/HaC-Mini/tree/master/details) -- F11 = Switch Keyboard Input Language (Set in System `Preferences/Keyboard`) -- PrtSc = Screen Capture (Set in System `Preferences/Keyboard`) +> ## Keyboard: + +- PrtSc (remapped to F13) = I use it for Screen Capture (Set in `System Preferences/Keyboard/Shortcuts`) +- Check `Use F1, F2, etc. keys as standard function keys` in `System Preferences/Keyboard` to gain access to standard F keys: + ![fnkeys](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/fnkeys.png) +- Additionally, [Karabiner-Elements](https://karabiner-elements.pqrs.org/) and [BetterTouchTool](https://folivora.ai/) are great productivty tools to remap and/or add functions to your keyboard. > ## Touchpad: -- By default, this repo is using `VoodoRMI`and `VoodooSMBus` to handle the touchpad. These kexts are still infants and can be buggy. Feel free to change to `VoodooPS2` should you prefer its stability. I, however, prefer the better feel and experience of `VoodooRMI`. - -> ## Touchpad Settings in macOS: - - Force Click is enabled by default, which turns any click on the trackpad into a force touch. I suggest you turn this off. -- In addition, I prefer to have tap to click on. - See my touchpad settings: +- In addition, I prefer to have tap to click on: ![touchpad](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/assets/img/macOS%20Settings/touchpad.png) > ## Optimizations: diff --git a/docs/CHANGELOG.md b/docs/CHANGELOG.md index 64c1097..1b67798 100644 --- a/docs/CHANGELOG.md +++ b/docs/CHANGELOG.md @@ -3,6 +3,50 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/). +> ### 2020-11-3 + +#### Changed + +- OC to 0.6.3 and upgrade various Acidanthera kexts +- Restructured docs: depricated legacy things and combined duplicates. +- `YogaSMC` is now the preferred method to handle Fn keys instead of ThinkpadAssisstant. + - Note that `YogaSMC` is still in its infancy, so you still prefer ThinkpadAssistant, use `SSDT-Keyboard-Legacy.dsl` and `/patches/OpenCore Patches/ Keyboard-Legacy.plist` + - Thank you @zhen-zen for the great kext and app. +- Updated `config.plsit`: + - Removed depricated ACPI renames in accordance with new ACPI patches. + - Added `Arch` value to each kext entry in accordance with new OpenCore doc. + - Added Thunderbolt 3 Device Properties. + - Added `ExtendBTFeatureFlags` value to replace `BT4LEContinuityFixup` +- Reorganized subdirectories within `/patches/` to make things easier to find and understand. +- Renamed `3_README-POSTinstallation.md` to `SUMMARY.md` since it's not really a step but more of an overview of what patches what. +- More readble and better writing of `SSDT-Keyboard` +- New `SSDT-PNLF` to accomodate `AppleBacklightSmoother.kext` +- New battery patch `SSDT-Battery` that fixes accesses to 16byte-EC-field HWAC (Issue #82). +- `SSDT-Sleep` is an all-in-one sleep patch over `SSDT-PTSWAK`, `SSDT-GPRW`, `SSDT-EXT*` + - It is no longer necessary to set sleep mode to `Linux` in BIOS as it is now indepently set by `SSDT-Sleep` +- `If (_OSI ("Darwin"))` and `SSDT-DTPG` are now replaced in favor of `SSDT-Darwin` and `OSDW`, just like in genuine Macs. +- Removed `USBPorts.kext` in favor of patching/mapping via ACPI with `SSDT-XHC1`, `SSDT-XHC2`, and `SSDT-USBX` +- `README.md`: + - Turned different sections into menus for better readability. + - Merged `3_README-POSTinstallation.md` into the `SUMMARY` section. +- Set `HibernateMode` to `NVRAM` instead of `Auto` + +#### Added + +- `update.sh` script to automatically build and replace all ACPI patches +- `SSDT-HWAC` to patch access to 16byte-EC-field HWAC +- `SSDT-EC` to patch embedded controller for use with `YogaSMC` +- `SSDT-Debug`, `SSDT-HOOKS`, and `Debug.plist` for debugging if needed +- `SSDT-INIT` to configure system values: `HPET`, `DYTC`, and `DPTF` +- `YogaSMC.kext` to interface with the device's EC. Make sure to also install the [app and pref pane](https://github.com/zhen-zen/YogaSMC/releases). +- `AppleBacklightSmoother.kext` is just as its name implies. +- `BrightnessKeys.kext` to handle Fn keys with ACPI renames. +- Documentation of modding the Thunderbolt 3 controller. + +#### Removed + +- `SSDT-HPET`, similar to genuine Macs, HPET is now disabled within `SSDT-INIT` + > ### 2020-10-6 #### Notice diff --git a/docs/assets/img/ALCPlugFix_fixAudio.png b/docs/assets/img/ALCPlugFix_fixAudio.png deleted file mode 100644 index 9445e9e..0000000 Binary files a/docs/assets/img/ALCPlugFix_fixAudio.png and /dev/null differ diff --git a/docs/assets/img/SPI_Programmer_CH341a.jpg b/docs/assets/img/SPI_Programmer_CH341a.jpg new file mode 100644 index 0000000..9870db6 Binary files /dev/null and b/docs/assets/img/SPI_Programmer_CH341a.jpg differ diff --git a/docs/assets/img/neofetch.png b/docs/assets/img/neofetch.png new file mode 100644 index 0000000..45d1e45 Binary files /dev/null and b/docs/assets/img/neofetch.png differ diff --git a/docs/references/ACPI-EC-queries.md b/docs/references/ACPI-EC-queries.md new file mode 100644 index 0000000..0eafd5b --- /dev/null +++ b/docs/references/ACPI-EC-queries.md @@ -0,0 +1,89 @@ +## Battery + +### _Q22 + +### _Q4A +/* Battery 0 attach/detach */ + +Method(_Q4A, 0, NotSerialized) +{ + Notify(BAT0, 0x81) +} + +### _Q4B +/* Battery 0 state change */ +``` +Method(_Q4B, 0, NotSerialized) +{ + Notify(BAT0, 0x80) +} +``` + +### _Q4C +/* Battery 1 attach/detach */ +``` +Method(_Q4C, 0, NotSerialized) +{ + Notify(BAT1, 0x81) +} +``` + +### _Q4D +/* Battery 1 state change */ +``` +Method(_Q4D, 0, NotSerialized) +{ + Notify(BAT1, 0x80) +} +``` + +### _Q24 +Battery 0 critical +``` +Notify(BAT0, 0x80) +``` + +### _Q25 +Battery 1 critical +``` +Notify(BAT1, 0x80) +``` + +## Power + +| Event | EC Query | | +|-------------------------------|----------|---| +| Lid Open | _Q2A | | +| Lid Close | _Q2B | | +| Sleep Button | _Q13 | | +| AC Status Change: Present | _Q26 | | +| AC Status Change: Not Present | _Q27 | | + +## Misc + +### _Q1C + +### _Q1D + +## Sleep? + +### _Q62 + +### _Q65 + + +### _Q3D + +### _Q48 + +### _Q49 + +### _Q7F + +### _Q46 + +### _Q3B + +### _Q4F + +### _Q2F \ No newline at end of file diff --git a/docs/references/asl_tutorial_v20190625.pdf b/docs/references/asl_tutorial_v20190625.pdf new file mode 100644 index 0000000..37a27bc Binary files /dev/null and b/docs/references/asl_tutorial_v20190625.pdf differ diff --git a/patches/Debug Patches/Debug.plist b/patches/Debug Patches/Debug.plist new file mode 100644 index 0000000..6a69bdc --- /dev/null +++ b/patches/Debug Patches/Debug.plist @@ -0,0 +1,1938 @@ + + + + + ACPI + + Add + + + Comment + + Enabled + + Path + SSDT-Debug.aml + + + Comment + Hook various event for ACPI debugging + Enabled + + Path + SSDT-HOOKS.aml + + + Delete + + Patch + + + Comment + DBG: MBGS to XDBG + Count + 0 + Enabled + + Find + + TUJHUw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WERCRw== + + ReplaceMask + + + Skip + 2 + TableLength + 0 + TableSignature + + + + + Comment + HOOKS: _Q1C to XQ1C + Count + 0 + Enabled + + Find + + X1ExQw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExQw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q1D to XQ1D + Count + 0 + Enabled + + Find + + X1ExRA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExRA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q1F to XQ1F + Count + 0 + Enabled + + Find + + X1ExRg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExRg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q2A to XQ2A + Count + 0 + Enabled + + Find + + X1EyQQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyQQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q2B to XQ2B + Count + 0 + Enabled + + Find + + X1EyQg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyQg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q2C to XQ2C + Count + 0 + Enabled + + Find + + X1EyQw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyQw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q2D to XQ2D + Count + 0 + Enabled + + Find + + X1EyRA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyRA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q2F to XQ2F + Count + 0 + Enabled + + Find + + X1EyRg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyRg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q3B to XQ3B + Count + 0 + Enabled + + Find + + X1EzQg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEzQg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q3D to XQ3D + Count + 0 + Enabled + + Find + + X1EzRA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEzRA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q3F to XQ3F + Count + 0 + Enabled + + Find + + X1EzRg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEzRg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q4A to XQ4A + Count + 0 + Enabled + + Find + + X1E0QQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0QQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q4B to XQ4B + Count + 0 + Enabled + + Find + + X1E0Qg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0Qg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q4E to XQ4E + Count + 0 + Enabled + + Find + + X1E0RQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0RQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q4F to XQ4F + Count + 0 + Enabled + + Find + + X1E0Rg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0Rg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q6A to XQ6A + Count + 0 + Enabled + + Find + + X1E2QQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2QQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q7F to XQ7F + Count + 0 + Enabled + + Find + + X1E3Rg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE3Rg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q13 to XQ13 + Count + 0 + Enabled + + Find + + X1ExMw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExMw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q14 to XQ14 + Count + 0 + Enabled + + Find + + X1ExNA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExNA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q15 to XQ15 + Count + 0 + Enabled + + Find + + X1ExNQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExNQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q16 to XQ16 + Count + 0 + Enabled + + Find + + X1ExNg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExNg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q19 to XQ19 + Count + 0 + Enabled + + Find + + X1ExOQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFExOQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q22 to XQ22 + Count + 0 + Enabled + + Find + + X1EyMg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyMg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q24 to XQ24 + Count + 0 + Enabled + + Find + + X1EyNA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyNA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q26 to XQ26 + Count + 0 + Enabled + + Find + + X1EyNg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyNg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q27 to XQ27 + Count + 0 + Enabled + + Find + + X1EyNw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEyNw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q38 to XQ38 + Count + 0 + Enabled + + Find + + X1EzOA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFEzOA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q40 to XQ40 + Count + 0 + Enabled + + Find + + X1E0MA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0MA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q41 to XQ41 + Count + 0 + Enabled + + Find + + X1E0MQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0MQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q43 to XQ43 + Count + 0 + Enabled + + Find + + X1E0Mw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0Mw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q45 to XQ45 + Count + 0 + Enabled + + Find + + X1E0NQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0NQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q46 to XQ46 + Count + 0 + Enabled + + Find + + X1E0Ng== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0Ng== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q48 to XQ48 + Count + 0 + Enabled + + Find + + X1E0OA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0OA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q49 to XQ49 + Count + 0 + Enabled + + Find + + X1E0OQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE0OQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q60 to XQ60 + Count + 0 + Enabled + + Find + + X1E2MA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2MA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q61 to XQ61 + Count + 0 + Enabled + + Find + + X1E2MQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2MQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q62 to XQ62 + Count + 0 + Enabled + + Find + + X1E2Mg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2Mg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q63 to XQ63 + Count + 0 + Enabled + + Find + + X1E2Mw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2Mw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q64 to XQ64 + Count + 0 + Enabled + + Find + + X1E2NA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2NA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q65 to XQ65 + Count + 0 + Enabled + + Find + + X1E2NQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2NQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q66 to XQ66 + Count + 0 + Enabled + + Find + + X1E2Ng== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE2Ng== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q70 to XQ70 + Count + 0 + Enabled + + Find + + X1E3MA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE3MA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q72 to XQ72 + Count + 0 + Enabled + + Find + + X1E3Mg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE3Mg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q73 to XQ73 + Count + 0 + Enabled + + Find + + X1E3Mw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE3Mw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _Q74 to XQ74 + Count + 0 + Enabled + + Find + + X1E3NA== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WFE3NA== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L17 to XL17 + Count + 0 + Enabled + + Find + + X0wxNw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEwxNw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L27 to XL27 + Count + 0 + Enabled + + Find + + X0wyNw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEwyNw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L61 to XL61 + Count + 0 + Enabled + + Find + + X0w2MQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2MQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L62 to XL62 + Count + 0 + Enabled + + Find + + X0w2Mg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2Mg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L66 to XL66 + Count + 0 + Enabled + + Find + + X0w2Ng== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2Ng== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L69 to XL69 + Count + 0 + Enabled + + Find + + X0w2OQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2OQ== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + HOOKS: _L6F to XL6F (Thunderbolt 3 Hotplug GPE) + Count + 0 + Enabled + + Find + + X0w2Rg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2Rg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + Kernel + + Add + + + Arch + x86_64 + BundlePath + DebugEnhancer.kext + Comment + Enable debug output in the macOS kernel + Enabled + + ExecutablePath + Contents/MacOS/DebugEnhancer + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + + + + Misc + + Debug + + AppleDebug + + ApplePanic + + DisableWatchDog + + + + NVRAM + + 7C436110-AB2A-4BBB-A880-FE41995C9F82 + + boot-args + + Add + + 7C436110-AB2A-4BBB-A880-FE41995C9F82 + + boot-args + keepsyms=1 acpi_layer=0x8 acpi_level=0x2 debug=0x100 + + + + + diff --git a/patches/Debug Patches/README.md b/patches/Debug Patches/README.md new file mode 100644 index 0000000..d418381 --- /dev/null +++ b/patches/Debug Patches/README.md @@ -0,0 +1 @@ +# How to Debug \ No newline at end of file diff --git a/patches/Debug Patches/SSDT-Debug.dsl b/patches/Debug Patches/SSDT-Debug.dsl new file mode 100644 index 0000000..637003c --- /dev/null +++ b/patches/Debug Patches/SSDT-Debug.dsl @@ -0,0 +1,44 @@ +/* + * Depends on /patches/Debug Patches/ Debug.plist + */ + +DefinitionBlock ("", "SSDT", 0, "X1C6", "_Debug", 0x00001000) +{ + // + // Many OEM ACPI implementations have a ADBG method which is used for debug + // logging. In almost all cases, this function calls MDBG, which is + // supposed to be defined in a ACPI debug SSDT (but is usually missing). + // This should make ADBG functional. + // + // To enable ACPI debug logging in AppleACPIPlatform: + // Add boot args: acpi_layer=0x8 acpi_level=0x2 debug=0x100 + // (https://pikeralpha.wordpress.com/2013/12/23/enabling-acpi-debugging/) + // + // To retrieve the ACPI debug output in macOS: + // log show --last boot --predicate 'process == "kernel" AND senderImagePath CONTAINS "AppleACPIPlatform"' --style compact | awk '/ACPI Debug/{getline; getline; print}' + // + Method (XDBG, 1, NotSerialized) + { + Debug = Arg0 + } + + // to see debug messages + Method (DBG1, 1, NotSerialized) + { + Debug = Arg0 + } + + Method (DBG2, 2, NotSerialized) + { + Debug = Arg0 + Debug = Arg1 + } + + Method (DBG3, 3, NotSerialized) + { + Debug = Arg0 + Debug = Arg1 + Debug = Arg2 + } + +} \ No newline at end of file diff --git a/patches/Debug Patches/SSDT-HOOKS.dsl b/patches/Debug Patches/SSDT-HOOKS.dsl new file mode 100644 index 0000000..5a81b58 --- /dev/null +++ b/patches/Debug Patches/SSDT-HOOKS.dsl @@ -0,0 +1,493 @@ +/* + * Depends on /patches/Debug Patches/ Debug.plist + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_HOOKS", 0x00001000) +{ + External (_SB.PCI0.LPCB.EC, DeviceObj) + + // EC Events + External (_SB.PCI0.LPCB.EC.XQ1C, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ1D, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ1F, MethodObj) // Keyboard Backlight Event + External (_SB.PCI0.LPCB.EC.XQ2A, MethodObj) // LID Open Event + External (_SB.PCI0.LPCB.EC.XQ2B, MethodObj) // LID Close Event + External (_SB.PCI0.LPCB.EC.XQ2C, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ2D, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ2F, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ3B, MethodObj) // Wifi ??? + External (_SB.PCI0.LPCB.EC.XQ3D, MethodObj) // Empty + External (_SB.PCI0.LPCB.EC.XQ3F, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ4A, MethodObj) // Battery Attach/Detach Event + External (_SB.PCI0.LPCB.EC.XQ4B, MethodObj) // Battery State Change Event + External (_SB.PCI0.LPCB.EC.XQ4E, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ4F, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ6A, MethodObj) // KBD MicMute Event (F4) + External (_SB.PCI0.LPCB.EC.XQ7F, MethodObj) // "Fatal()" ? + External (_SB.PCI0.LPCB.EC.XQ13, MethodObj) // KBD Sleepbutton Event (FN+4) + External (_SB.PCI0.LPCB.EC.XQ14, MethodObj) // KBD Brightness up Event (F6) + External (_SB.PCI0.LPCB.EC.XQ15, MethodObj) // KBD Brightness down Event (F5) + External (_SB.PCI0.LPCB.EC.XQ16, MethodObj) // Next display Event (F7) + External (_SB.PCI0.LPCB.EC.XQ19, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ22, MethodObj) // Battery at critical low state Event + External (_SB.PCI0.LPCB.EC.XQ24, MethodObj) // Battery + External (_SB.PCI0.LPCB.EC.XQ26, MethodObj) // AC Power Connected + External (_SB.PCI0.LPCB.EC.XQ27, MethodObj) // AC Power Removed + External (_SB.PCI0.LPCB.EC.XQ38, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ40, MethodObj) // Thermal/DYTC ??? + External (_SB.PCI0.LPCB.EC.XQ41, MethodObj) // Global Wireless Disable/Enable Event ? + External (_SB.PCI0.LPCB.EC.XQ43, MethodObj) // KBD Audio Mute Event (F1) + External (_SB.PCI0.LPCB.EC.XQ45, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ46, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ48, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ49, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ60, MethodObj) // KBD Bluetooth Event (F10) + External (_SB.PCI0.LPCB.EC.XQ61, MethodObj) // KBD Keyboard Event (F11) + External (_SB.PCI0.LPCB.EC.XQ62, MethodObj) // KBD Star Event (F12) + External (_SB.PCI0.LPCB.EC.XQ63, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ64, MethodObj) // KBD Wifi Event (F8) + External (_SB.PCI0.LPCB.EC.XQ65, MethodObj) // ??? + External (_SB.PCI0.LPCB.EC.XQ66, MethodObj) // KBD Settings Event (F9) + External (_SB.PCI0.LPCB.EC.XQ70, MethodObj) // Fan ??? + External (_SB.PCI0.LPCB.EC.XQ72, MethodObj) // Fan ??? + External (_SB.PCI0.LPCB.EC.XQ73, MethodObj) // Fan ??? + External (_SB.PCI0.LPCB.EC.XQ74, MethodObj) // KBD FNLock Event + + // GPE Events (General Purpose) + External (_GPE.XL17, MethodObj) // ??? + External (_GPE.XL27, MethodObj) // ??? + External (_GPE.XL61, MethodObj) // ??? + External (_GPE.XL62, MethodObj) // ??? + External (_GPE.XL66, MethodObj) // ??? + External (_GPE.XL69, MethodObj) // ??? + // External (_GPE.XL6D, MethodObj) // ??? + External (_GPE.XL6F, MethodObj) // Thunderbolt HotPlug + + + Scope (\_SB.PCI0.LPCB.EC) + { + // MHKK + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q1C (???)" + + XQ1C() + } + + // ??? + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q1D (???)" + + XQ1D() + } + + // Keyboard Backlight Event + Method (_Q1F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q1F (Keyboard Backlight Event)" + + XQ1F() + } + + // LID Open Event + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q2A (LID Open Event)" + + XQ2A() + } + + // LID Close Event + Method (_Q2B, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q2B (LID Close Event)" + + XQ2B() + } + + // ??? + Method (_Q2C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q2C (???)" + + XQ2C() + } + + // ??? + Method (_Q2D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q2D (???)" + + XQ2D() + } + + // ??? + Method (_Q2F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q2F (???)" + + XQ2F() + } + + // Wifi ??? + Method (_Q3B, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q3B (Wifi ???)" + + XQ3B() + } + + // Empty??? + Method (_Q3D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q3D (Empty???)" + + XQ3D() + } + + // ??? + Method (_Q3F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q3F (???)" + + XQ3F() + } + + // Battery Attach/Detach Event + Method (_Q4A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q4A (Battery Attach/Detach Event)" + + XQ4A() + } + + // Battery State Change Event + Method (_Q4B, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q4B (Battery State Change Event)" + + XQ4B() + } + + // ??? + Method (_Q4E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q4E (???)" + + XQ4E() + } + + // ??? + Method (_Q4F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q4F (???)" + + XQ4F() + } + + // KBD MicMute Event (F4) + Method (_Q6A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q6A (KBD MicMute Event - F4)" + + XQ6A() + } + + // "Fatal()" ? + Method (_Q7F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q7F (FATAL())" + + XQ7F() + } + + // KBD Sleepbutton Event (FN+4) + Method (_Q13, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q13 (KBD Sleepbutton Event - FN+4)" + + XQ13() + } + + // KBD Brightness up Event (F4) + Method (_Q14, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q14 (KBD Brightness up Event - F4)" + + XQ14() + } + + // KBD Brightness down Event (F5) + Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q15 (KBD Brightness down Event - F5)" + + XQ15() + } + + // KBD Next display Event + Method (_Q16, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q16 (Next display Event)" + + XQ16() + } + + // ??? + Method (_Q19, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q19 (???)" + + XQ19() + } + + // Battery at critical low state Event + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q22 (Battery at critical low state Event)" + + XQ22() + } + + // Battery + Method (_Q24, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q24 (Battery)" + + XQ24() + } + + // AC Power Connected Event + Method (_Q26, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q26 (AC Power Connected Event)" + + XQ26() + } + + // AC Power Removed Event + Method (_Q27, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q27 (AC Power Removed Event)" + + XQ27() + } + + // ??? + Method (_Q38, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q38 (???)" + + XQ38() + } + + // Thermal/DYTC ??? + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q40 (Thermal/DYTC???)" + + XQ40() + } + + // ??? + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q41 (???)" + + XQ41() + } + + // KBD Audio Mute Event (F1) + Method (_Q43, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q43 (KBD Audio Mute Event - F1)" + + XQ43() + } + + // ??? + Method (_Q45, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q45 (???)" + + XQ45() + } + + // ??? + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q46 (???)" + + XQ46() + } + + // ??? + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q48 (???)" + + XQ48() + } + + // ??? + Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q49 (???)" + + XQ49() + } + + // ??? + Method (_Q60, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q60 (???)" + + XQ60() + } + + // ??? + Method (_Q61, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q61 (???)" + + XQ61() + } + + // ??? + Method (_Q62, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q62 (???)" + + XQ62() + } + + // ??? + Method (_Q63, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q63 (???)" + + XQ63() + } + + // ??? + Method (_Q64, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q64 (???)" + + XQ64() + } + + // ??? + Method (_Q65, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q65 (???)" + + XQ65() + } + + // ??? + Method (_Q66, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q66 (???)" + + XQ66() + } + + // Fan??? + Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q70 (Fan???)" + + XQ70() + } + + // Fan ??? + Method (_Q72, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q72 (Fan???)" + + XQ72() + } + + // Fan ??? + Method (_Q73, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q73 (Fan???)" + + XQ73() + } + + // Keyboard FNLock Event + Method (_Q74, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "HOOKS: EC:_Q74 (Keyboard FNLock Event)" + + XQ73() + } + } + + + Scope (_GPE) + { + Method (_L17, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Debug = "HOOKS: _L17() start" + + XL17() + } + + Method (_L27, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Debug = "HOOKS: _L27() start" + + XL27() + } + + Method (_L61, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Debug = "HOOKS: _L61()" + + XL61() + } + + + Method (_L62, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Debug = "HOOKS: _L62()" + + XL62() + } + + Method (_L66, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Debug = "HOOKS: _L66() start (iGPU)" + + XL66() + } + + // PCI Wake + Method (_L69, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Debug = "HOOKS: _L69() start (PCI)" + + XL69() + } + + // Device Wake - already hooked + // Method (_L6D, 0, NotSerialized) // _Lxx: Level-Triggered GPE + // { + // Debug = "HOOKS: _L6D() (Device wake" + + // XL6D() + // } + + // TB HotPlug + Method (_L6F, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Debug = "HOOKS: _L6F() (TB HotPlug)" + + XL6F() + } + } +} \ No newline at end of file diff --git a/patches/Internal Displays/FHD-EDID.plist b/patches/Display Patches/FHD-Non-touch_EDID.plist similarity index 100% rename from patches/Internal Displays/FHD-EDID.plist rename to patches/Display Patches/FHD-Non-touch_EDID.plist diff --git a/patches/OpenCore Patches/Config-FHD_Touchscreen.plist b/patches/Display Patches/FHD_Touchscreen.plist similarity index 100% rename from patches/OpenCore Patches/Config-FHD_Touchscreen.plist rename to patches/Display Patches/FHD_Touchscreen.plist diff --git a/patches/Display Patches/README.md b/patches/Display Patches/README.md new file mode 100644 index 0000000..ca4644d --- /dev/null +++ b/patches/Display Patches/README.md @@ -0,0 +1,21 @@ +## README +- By default, the repo setup is display-agnostic. **At the minimum, an EDID override is required for functioning HDMI hotplug.** +- If the EDID profile for your display is not included in here, please refer to [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) +- Refer to [/docs/references/x1c6-Platform_Specifications](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/references/x1c6-Platform_Specifications.pdf) for possible stock ThinkPad X1 6th Gen configurations. + +### WQHD-HDR-B140QAN02_0.icm +Calibrated color profile for the WQHD-HDR display. + +### WQHD-HDR-EDID.plist +EDID override for the WQHD-HDR display, with additional overlocked refresh rates: + - 64Hz is stable. + - 65Hz causes minor artifacts. + - 66Hz makes display go crazy. + - You may be more/less lucky with your own panel. + +### FHD-Non-touch_EDID.plist +EDID override for the Non-touch 1080p display. + +### FHD_Touchscreen.plist +Patches for the 1080p touchscreen display. + diff --git a/patches/Internal Displays/WQHD-HDR-B140QAN02_0.icm b/patches/Display Patches/WQHD-HDR-B140QAN02_0.icm similarity index 100% rename from patches/Internal Displays/WQHD-HDR-B140QAN02_0.icm rename to patches/Display Patches/WQHD-HDR-B140QAN02_0.icm diff --git a/patches/Display Patches/WQHD-HDR-EDID.plist b/patches/Display Patches/WQHD-HDR-EDID.plist new file mode 100644 index 0000000..729edea --- /dev/null +++ b/patches/Display Patches/WQHD-HDR-EDID.plist @@ -0,0 +1,17 @@ + + + + + DeviceProperties + + Add + + PciRoot(0x0)/Pci(0x2,0x0) + + AAPL00,override-no-connect + AP///////wAwrq5AAAAAAAAbAQSQHxF44vvVplM0tiUOUFQAAAABAQEBAQEBAQEBAQEBAQEB5l8AoKCgQFAwIDUAgGghAAAYj2YAoKCgLVAwIDUAgGghAAAY22cAoKCgKVAwIDUAgGghAAAYMGUAoKCgMFAwIDUAgGghAAAYADc= + + + + + diff --git a/patches/Internal Displays/WQHD-HDR-EDID.plist b/patches/Internal Displays/WQHD-HDR-EDID.plist deleted file mode 100755 index 730021f..0000000 --- a/patches/Internal Displays/WQHD-HDR-EDID.plist +++ /dev/null @@ -1,30 +0,0 @@ - - - - - DeviceProperties - - Add - - PciRoot(0x0)/Pci(0x2,0x0) - - AAPL00,override-no-connect - - AP///////wAwrq5AAAAAAAAbAQSQHxF44vvVplM0tiUO - UFQAAAABAQEBAQEBAQEBAQEBAQEB5l8AoKCgQFAwIDUA - gGghAAAYj2YAoKCgLVAwIDUAgGghAAAY22cAoKCgKVAw - IDUAgGghAAAYMGUAoKCgMFAwIDUAgGghAAAYADc= - - DELETE ME - 64Hz is stable. - DELETE ME 2 - 65Hz causes minor artifacts. - DELETE ME 3 - 66Hz makes display goes crazy. - DELETE ME 4 - You be more/less lucky with your specific display. - - - - - diff --git a/patches/OpenCore Patches/Config-DW1560.plist b/patches/Network Patches/DW1560.plist old mode 100755 new mode 100644 similarity index 83% rename from patches/OpenCore Patches/Config-DW1560.plist rename to patches/Network Patches/DW1560.plist index a3b7e50..b8905f3 --- a/patches/OpenCore Patches/Config-DW1560.plist +++ b/patches/Network Patches/DW1560.plist @@ -93,6 +93,22 @@ PlistPath Contents/Info.plist + + BundlePath + AirPortBrcmNIC_Injector.kext + Comment + + Enabled + + ExecutablePath + Contents/MacOS/AirportBrcmFixup/Contents/PlugIns/AirPortBrcmNIC_Injector.kext + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + diff --git a/patches/OpenCore Patches/Config-DW1820A.plist b/patches/Network Patches/DW1820A.plist old mode 100755 new mode 100644 similarity index 100% rename from patches/OpenCore Patches/Config-DW1820A.plist rename to patches/Network Patches/DW1820A.plist diff --git a/patches/OpenCore Patches/Config-Intel.plist b/patches/Network Patches/Intel.plist similarity index 100% rename from patches/OpenCore Patches/Config-Intel.plist rename to patches/Network Patches/Intel.plist diff --git a/patches/OpenCore Patches/4K-Output.plist b/patches/OpenCore Patches/4K-Output-wo-BIOSmod.plist similarity index 100% rename from patches/OpenCore Patches/4K-Output.plist rename to patches/OpenCore Patches/4K-Output-wo-BIOSmod.plist diff --git a/patches/OpenCore Patches/TPbattery.plist b/patches/OpenCore Patches/Battery-Legacy.plist old mode 100755 new mode 100644 similarity index 100% rename from patches/OpenCore Patches/TPbattery.plist rename to patches/OpenCore Patches/Battery-Legacy.plist diff --git a/patches/OpenCore Patches/HPET.plist b/patches/OpenCore Patches/HPET.plist deleted file mode 100644 index 4c4d603..0000000 --- a/patches/OpenCore Patches/HPET.plist +++ /dev/null @@ -1,131 +0,0 @@ - - - - - ACPI - - Add - - - Comment - HPET _CRS (Needs _CRS to XCRS Rename) - Enabled - - Path - SSDT-HPET.aml - - - Patch - - - Comment - HPET _CRS to XCRS Rename - Count - 0 - Enabled - - Find - - X0NSUwig - - Limit - 0 - Mask - - - OemTableId - - AAAAAA== - - Replace - - WENSUwig - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - AAAAAA== - - - - Comment - RTC IRQ 8 Patch - Count - 0 - Enabled - - Find - - IgABeQA= - - Limit - 0 - Mask - - - OemTableId - - AAAAAA== - - Replace - - IgAAeQA= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - AAAAAA== - - - - Comment - TIMR IRQ 0 Patch - Count - 0 - Enabled - - Find - - IgEAeQA= - - Limit - 0 - Mask - - - OemTableId - - AAAAAA== - - Replace - - IgAAeQA= - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - AAAAAA== - - - - - - diff --git a/patches/OpenCore Patches/HWAC.plist b/patches/OpenCore Patches/HWAC.plist new file mode 100644 index 0000000..fe5415d --- /dev/null +++ b/patches/OpenCore Patches/HWAC.plist @@ -0,0 +1,47 @@ + + + + + ACPI + + Patch + + + Comment + Battery: Change HWAC to XWAC EC reads + Count + 0 + Enabled + + Find + + RUNfX0hXQUM= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + RUNfX1hXQUM= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + + diff --git a/patches/OpenCore Patches/x1c6-keyboard.plist b/patches/OpenCore Patches/Keyboard-Legacy.plist similarity index 100% rename from patches/OpenCore Patches/x1c6-keyboard.plist rename to patches/OpenCore Patches/Keyboard-Legacy.plist diff --git a/patches/OpenCore Patches/PTSWAK.plist b/patches/OpenCore Patches/Sleep.plist similarity index 70% rename from patches/OpenCore Patches/PTSWAK.plist rename to patches/OpenCore Patches/Sleep.plist index 0cf6bfc..03a0008 100644 --- a/patches/OpenCore Patches/PTSWAK.plist +++ b/patches/OpenCore Patches/Sleep.plist @@ -8,65 +8,55 @@ Comment - _PTS to ZPTS(1,N) + S3 Sleep: GRPW to ZRPW Count 0 Enabled Find - - X1BUUwE= - + BkdQUlcCcA== Limit 0 Mask - - + OemTableId - - + Replace - - WlBUUwE= - + BlpQUlcCcA== ReplaceMask - - + Skip 0 TableLength 0 + TableSignature + RFNEVA== Comment - _WAK to ZWAK(1,S) + S3 Sleep: _WAK to ZWAK(1,S) Count 0 Enabled Find - - X1dBSwk= - + X1dBSwk= Limit 0 Mask - - + OemTableId - - + Replace - - WldBSwk= - + WldBSwk= ReplaceMask - - + Skip 0 TableLength 0 + TableSignature + RFNEVA== diff --git a/patches/OpenCore Patches/TB3-hotplug.plist b/patches/OpenCore Patches/TB3-hotplug.plist deleted file mode 100644 index ef47b35..0000000 --- a/patches/OpenCore Patches/TB3-hotplug.plist +++ /dev/null @@ -1,123 +0,0 @@ - - - - - ACPI - - Add - - - Comment - TB3 Hotplug Support - Enabled - - Path - SSDT-DTPG.aml - - - Comment - TB3 Hotplug - Enabled - - Path - SSDT-Z390-TB3HP.aml - - - Patch - - - Comment - _L6F to XL6F (Thunderbolt 3 Hotplug GPE) - Count - 1 - Enabled - - Find - - X0w2Rg== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WEw2Rg== - - ReplaceMask - - - Skip - 0 - TableLength - 0 - TableSignature - - - - - Comment - RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) - Count - 1 - Enabled - - Find - - X0lOSQ== - - Limit - 0 - Mask - - - OemTableId - - - Replace - - WElOSQ== - - ReplaceMask - - - Skip - 11 - TableLength - 0 - TableSignature - - - - - - COMMENT/ DELETE ME - Incomplete! Only acting as notes, please refer to docs/5_README-other - Kernel - - Add - - - BundlePath - ThunderboltReset.kext - Comment - - Enabled - - ExecutablePath - Contents/MacOS/ThunderboltReset - MaxKernel - - MinKernel - - PlistPath - Contents/Info.plist - - - - - diff --git a/patches/OpenCore Patches/Thunderbolt3.plist b/patches/OpenCore Patches/Thunderbolt3.plist new file mode 100644 index 0000000..73f76da --- /dev/null +++ b/patches/OpenCore Patches/Thunderbolt3.plist @@ -0,0 +1,253 @@ + + + + + ACPI + + Patch + + + Comment + Thunderbolt 3: _L27 to XL27 + Count + 0 + Enabled + + Find + + X0wyNw== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEwyNw== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + Comment + Thunderbolt 3: RP09:_PS0 to RP09:XPS0 + Count + 1 + Enabled + + Find + + X1BTMA== + + Limit + 0 + Mask + + + OemTableId + + UlZQN1J0ZDM= + + Replace + + WFBTMA== + + ReplaceMask + + + Skip + 0 + TableLength + 7453 + TableSignature + + U1NEVA== + + + + Comment + Thunderbolt 3: RP09:_PS3 to RP09:XPS3 + Count + 1 + Enabled + + Find + + X1BTMw== + + Limit + 0 + Mask + + + OemTableId + + UlZQN1J0ZDM= + + Replace + + WFBTMw== + + ReplaceMask + + + Skip + 0 + TableLength + 7453 + TableSignature + + U1NEVA== + + + + Comment + Thunderbolt 3: _L6F to XL6F (Thunderbolt 3 Hotplug GPE) + Count + 0 + Enabled + + Find + + X0w2Rg== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WEw2Rg== + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + + + + Comment + Thunderbolt 3: RP09._INI to RP09.XINI for ICM disable (ThunderboltReset.kext) + Count + 1 + Enabled + + Find + + X0lOSQ== + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WElOSQ== + + ReplaceMask + + + Skip + 11 + TableLength + 0 + TableSignature + + + + + Comment + Thunderbolt 3: _PTS to ZPTS(1,N) + Count + 0 + Enabled + + Find + + X1BUUwE= + + Limit + 0 + Mask + + + OemTableId + + + Replace + + WlBUUwE= + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + Kernel + + Add + + + Arch + x86_64 + BundlePath + ThunderboltReset.kext + Comment + + Enabled + + ExecutablePath + Contents/MacOS/ThunderboltReset + MaxKernel + + MinKernel + + PlistPath + Contents/Info.plist + + + + UEFI + + Drivers + + TbtForcePower.efi + + + + diff --git a/patches/OpenCore Patches/XHC1.plist b/patches/OpenCore Patches/XHC1.plist new file mode 100644 index 0000000..4e3c3e4 --- /dev/null +++ b/patches/OpenCore Patches/XHC1.plist @@ -0,0 +1,47 @@ + + + + + ACPI + + Patch + + + Comment + XHC1: Notify(XHC_, 0x02) to XHC1 (Fix Restart on Shutdown) + Count + 0 + Enabled + + Find + + hlhIQ18K + + Limit + 0 + Mask + + + OemTableId + + + Replace + + hlhIQzEK + + ReplaceMask + + + Skip + 0 + TableLength + 0 + TableSignature + + RFNEVA== + + + + + + diff --git a/patches/README.md b/patches/README.md index 980330b..6b46d76 100644 --- a/patches/README.md +++ b/patches/README.md @@ -1 +1,22 @@ -## Please refer to [docs/4_README-ACPIpatching.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/4_README-ACPIpatching.md) for Hotpatching notes. \ No newline at end of file +## README + +In the current directory are ACPI source files of patches in-use. + +Please refer to [docs/3_README-ACPIpatching.md](https://github.com/tylernguyen/x1c6-hackintosh/blob/master/docs/3_README-ACPIpatching.md) for each of their specific usage and purposes. In addition, each patch have insightful comments in them, please read throughly read their source code. + +## OpenCore Patches +By default, the repo `config.plist` should have already have these patches included. These patches are mostly dependencies of various ACPI patches. They are here for reference patches. + +## Display Patches +By default, the repo setup is display-agnostic. At the minimum, an EDID override is required for functioning HDMI hotplug. In addition, there are other things in this patch folder: calibrated color profiled, touchscreen patch. + +If the EDID profile for your display is not included in here, please refer to [Issue #60](https://github.com/tylernguyen/x1c6-hackintosh/issues/60) + +## Network Patches +By default, the repo is setup for the macOS native Broadcom card. If your config includes other wireless cards, please refer to this folder. + +## Debug Patches +By default, debug information is very limited. These patches will you much more information when diagnosing issues. + +## update.sh +Run this script to compile `.dsl` patches into `.aml` and place them into the ACPI folder. \ No newline at end of file diff --git a/patches/SSDT-ALS0.dsl b/patches/SSDT-ALS0.dsl index ae33b0f..8d2badf 100644 --- a/patches/SSDT-ALS0.dsl +++ b/patches/SSDT-ALS0.dsl @@ -3,7 +3,8 @@ * Here we create an Ambient Light Sensor ACPI Device, which can be used by SMCLightSensor kext * to report either dummy (when no device is present) or valid values through SMC interface. */ -DefinitionBlock ("", "SSDT", 2, "tyler", "ALS0", 0x00000000) + +DefinitionBlock ("", "SSDT", 2, "tyler", "_ALS0", 0x00000000) { Scope (_SB) { diff --git a/patches/SSDT-Battery.dsl b/patches/SSDT-Battery.dsl new file mode 100644 index 0000000..37d0357 --- /dev/null +++ b/patches/SSDT-Battery.dsl @@ -0,0 +1,1388 @@ +// +// SSDT-BATX +// Revision 5 +// +// Copyleft (c) 2020 by bb. No rights reserved. +// +// +// Abstract: +// This SSDT is a complete, self-contained replacement for all battery-patches on Thinkpads which share +// a common EC-layout for battery-handling. It should be compatible with all(?) T- and X-series Thinkpads and maybe even more. +// +// It doesn't need any patches to the original DSDT, handles single- and dual-battery-systems gracefully and adds +// support for `Battery Information Supplement` (see: https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md). +// +// It is faster, more compatible and much more robust than existing patches as it doesn't relie on the original DSDT-implementation +// for battery-handling and EC-access. It eliminates the need to patch mutexes, notifies or EC-fields completely. +// +// It replaces any battery-related DSDT-patches and any SSDT like SSDT-BAT0, SSDT-BATT, SSDT-BATC, SSDT-BATN and similar. +// +// Its only dependency is the memory-layout of the Embedded Controller (EC), which is mostly the same for all decent modern thinkpads +// (at least T440/X440 upwards) and nothing else. Just drop the SSDT in and be done. +// For most Thinkpads, this should be the only thing you need to handle your batteries. Nothing more, nothing less. +// +// But be aware: this is newly created stuff, not much tested or battle proven yet. May contain bugs and edgecases. +// If so, please open a bug @ https://github.com/benbender/x1c6-hackintosh/issues +// +// +// References: +// https://github.com/coreboot/coreboot/blob/master/src/ec/quanta/it8518/acpi/ec.asl +// https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf +// https://github.com/acidanthera/VirtualSMC/blob/master/Docs/Battery%20Information%20Supplement.md +// +// +// Changelog: +// Revision 1 - Raised timeout for mutexes, factored bank-switching out, added sleep to bank-switching, moved HWAC to its own SSDT +// Revision 2 - Prelimitary dual-battery-support, large refactoring +// Revision 3 - Remove need of patched notifies, handle battery attach/detach inside, make the whole device self-contained (exept for the EC-helpers) +// Revision 4 - Waits on initialization of the batts now. Besides that: Optimization, rework, cleanup, fixes. Truely self-contained now. And faster. +// Revision 5 - optimization, bug-fixing. Adds temp, concatenates string-data on combined batteries. +// +// +// Add the following methods if didn't have them defined anyways: +// +// Credits @benbender + +DefinitionBlock ("", "SSDT", 2, "tyler", "_Battery", 0x00001000) +{ + External (_SB.PCI0.LPCB.EC, DeviceObj) + + // @see https://en.wikipedia.org/wiki/Bank_switching + // + // HIID: [Battery information ID for 0xA0-0xAF] + // (this byte is depend on the interface, 62&66 and 1600&1604) + External (_SB.PCI0.LPCB.EC.HIID, FieldUnitObj) + + External (_SB.PCI0.LPCB.EC.BAT0._STA, MethodObj) + External (_SB.PCI0.LPCB.EC.BAT0._HID, IntObj) + + External (_SB.PCI0.LPCB.EC.BAT1._STA, MethodObj) + External (_SB.PCI0.LPCB.EC.BAT1._HID, IntObj) + + External (H8DR, FieldUnitObj) + + + Scope (\_SB.PCI0.LPCB.EC) + { + // + // EC region overlay. + // + OperationRegion (BRAM, EmbeddedControl, 0x00, 0x0100) + + /** + * New battery device + */ + Device (BATX) + { + /************************* Configuration *************************/ + + Name (BDBG, One) + + + /************************* Mutex **********************************/ + + Mutex (BAXM, 0x00) + + + /************************* EC overlay *****************************/ + + + Field(BRAM, ByteAcc, NoLock, Preserve) + { + Offset (0x38), + // HB0S: [Battery 0 status (read only)] + // bit 3-0 level + // F: Unknown + // 2-n: battery level + // 1: low level + // 0: (critical low battery, suspend/ hibernate) + // bit 4 error + // bit 5 charge + // bit 6 discharge + HB0S, 7, /* Battery 0 state */ + HB0A, 1, /* Battery 0 present */ + + // Offset (0x39), + HB1S, 7, /* Battery 1 state */ + HB1A, 1, /* Battery 1 present */ + + Offset (0xC9), + HWAT, 8, /* Wattage of AC/DC */ + + // Zero on the X1C6. Probably because of the charging is handled by the TI USB-C-PD-chip. + // Offset (0xCC), + // PWMH, 8, /* CC : AC Power Consumption (MSB) */ + // PWML, 8, /* CD : AC Power Consumption (LSB) - unit: 100mW */ + } + + // + // EC Registers + // HIID == 0x00 + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // SBRC, 16, // Remaining Capacity + RC00, 8, + RC01, 8, + // SBFC, 16, // Fully Charged Capacity + FC00, 8, + FC01, 8, + // SBAE, 16, // Average Time To Empty + AE00, 8, + AE01, 8, + // SBRS, 16, // Relative State Of Charge + RS00, 8, + RS01, 8, + // SBAC, 16, // Average Current / present rate + AC00, 8, + AC01, 8, + // SBVO, 16, // Voltage + VO00, 8, + VO01, 8, + // SBAF, 16, // Average Time To Full + AF00, 8, + AF01, 8, + // SBBS, 16, // Battery State + BS00, 8, + BS01, 8, + } + + // + // EC Registers + // HIID == 0x01 + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // Battery Mode(w) + // , 15, + // SBCM, 1, // bit 15 - CAPACITY_MODE + // 0: Report in mA/mAh ; 1: Enabled + // SBBM, 16, // Battery Mode(w) + BM00, 8, + BM01, 8, + // SBMD, 16, // Manufacture Data + MD00, 8, + MD01, 8, + // SBCC, 16, // Cycle Count + CC00, 8, + CC01, 8, + } + + // + // EC Registers + // HIID == 0x02 + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // SBDC, 16, // Design Capacity + DC00, 8, + DC01, 8, + // SBDV, 16, // Design Voltage + DV00, 8, + DV01, 8, + // SBOM, 16, // Optional Mfg Function 1 + OM00, 8, + OM01, 8, + // SBSI, 16, // Specification Info + SI00, 8, + SI01, 8, + // SBDT, 16, // Manufacture Date + DT00, 8, + DT01, 8, + // SBSN, 16, // Serial Number + SN00, 8, + SN01, 8, + } + + // + // EC Registers + // HIID == 0x04: Battery type + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // SBCH, 32, // Device Checmistory (string) + CH00, 8, + CH01, 8, + CH02, 8, + CH03, 8 + } + + // + // EC Registers + // HIID == 0x05: Battery OEM information + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // SBMN, 128, // Manufacture Name (s) + MN00, 8, + MN01, 8, + MN02, 8, + MN03, 8, + MN04, 8, + MN05, 8, + MN06, 8, + MN07, 8, + MN08, 8, + MN09, 8, + MN0A, 8, + MN0B, 8, + MN0C, 8, + MN0D, 8, + MN0E, 8, + MN0F, 8, + } + + // + // EC Registers + // HIID == 0x06: Battery name + // + Field (BRAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + // SBDN, 128, // Device Name (s) + DN00, 8, + DN01, 8, + DN02, 8, + DN03, 8, + DN04, 8, + DN05, 8, + DN06, 8, + DN07, 8, + DN08, 8, + DN09, 8, + DN0A, 8, + DN0B, 8, + DN0C, 8, + DN0D, 8, + DN0E, 8, + DN0F, 8, + } + + + /************************* Access methods *************************/ + + /** + * Method to read the 16-bit-EC-field SBRC + * + * Remaining Capacity + */ + Method (SBRC, 0, NotSerialized) + { + Return (B1B2 (RC00, RC01)) + } + + /** + * Method to read the 16 bit-EC-field SBFC + * + * Fully Charged Capacity + */ + Method (SBFC, 0, NotSerialized) + { + Return (B1B2 (FC00, FC01)) + } + + /** + * Method to read the 16 bit-EC-field SBAE + * + * Average Time To Empty + */ + Method (SBAE, 0, NotSerialized) + { + Return (B1B2 (AE00, AE01)) + } + + /** + * Method to read the 16 bit-EC-field SBRS + * + * Relative State Of Charge + */ + Method (SBRS, 0, NotSerialized) + { + Return (B1B2 (RS00, RS01)) + } + + /** + * Method to read the 16 bit-EC-field SBAC + * + * Average Current / present rate + */ + Method (SBAC, 0, NotSerialized) + { + Return (B1B2 (AC00, AC01)) + } + + /** + * Method to read the 16 bit-EC-field SBVO + * + * Voltage + */ + Method (SBVO, 0, NotSerialized) + { + Return (B1B2 (VO00, VO01)) + } + + /** + * Method to read the 16 bit-EC-field SBAF + * + * Average Time To Full + */ + Method (SBAF, 0, NotSerialized) + { + Return (B1B2 (AF00, AF01)) + } + + /** + * Method to read the 16 bit-EC-field SBBS + * + * Battery State + */ + Method (SBBS, 0, NotSerialized) + { + Return (B1B2 (BS00, BS01)) + } + + + /** + * Method to read the 16 bit-EC-field SBBM + * + * Battery Mode(w) + */ + Method (SBBM, 0, NotSerialized) + { + Return (B1B2 (BM00, BM01)) + } + + /** + * Method to read the 16 bit-EC-field SBMD + * + * Manufacture Data + */ + Method (SBMD, 0, NotSerialized) + { + Return (B1B2 (MD00, MD01)) + } + + /** + * Method to read the 16 bit-EC-field SBCC + * + * Cycle Count + */ + Method (SBCC, 0, NotSerialized) + { + Return (B1B2 (CC00, CC01)) + } + + + /** + * Method to read the 16 bit-EC-field SBDC + * + * Design Capacity + */ + Method (SBDC, 0, NotSerialized) + { + Return (B1B2 (DC00, DC01)) + } + + /** + * Method to read the 16 bit-EC-field SBDV + * + * Design Voltage + */ + Method (SBDV, 0, NotSerialized) + { + Return (B1B2 (DV00, DV01)) + } + + /** + * Method to read the 16 bit-EC-field SBOM + * + * Optional Mfg Function 1 + */ + Method (SBOM, 0, NotSerialized) + { + Return (B1B2 (OM00, OM01)) + } + + /** + * Method to read the 16 bit-EC-field SBSI + * + * Specification Info + */ + Method (SBSI, 0, NotSerialized) + { + Return (B1B2 (SI00, SI01)) + } + + /** + * Method to read the 16 bit-EC-field SBDT + * + * Manufacture Date + */ + Method (SBDT, 0, NotSerialized) + { + Return (B1B2 (DT00, DT01)) + } + + /** + * Method to read the 16 bit-EC-field SBSN + * + * Serial Number (string) + */ + Method (SBSN, 0, NotSerialized) + { + Local0 = B1B2 (SN00, SN01) + + Local3 = Buffer (0x06) + { + " " + } + + Local2 = 0x04 + + While (Local0) + { + Divide (Local0, 10, Local1, Local0) + Local3 [Local2] = (Local1 + 0x30) + Local2-- + } + + Return (ToString (Local3)) + } + + /** + * Method to read the 32 bit-EC-field SBCH + * + * Device Checmistory (string) + */ + Method (SBCH, 0, NotSerialized) + { + Return (ToString (B1B4 (CH00, CH01, CH02, CH03))) + } + + + /** + * Method to read 128 bit-EC-field SBMN + * + * Manufacture Name (string) + */ + Method (SBMN, 0, NotSerialized) + { + Local0 = Buffer (0x10) {} + + Local0 [0x00] = MN00 + Local0 [0x01] = MN01 + Local0 [0x02] = MN02 + Local0 [0x03] = MN03 + Local0 [0x04] = MN04 + Local0 [0x05] = MN05 + Local0 [0x06] = MN06 + Local0 [0x07] = MN07 + Local0 [0x08] = MN08 + Local0 [0x09] = MN09 + Local0 [0x0A] = MN0A + Local0 [0x0B] = MN0B + Local0 [0x0C] = MN0C + Local0 [0x0D] = MN0D + Local0 [0x0E] = MN0E + Local0 [0x0F] = MN0F + + Return (ToString (Local0)) + } + + /** + * Method to read 128 bit-EC-field SBDN + * + * Device Name (string) + */ + Method (SBDN, 0, NotSerialized) + { + Local0 = Buffer (0x10) {} + + Local0 [0x00] = DN00 + Local0 [0x01] = DN01 + Local0 [0x02] = DN02 + Local0 [0x03] = DN03 + Local0 [0x04] = DN04 + Local0 [0x05] = DN05 + Local0 [0x06] = DN06 + Local0 [0x07] = DN07 + Local0 [0x08] = DN08 + Local0 [0x09] = DN09 + Local0 [0x0A] = DN0A + Local0 [0x0B] = DN0B + Local0 [0x0C] = DN0C + Local0 [0x0D] = DN0D + Local0 [0x0E] = DN0E + Local0 [0x0F] = DN0F + + Return (ToString (Local0)) + } + + + /************************* Helper methods *************************/ + + /** + * Status from two EC fields + * + * e.g. B1B2 (0x3A, 0x03) -> 0x033A + */ + Method (B1B2, 2, NotSerialized) + { + Return ((Arg0 | (Arg1 << 0x08))) + } + + /** + * Status from four EC fields + */ + Method (B1B4, 4, NotSerialized) + { + Local0 = (Arg2 | (Arg3 << 0x08)) + Local0 = (Arg1 | (Local0 << 0x08)) + Local0 = (Arg0 | (Local0 << 0x08)) + + Return (Local0) + } + + + /************************* Battery device *************************/ + + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + /** + * Battery Slot Status + */ + Method (_STA, 0, NotSerialized) + { + // call original _STA for BAT0 and BAT1 + // result is bitwise OR between them + If (_OSI ("Darwin")) + { + If (CondRefOf (^^BAT1._STA) && CondRefOf (^^BAT1._STA)) + { + Return (^^BAT0._STA() | ^^BAT1._STA()) + } + + If (CondRefOf (^^BAT1._STA)) + { + Return (^^BAT1._STA()) + } + + Return (^^BAT0._STA()) + } + + Return (Zero) + } + + Method (_INI, 0, NotSerialized) + { + If (_OSI ("Darwin")) + { + If (CondRefOf (^^BAT0._HID)) + { + // disable original battery objects by setting invalid _HID + ^^BAT0._HID = 0 + } + + If (CondRefOf (^^BAT1._HID)) + { + // disable original battery objects by setting invalid _HID + ^^BAT1._HID = 0 + } + } + } + + + + /** + * Extended Battery Static Information pack layout + */ + Name (PBIX, Package (0x15) { + 0x01, // 0x00: BIXRevision - Revision - Integer + 0x01, // 0x01: BIXPowerUnit - Power Unit: mAh - Integer (DWORD) + // ACPI spec : 0 - mWh : 1 - mAh + // We are always outputting mAh. + 0xFFFFFFFF, // 0x02: BIXDesignCapacity - Design Capacity - Integer (DWORD) + 0xFFFFFFFF, // 0x03: BIXLastFullChargeCapacity - Last Full Charge Capacity - Integer (DWORD) + 0x01, // 0x04: BIXBatteryTechnology - Battery Technology: Rechargeable - Integer (DWORD) + 0xFFFFFFFF, // 0x05: BIXDesignVoltage - Design Voltage - Integer (DWORD) + 0xFFFFFFFF, // 0x06: BIXDesignCapacityOfWarning - Design Capacity of Warning - Integer (DWORD) + 0xFFFFFFFF, // 0x07: BIXDesignCapacityOfLow - Design Capacity of Low - Integer (DWORD) + 0xFFFFFFFF, // 0x08: BIXCycleCount - Cycle Count - Integer (DWORD) + 0x00017318, // 0x09: BIXMeasurementAccuracy - Measurement Accuracy (98.3%?) - Integer (DWORD) + 0xFFFFFFFF, // 0x0a: BIXMaxSamplingTime - Max Sampling Time (500ms) - Integer (DWORD) + 0xFFFFFFFF, // 0x0b: BIXMinSamplingTime - Min Sampling Time (10ms) - Integer (DWORD) + 1000, // 0x0c: BIXMaxAveragingInterval - Max Averaging Interval - Integer (DWORD) + 500, // 0x0d: BIXMinAveragingInterval - Min Averaging Interval - Integer (DWORD) + 0xFFFFFFFF, // 0x0e: BIXBatteryCapacityGranularity1 - Capacity Granularity 1 + 0xFFFFFFFF, // 0x0f: BIXBatteryCapacityGranularity2 - Capacity Granularity 2 + "", // 0x10: BIXModelNumber - Model Number - String + "", // 0x11: BIXSerialNumber - Serial Number - String + "", // 0x12: BIXBatteryType - Battery Type - String + "", // 0x13: BIXOEMInformation - OEM Information - String + 0x00 // 0x14: ??? - Battery Swapping Capability, 0x00000000 = non-swappable - Integer (DWORD) + // added in Revision 1: Zero means Non-swappable, One - Cold-swappable, 0x10 - Hot-swappable + }) + + Name (BX0I, Package (0x15) {}) + Name (BX1I, Package (0x15) {}) + + /** + * Get Battery extended information per battery + * + * Arg0: Battery id 0x00 / 0x10 + * Arg1: Battery Real-time Information pack + */ + Method (GBIX, 2, NotSerialized) + { + // Wait for the battery to become available + If (Arg0 == 0x10) + { + // use BAT1 + Local4 = HB1S + Local5 = HB1A + } + Else + { + // use BAT0 + Local4 = HB0S + Local5 = HB0A + } + + Local6 = 10 + Local7 = Zero + + While ((!Local7 && Local6)) + { + // If battery available + If (Local5) + { + // If battery ok + If (((Local4 & 0x07) == 0x07)) + { + // decrease timer and wait for battery to be ready + Sleep (1000) + Local6-- + } + Else + { + // Battery error + Local7 = One + } + } + Else + { + // battery unavailable, not need to wait + Local6 = Zero + } + } + + // Battery not ready, give up for now + If (Local7 != One) + { + Debug = "BATX:GBIX: !!!WARNING: Could not get battery-data in time. Giving up for now. - WARNING!!!" + + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x03] = 0xFFFFFFFF + Arg1 [0x06] = 0x00 + Arg1 [0x07] = 0x00 + + Return (Arg1) + } + + // Aquire Mutex + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in GBIX" + + Return (Arg1) + } + + + // + // Information Page 1 - + // + HIID = (Arg0 | 0x01) + + // cycle count + Arg1 [0x08] = SBCC /* \_SB_.PCI0.LPCB.EC__.BATX.SBCC */ + + // needs conversion? + Local7 = SBBM /* \_SB_.PCI0.LPCB.EC__.BATX.SBBM */ + Local7 >>= 0x0F + Arg1 [0x01] = (Local7 ^ 0x01) + + + // + // Information Page 0 - + // + HIID = Arg0 + + If (Local7) + { + Local1 = (SBFC * 10) + } + Else + { + Local1 = SBFC /* \_SB_.PCI0.LPCB.EC__.BATX.SBFC */ + } + + Arg1 [0x03] = Local1 + + + // + // Information Page 2 - + // + HIID = (Arg0 | 0x02) + + // Design capacity + If (Local7) + { + Local0 = (SBDC * 10) + } + Else + { + Local0 = SBDC /* \_SB_.PCI0.LPCB.EC__.BATX.SBDC */ + } + + Arg1 [0x02] = Local0 + + // Design capacity of high at 10%, values of VirtualSMC + Arg1 [0x06] = Local0 / 100 * 10 + + // Design capacity of low at 5%, values of VirtualSMC + Arg1 [0x07] = Local0 / 100 * 5 + + // Design voltage + Arg1 [0x05] = SBDV /* \_SB_.PCI0.LPCB.EC__.BATX.SBDV */ + + // Serial Number + Arg1 [0x11] = SBSN /* \_SB_.PCI0.LPCB.EC__.BATX.SBSN */ + + + // + // Information Page 6 - + // + HIID = (Arg0 | 0x06) + + // Model Number - Device Name + Arg1 [0x10] = SBDN /* \_SB_.PCI0.LPCB.EC__.BATX.SBDN */ + + + // + // Information Page 4 - + // + HIID = (Arg0 | 0x04) + + // Battery Type - Device Chemistry + Arg1 [0x12] = SBCH /* \_SB_.PCI0.LPCB.EC__.BATX.SBCH */ + + + // + // Information Page 5 - + // + HIID = (Arg0 | 0x05) + + // OEM Information - Manufacturer Name + Arg1 [0x13] = SBMN /* \_SB_.PCI0.LPCB.EC__.BATX.SBMN */ + + // Release mutex + Release (BAXM) + + // Return result + Return (Arg1) + } + + /** + * Acpi-Spec: + * 10.2.2.2 _BIX (Battery Information Extended) + * The _BIX object returns the static portion of the Control Method Battery information. This information + * remains constant until the battery is changed. The _BIX object returns all information available via the + * _BIF object plus additional battery information. The _BIF object is deprecated in lieu of _BIX in ACPI 4.0 + */ + Method (_BIX, 0, NotSerialized) // _BIX: Battery Information Extended + { + Debug = "BATX:_BIX" + + // needs to be run in any way as it waits for the bat-device to be available + BX0I = GBIX (0x00, PBIX) + + // If BAT0 present and debugging enabled + If (HB0A && BDBG == One) + { + Concatenate ("BATX:BIXPowerUnit: BAT0 ", BX0I[0x01], Debug) + Concatenate ("BATX:BIXDesignCapacity: BAT0 ", ToDecimalString (DerefOf (BX0I [0x02])), Debug) + Concatenate ("BATX:BIXLastFullChargeCapacity: BAT0 ", ToDecimalString (DerefOf (BX0I [0x03])), Debug) + Concatenate ("BATX:BIXBatteryTechnology: BAT0 ", ToDecimalString (DerefOf (BX0I [0x04])), Debug) + Concatenate ("BATX:BIXDesignVoltage: BAT0 ", ToDecimalString(DerefOf (BX0I [0x05])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfWarning: BAT0 ", ToDecimalString (DerefOf (BX0I [0x06])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfLow: BAT0 ", ToDecimalString (DerefOf (BX0I [0x07])), Debug) + Concatenate ("BATX:BIXCycleCount: BAT0 ", ToDecimalString (DerefOf (BX0I [0x08])), Debug) + Concatenate ("BATX:BIXModelNumber: BAT0 ", DerefOf (BX0I [0x10]), Debug) + Concatenate ("BATX:BIXSerialNumber: BAT0 ", DerefOf (BX0I [0x11]), Debug) + Concatenate ("BATX:BIXBatteryType: BAT0 ", DerefOf (BX0I [0x12]), Debug) + Concatenate ("BATX:BIXOEMInformation: BAT0 ", DerefOf (BX0I [0x13]), Debug) + } + + // If BAT1 is not available, simply return data from BAT0 + If (!HB1A) + { + Return (BX0I) + } + + // Get data from BAT1 + BX1I = GBIX (0x10, PBIX) + + // If BAT1 present and debugging enabled + If (BDBG == One) + { + Concatenate ("BATX:BIXPowerUnit: BAT1 ", BX1I[0x01], Debug) + Concatenate ("BATX:BIXDesignCapacity: BAT1 ", ToDecimalString (DerefOf (BX1I [0x02])), Debug) + Concatenate ("BATX:BIXLastFullChargeCapacity: BAT1 ", ToDecimalString (DerefOf (BX1I [0x03])), Debug) + Concatenate ("BATX:BIXBatteryTechnology: BAT1 ", ToDecimalString (DerefOf (BX1I [0x04])), Debug) + Concatenate ("BATX:BIXDesignVoltage: BAT1 ", ToDecimalString(DerefOf (BX1I [0x05])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfWarning: BAT1 ", ToDecimalString (DerefOf (BX1I [0x06])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfLow: BAT1 ", ToDecimalString (DerefOf (BX1I [0x07])), Debug) + Concatenate ("BATX:BIXCycleCount: BAT1 ", ToDecimalString (DerefOf (BX1I [0x08])), Debug) + Concatenate ("BATX:BIXModelNumber: BAT1 ", DerefOf (BX1I [0x10]), Debug) + Concatenate ("BATX:BIXSerialNumber: BAT1 ", DerefOf (BX1I [0x11]), Debug) + Concatenate ("BATX:BIXBatteryType: BAT1 ", DerefOf (BX1I [0x12]), Debug) + Concatenate ("BATX:BIXOEMInformation: BAT1 ", DerefOf (BX1I [0x13]), Debug) + } + + // If BAT1 available and BAT0 not, return data from BAT1. Very unlikely. + If (!HB0A) + { + Return (BX1I) + } + + + // PowerUnits differ between both batteries. This case isn't handled in SSDT-BATX atm. Please report a bug. + If (DerefOf (BX0I [0x01]) != DerefOf (BX1I [0x01])) + { + Debug = "BATX:BIXPowerUnit: !!!WARNING: PowerUnits differ between batteries. This case isn't handled in SSDT-BATX atm. Please report a bug - WARNING!!!" + } + + + // combine batteries into Local0 if both present + Local0 = BX0I + + // _BIX 0 Revision - leave BAT0 value + + // _BIX 1 Power Unit - leave BAT0 value + + // _BIX 2 Design Capacity - add BAT0 and BAT1 values + Local0 [0x02] = DerefOf (BX0I [0x02]) + DerefOf (BX1I [0x02]) + + // _BIX 3 Last Full Charge Capacity - add BAT0 and BAT1 values + Local0 [0x03] = DerefOf (BX0I [0x03]) + DerefOf (BX1I [0x03]) + + // _BIX 4 Battery Technology - leave BAT0 value + + // _BIX 5 Design Voltage - average between BAT0 and BAT1 values + Local0 [0x05] = (DerefOf (BX0I [0x05]) + DerefOf (BX1I [0x05])) / 2 + + // _BIX 6 Design Capacity of Warning - add BAT0 and BAT1 values + Local0 [0x06] = DerefOf (BX0I [0x06]) + DerefOf (BX1I [0x06]) + + // _BIX 7 Design Capacity of Low - add BAT0 and BAT1 values + Local0 [0x07] = DerefOf (BX0I [0x07]) + DerefOf (BX1I [0x07]) + + // _BIX 8 Cycle Count - average between BAT0 and BAT1 values + Local0 [0x08] = (DerefOf (BX0I [0x08]) + DerefOf (BX1I [0x08])) / 2 + + // _BIX 10 Model Number - concatenate BAT0 and BAT1 values + Local0 [0x10] = Concatenate (Concatenate (DerefOf (BX0I [0x10]), " / "), DerefOf (BX1I [0x10])) + + // _BIX 11 Serial Number - concatenate BAT0 and BAT1 values + Local0 [0x11] = Concatenate (Concatenate (DerefOf (BX0I [0x11]), " / "), DerefOf (BX1I [0x11])) + + // _BIX 12 Battery Type - concatenate BAT0 and BAT1 values + Local0 [0x12] = Concatenate (Concatenate (DerefOf (BX0I [0x12]), " / "), DerefOf (BX1I [0x12])) + + // _BIX 13 OEM Information - concatenate BAT0 and BAT1 values + Local0 [0x13] = Concatenate (Concatenate (DerefOf (BX0I [0x13]), " / "), DerefOf (BX1I [0x13])) + + If (BDBG == One) + { + Concatenate ("BATX:BIXPowerUnit: BATX ", Local0 [0x01], Debug) + Concatenate ("BATX:BIXDesignCapacity: BATX ", ToDecimalString (DerefOf (Local0 [0x02])), Debug) + Concatenate ("BATX:BIXLastFullChargeCapacity: BATX ", ToDecimalString (DerefOf (Local0 [0x03])), Debug) + Concatenate ("BATX:BIXBatteryTechnology: BATX ", ToDecimalString (DerefOf (Local0 [0x04])), Debug) + Concatenate ("BATX:BIXDesignVoltage: BATX ", ToDecimalString(DerefOf (Local0 [0x05])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfWarning: BATX ", ToDecimalString (DerefOf (Local0 [0x06])), Debug) + Concatenate ("BATX:BIXDesignCapacityOfLow: BATX ", ToDecimalString (DerefOf (Local0 [0x07])), Debug) + Concatenate ("BATX:BIXCycleCount: BATX ", ToDecimalString (DerefOf (Local0 [0x08])), Debug) + Concatenate ("BATX:BIXModelNumber: BATX ", DerefOf (Local0 [0x10]), Debug) + Concatenate ("BATX:BIXSerialNumber: BATX ", DerefOf (Local0 [0x11]), Debug) + Concatenate ("BATX:BIXBatteryType: BATX ", DerefOf (Local0 [0x12]), Debug) + Concatenate ("BATX:BIXOEMInformation: BATX ", DerefOf (Local0 [0x13]), Debug) + } + + Return (Local0) + } + + + /** + * Battery Real-time Information pack layout + */ + Name (PBST, Package (0x04) + { + 0x00000000, // 0x00: BSTState - Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // 0x01: BSTPresentRate - Battery Present Rate [mW], 0xFFFFFFFF if unknown rate + 0, // 0x02: BSTRemainingCapacity - Battery Remaining Capacity [mWh], 0xFFFFFFFF if unknown capacity + 0, // 0x03: BSTPresentVoltage - Battery Present Voltage [mV], 0xFFFFFFFF if unknown voltage + }) + + Name (BT0P, Package (0x04) {}) // Cache of PBST for BAT0 + Name (BT1P, Package (0x04) {}) // Cache of PBST for BAT1 + + /** + * Get Battery Status per battery + * + * Arg0: Battery id 0x00 / 0x10 + * Arg1: Battery Real-time Information pack + */ + Method (GBST, 2, NotSerialized) + { + // Aquire mutex + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in GBST" + + Return (Arg1) + } + + If (Arg0 == 0x00) + { + Local6 = HB0S + } + Else + { + Local6 = HB1S + } + + // Not charging + Local0 = 0x00 + + If ((Local6 & 0x20) == 0x20) + { + // 2 = Charging + Local0 = 0x02 + } + ElseIf ((Local6 & 0x40) == 0x40) + { + // 1 = Discharging + Local0 = 0x01 + } + + + // + // Information Page 1 - + // + HIID = (Arg0 | 0x01) + + // needs conversion? + Local7 = SBBM /* \_SB_.PCI0.LPCB.EC__.BATX.SBBM */ + Local7 >>= 0x0F + + + // + // Information Page 0 - + // + HIID = Arg0 + + // + Local2 = SBRC /* \_SB_.PCI0.LPCB.EC__.BATX.SBRC */ + + If (Local7) + { + Local2 = (Local2 * 10) + } + + // Present rate is a 16bit signed int, positive while charging + // and negative while discharging. + Local1 = SBAC /* \_SB_.PCI0.LPCB.EC__.BATX.SBAC */ + + If ((Local1 >= 0x8000)) + { + // If discharging + If ((Local0 & 0x01) == 0x01) + { + // Negate present rate + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = 0x00 + } + } + ElseIf (!(Local0 & 0x02) == 0x02) + { + Local1 = 0x00 + } + + // Get voltage + Local3 = SBVO /* \_SB_.PCI0.LPCB.EC__.BATX.SBVO */ + + // Needs conversion + If (Local7) + { + Local1 = (Local1 * Local3 / 1000) + } + + // Set data + Arg1 [0x00] = Local0 + Arg1 [0x01] = Local1 + Arg1 [0x02] = Local2 + Arg1 [0x03] = Local3 + + // Release mutex + Release (BAXM) + + // Return data + Return (Arg1) + } + + /** + * Battery availability info + */ + Name (PBAI, Package () + { + 0xFF, // 0x00: BAT0 present or not + 0xFF, // 0x01: BAT1 present or not + }) + + /** + * Battery status + */ + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Debug = "BATX:_BST()" + + // Check if battery is added or removed + Local3 = DerefOf (PBAI [0x00]) + Local4 = DerefOf (PBAI [0x01]) + + If (Local3 != HB0A || Local4 != HB1A) + { + PBAI [0x00] = HB0A + PBAI [0x01] = HB1A + + If (Local3 != 0xFF || Local4 != 0xFF) + { + If (BDBG == One) + { + Concatenate ("BATX:_BST() - PBAI:HB0A (old): ", Local3, Debug) + Concatenate ("BATX:_BST() - PBAI:HB1A (old): ", Local4, Debug) + Concatenate ("BATX:_BST() - PBAI:HB0A (new): ", HB0A, Debug) + Concatenate ("BATX:_BST() - PBAI:HB1A (new): ", HB1A, Debug) + } + + // + // Here we actually would need an option to tell VirtualSMC to refresh the static battery data + // because a battery was dettached or attached. + // + Notify (BATX, 0x81) // Status Change + } + } + + // gather battery data from BAT0 if available + If (HB0A) + { + BT0P = GBST (0x00, PBST) + + If (BDBG == One) + { + Concatenate ("BATX:BSTState: BAT0 (acpi) - ", HB0S, Debug) + Concatenate ("BATX:BSTState: BAT0 ", DerefOf (BT0P [0x00]), Debug) + Concatenate ("BATX:BSTPresentRate: BAT0 ", ToDecimalString (DerefOf (BT0P [0x01])), Debug) + Concatenate ("BATX:BSTRemainingCapacity: BAT0 ", ToDecimalString (DerefOf (BT0P [0x02])), Debug) + Concatenate ("BATX:BSTPresentVoltage: BAT0 ", ToDecimalString (DerefOf (BT0P [0x03])), Debug) + } + + // If BAT1 isn't available, simply return data from BAT0 + If (!HB1A) + { + Return (BT0P) + } + } + + + // gather battery data from BAT1 + BT1P = GBST (0x10, PBST) + + If (BDBG == One) + { + Concatenate ("BATX:BSTState: BAT1 (acpi) - ", HB1S, Debug) + Concatenate ("BATX:BSTState: BAT1 ", DerefOf (BT1P [0x00]), Debug) + Concatenate ("BATX:BSTPresentRate: BAT1 ", ToDecimalString (DerefOf (BT1P [0x01])), Debug) + Concatenate ("BATX:BSTRemainingCapacity: BAT1 ", ToDecimalString (DerefOf (BT1P [0x02])), Debug) + Concatenate ("BATX:BSTPresentVoltage: BAT1 ", ToDecimalString (DerefOf (BT1P [0x03])), Debug) + } + + // If BAT1 is availble but BAT0 isn't, simply return data from BAT1. Very unlikely. + If (!HB0A) + { + Return (BT1P) + } + + // combine batteries into Local0 result if possible + Local0 = BT0P + + // _BST 0 - Battery State - if one battery is charging, then charging, else discharging + Local4 = DerefOf (BT0P [0x00]) + Local5 = DerefOf (BT1P [0x00]) + + If (Local4 != Local5) + { + If (((Local4 & 0x02) == 0x02) || ((Local5 & 0x02) == 0x02)) + { + // 2 = Charging + Local0 [0x00] = 0x02 + } + ElseIf (((Local4 & 0x01) == 0x01) || ((Local5 & 0x01) == 0x01)) + { + // 1 = Discharging + Local0 [0x00] = 0x01 + } + } + + // _BST 1 - Battery Present Rate - add BAT0 and BAT1 values + Local0 [0x01] = DerefOf (BT0P [0x01]) + DerefOf (BT1P [0x01]) + + // _BST 2 - Battery Remaining Capacity - add BAT0 and BAT1 values + Local0 [0x02] = DerefOf (BT0P [0x02]) + DerefOf (BT1P [0x02]) + + // _BST 3 - Battery Present Voltage - average between BAT0 and BAT1 values + Local0 [0x03] = (DerefOf (BT0P [0x03]) + DerefOf (BT1P [0x03])) / 2 + + If (BDBG == One) + { + Concatenate ("BATX:BSTState: BATX ", DerefOf (Local0 [0x00]), Debug) + Concatenate ("BATX:BSTPresentRate: BATX ", ToDecimalString (DerefOf (Local0 [0x01])), Debug) + Concatenate ("BATX:BSTRemainingCapacity: BATX ", ToDecimalString (DerefOf (Local0 [0x02])), Debug) + Concatenate ("BATX:BSTPresentVoltage: BATX ", ToDecimalString (DerefOf (Local0 [0x03])), Debug) + } + + // Return combined battery + Return (Local0) + } + + + + /** + * Battery Status Supplement pack layout + */ + Name (PBSS, Package (0x07) + { + 0xFFFFFFFF, // 0x00: BSSTemperature - Temperature, AppleSmartBattery format + 0xFFFFFFFF, // 0x01: BSSTimeToFull - TimeToFull [minutes] (0xFF) + 0xFFFFFFFF, // 0x02: BSSTimeToEmpty - TimeToEmpty [minutes] (0) + 0xFFFFFFFF, // 0x03: BSSChargeLevel - ChargeLevel [percent] + 0xFFFFFFFF, // 0x04: BSSAverageRate - AverageRate [mA] (signed) + 0xFFFFFFFF, // 0x05: BSSChargingCurrent - ChargingCurrent [mA] + 0xFFFFFFFF, // 0x06: BSSChargingVoltage - ChargingVoltage [mV] + }) + + Name (PBS0, Package (0x07) {}) + Name (PBS1, Package (0x07) {}) + + /** + * Get Battery Status Supplement per battery + * + * Arg0: Battery 0x00/0x10 + * Arg1: package + */ + Method (GBSS, 2, NotSerialized) + { + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in GBSS" + + Return (PBSS) + } + + // + // Information Page 0 - + // + HIID = Arg0 + + // 0x01: TimeToFull (0x11), minutes (0xFF) + Local6 = SBAF + + If (Local6 == 0xFFFF) + { + Local6 = 0 + } + + Arg1 [0x01] = Local6 + + // 0x02: TimeToEmpty (0x12), minutes (0) + Local6 = SBAE + + If (Local6 == 0xFFFF) + { + Local6 = 0 + } + + Arg1 [0x02] = Local6 + + // 0x03: BSSChargeLevel - ChargeLevel, percentage + Arg1 [0x03] = SBRS + + // 0x04: AverageRate (0x14), mA (signed) + Arg1 [0x04] = SBAC + + // 0x05: ChargingCurrent (0x15), mA, seems to be unused anyways + // Arg1 [0x05] = ??? + + // 0x06: ChargingVoltage (0x16), mV, seems to be unused anyways + // Arg1 [0x06] = ??? + + // Fake Temperature (0x10) to 30C as it isn't available from the EC, AppleSmartBattery format + Arg1 [0x00] = 0xBD7 + + Release (BAXM) + + Return (Arg1) + } + + /** + * Battery Status Supplement + */ + Method (CBSS, 0, NotSerialized) + { + Debug = "BATX:CBSS()" + + If (!H8DR) + { + Return (PBSS) + } + + If (HB0A) + { + PBS0 = GBSS (0x00, PBSS) + + If (BDBG == One) + { + Concatenate ("BATX:BSSTimeToFull: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BAT0 ", ToDecimalString (DerefOf (PBS0 [0x04])), Debug) + } + + If (!HB1A) + { + Return (PBS0) + } + } + + // gather battery data from BAT1 + PBS1 = GBSS (0x10, PBSS) + + If (BDBG == One) + { + Concatenate ("BATX:BSSTimeToFull: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BAT1 ", ToDecimalString (DerefOf (PBS1 [0x04])), Debug) + } + + If (!HB0A) + { + Return (PBS1) + } + + // combine batteries into Local0 result if possible + Local0 = PBS0 + + // 0x01: TimeToFull (0x11), minutes (0xFF), Valid integer in minutes + Local0 [0x01] = (DerefOf (PBS0 [0x01]) + DerefOf (PBS1 [0x01])) + + // 0x02: BSSTimeToEmpty - TimeToEmpty, minutes (0), Valid integer in minutes + Local0 [0x02] = (DerefOf (PBS0 [0x02]) + DerefOf (PBS1 [0x02])) + + // 0x03: BSSChargeLevel - ChargeLevel, percentage, 0 - 100 for percentage. + Local0 [0x03] = (DerefOf (PBS0 [0x03]) + DerefOf (PBS1 [0x03])) / 2 + + // 0x04: BSSAverageRate - AverageRate, mA (signed), Valid signed integer in mA. + Local0 [0x04] = (DerefOf (PBS0 [0x04]) + DerefOf (PBS1 [0x04])) + + If (BDBG == One) + { + Concatenate ("BATX:BSSTimeToFull: BATX ", ToDecimalString (DerefOf (Local0 [0x01])), Debug) + Concatenate ("BATX:BSSTimeToEmpty: BATX ", ToDecimalString (DerefOf (Local0 [0x02])), Debug) + Concatenate ("BATX:BSSChargeLevel: BATX ", ToDecimalString (DerefOf (Local0 [0x03])), Debug) + Concatenate ("BATX:BSSAverageRate: BATX ", ToDecimalString (DerefOf (Local0 [0x04])), Debug) + } + + Return (Local0) + } + + + + /** + * Battery Information Supplement pack layout + */ + Name (PBIS, Package (0x07) + { + // 0x006F007F, // 0x00: BISConfig - config, double check if you have valid AverageRate before + // fliping that bit to 0x007F007F since it will disable quickPoll + 0x007F007F, // disable quickpoll + 0xFFFFFFFF, // 0x01: BISManufactureDate - ManufactureDate (0x1), AppleSmartBattery format + 0x00002342, // 0x02: BISPackLotCode - PackLotCode + 0x00002342, // 0x03: BISPCBLotCode - PCBLotCode + 0x00002342, // 0x04: BISFirmwareVersion - FirmwareVersion + 0x00002342, // 0x05: BISHardwareVersion - HardwareVersion + 0x00002342, // 0x06: BISBatteryVersion - BatteryVersion + }) + + /** + * Battery Information Supplement + */ + Method (CBIS, 0, NotSerialized) + { + Debug = "BATX:CBIS()" + + If (!H8DR) + { + Return (PBIS) + } + + If (Acquire (BAXM, 65535)) + { + Debug = "BATX:AcquireLock failed in CBIS" + + Return (PBIS) + } + + + // + // Information Page 2 - + // + HIID = (0x00 | 0x02) + + // 0x01: ManufactureDate (0x1), AppleSmartBattery format + PBIS [0x01] = SBDT + + Release (BAXM) + + Return (PBIS) + } + } + } +} +//EOF diff --git a/patches/SSDT-DMAC.dsl b/patches/SSDT-DMAC.dsl index 0843d84..b081ab5 100755 --- a/patches/SSDT-DMAC.dsl +++ b/patches/SSDT-DMAC.dsl @@ -1,51 +1,60 @@ -//Add DMAC -DefinitionBlock ("", "SSDT", 2, "tyler", "DMAC", 0) +/* + * Fix up memory controller + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_DMAC", 0x00001000) { - External(_SB.PCI0.LPCB, DeviceObj) + External (OSDW, MethodObj) // 0 Arguments + External (_SB.PCI0.LPCB, DeviceObj) + + // https://github.com/daliansky/OC-little/blob/master/06-%E6%B7%BB%E5%8A%A0%E7%BC%BA%E5%A4%B1%E7%9A%84%E9%83%A8%E4%BB%B6/SSDT-DMAC.dsl Scope (_SB.PCI0.LPCB) { + // https://github.com/khronokernel/DarwinDumped/blob/b6d91cf4a5bdf1d4860add87cf6464839b92d5bb/MacBookPro/MacBookPro14%2C1/ACPI%20Tables/DSL/DSDT.dsl#L5044 + // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/acpi/acpi/lpc.asl + /* DMA Controller */ Device (DMAC) { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () + Name (_HID, EISAID("PNP0200")) + + Name (_CRS, ResourceTemplate() { - IO (Decode16, - 0x0000, // Range Minimum - 0x0000, // Range Maximum - 0x01, // Alignment - 0x20, // Length - ) - IO (Decode16, - 0x0081, // Range Minimum - 0x0081, // Range Maximum - 0x01, // Alignment - 0x11, // Length - ) - IO (Decode16, - 0x0093, // Range Minimum - 0x0093, // Range Maximum - 0x01, // Alignment - 0x0D, // Length - ) - IO (Decode16, - 0x00C0, // Range Minimum - 0x00C0, // Range Maximum - 0x01, // Alignment - 0x20, // Length - ) - DMA (Compatibility, NotBusMaster, Transfer8_16, ) - {4} + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } }) + Method (_STA, 0, NotSerialized) { - If (_OSI ("Darwin")) + If (OSDW ()) { Return (0x0F) } - Else + + Return (Zero) + } + } + + /* FPU / MATH */ + Device(MAT0) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + + Method (_STA, 0, NotSerialized) + { + If (OSDW ()) { - Return (Zero) + Return (0x0F) } + + Return (Zero) } } } diff --git a/patches/SSDT-Darwin.dsl b/patches/SSDT-Darwin.dsl new file mode 100644 index 0000000..405f737 --- /dev/null +++ b/patches/SSDT-Darwin.dsl @@ -0,0 +1,51 @@ +/* + * Detect Darwin (OSX) to enable other patches + * Credits @osy86 + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_Darwin", 0) +{ + Method (DTGP, 5, NotSerialized) + { + If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b"))) + { + If ((Arg1 == One)) + { + If ((Arg2 == Zero)) + { + Arg4 = Buffer (One) + { + 0x03 + } + Return (One) + } + + If ((Arg2 == One)) + { + Return (One) + } + } + } + + Arg4 = Buffer (One) + { + 0x00 + } + Return (Zero) + } + + Scope (\) + { + Method (OSDW, 0, NotSerialized) + { + If (CondRefOf (\_OSI, Local0)) + { + If (_OSI ("Darwin")) + { + Return (One) // is Darwin + } + } + Return (Zero) + } + } +} \ No newline at end of file diff --git a/patches/SSDT-EC.dsl b/patches/SSDT-EC.dsl new file mode 100644 index 0000000..9646476 --- /dev/null +++ b/patches/SSDT-EC.dsl @@ -0,0 +1,439 @@ +/* + * + * Neccessary dependcies to read from the machine's embedded controller. This patch is specific to the x1c6, and to a larger extent, ThinkPads. Not to be confused with Dortania's SSDT-EC.dsl + * + * For use with YogaSMC.kext and App + * https://github.com/zhen-zen/YogaSMC + * + * Credits @benbender @zhen-zen + */ + +/* + https://github.com/coreboot/coreboot/blob/master/src/ec/quanta/it8518/acpi/ec.asl + Memory layout of X1C6-embedded controller as far as known: + OperationRegion (ECOR, EmbeddedControl, 0x00, 0x0100) + Field (ECOR, ByteAcc, NoLock, Preserve) + { + HDBM, 1, + , 1, + , 1, + HFNE, 1, // Enable Sticky Fn Key + , 1, + , 1, + HLDM, 1, + Offset (0x01), // [Configuration Space 1] + BBLS, 1, + BTCM, 1, + , 1, + , 1, + , 1, + HBPR, 1, + BTPC, 1, + Offset (0x02), // [Configuration Space 2] + HDUE, 1, + , 4, + SNLK, 1, + Offset (0x03), // [Configuration Space 3] + , 5, + HAUM, 2, + Offset (0x05), // [Sound Mask 1] + HSPA, 1, // power off alarm + Offset (0x06), // [Sound ID (Write only)] + HSUN, 8, // Sound ID (Write Only) + Offset(0x07), // [Sound Repeat Interval (unit time 125ms)] + HSRP, 8, // Sound Repeat Interval (Unit time : 125ms ) + Offset (0x0C), // [LED On/Off/ Blinking Control (Write only)] + HLCL, 4, // 0: power LED + // 1: battery status 0 + // 2: battery status 1 + // 3: additional Bay LED (Venice) / reserved (Toronto-4) / Slicer LED (Tokyo) + // 4-6: reserved + // 7: suspend LED + // 8: dock LED 1 + // 9: dock LED 2 + // 10-13: reserved + // 14: microphone mute + // 15: reserved + , 4, + CALM, 1, + Offset (0x0E), // [Peripheral Status 4] + HFNS, 2, // Bit[1, 0] : Fn Key Status + // [0, 0] ... Unlock + // [0, 1] ... Sticky + // [1, 0] ... Lock + // [1, 1] ... Reserved + Offset (0x0F), // [Peripheral status 5 (read only)] ? + , 6, + NULS, 1, + Offset (0x10), // [Attention Mask (00-127)] + HAM0, 8, // 10 : Attention Mask (00-07) + HAM1, 8, // 11 : Attention Mask (08-0F) + HAM2, 8, // 12 : Attention Mask (10-17) + HAM3, 8, // 13 : Attention Mask (18-1F) + HAM4, 8, // 14 : Attention Mask (20-27) + HAM5, 8, // 15 : Attention Mask (28-2F) + HAM6, 8, // 16 : Attention Mask (30-37) + HAM7, 8, // 17 : Attention Mask (38-3F) + HAM8, 8, // 18 : Attention Mask (40-47) + HAM9, 8, // 19 : Attention Mask (48-4F) + HAMA, 8, // 1A : Attention Mask (50-57) + HAMB, 8, // 1B : Attention Mask (58-5F) + HAMC, 8, // 1C : Attention Mask (60-67) + HAMD, 8, // 1D : Attention Mask (68-6F) + HAME, 8, // 1E : Attention Mask (70-77) + HAMF, 8, // 1F : Attention Mask (78-7F) + Offset (0x23), // [Misc. control] + HANT, 8, + Offset (0x26), + , 2, + HANA, 2, + Offset (0x27), // [Passward Scan Code] + Offset (0x28), + , 1, + SKEM, 1, + Offset (0x29), + Offset (0x2A), // [Attention Request] + HATR, 8, // 2A : Attention request + Offset(0x2B), // [Trip point of battery capacity] + HT0H, 8, // 2B : MSB of Trip Point Capacity for Battery 0 + HT0L, 8, // 2C : LSB of Trip Point Capacity for Battery 0 + HT1H, 8, // 2D : MSB of Trip Point Capacity for Battery 1 + HT1L, 8, // 2E : LSB of Trip Point Capacity for Battery 1 + Offset(0x2F), // [Fan Speed Control] + HFSP, 8, // bit 2-0: speed (0: stop, 7:highest speed) + // bit 5-3: reserved (should be 0) + // bit 6: max. speed + // bit 7: Automatic mode (fan speed controlled by thermal level) + Offset(0x30), // [Audio mute control] + , 7, // Reserved bits[0:6] + SMUT, 1, // Mute + Offset (0x31), // [Peripheral Control 2] + FANS, 2, // bit 0,1 Fan selector ? + // 00: Fan 1, 01: Fan 2 ? + HUWB, 1, // UWB on + , 3, + VPON, 1, + VRST, 1, + Offset(0x32), // [EC Event Mask 0] + HWPM, 1, // PME : Not used. PME# is connected to GPE directly. + HWLB, 1, // Critical Low Bat + HWLO, 1, // Lid Open + HWDK, 1, + HWFN, 1, // FN key + HWBT, 1, + HWRI, 1, // Ring Indicator (UART) + HWBU, 1, // Bay Unlock + HWLU, 1, + Offset (0x34), + , 3, + PIBS, 1, + , 3, + HPLO, 1, + Offset (0x36), + HWAC, 16, + Offset(0x38), // [Battery 0 status (read only)] + HB0S, 7, // bit 3-0 level + // F: Unknown + // 2-n: battery level + // 1: low level + // 0: (critical low battery, suspend/ hibernate) + // bit 4 error + // bit 5 charge + // bit 6 discharge + HB0A, 1, // bit 7 battery attached + Offset(0x39), // [Battery 1 status (read only)] + // bit definition is the same as offset(0x38) + Offset(0x3A), // [Peripheral control 0] + HCMU, 1, // Mute + , 2, + OVRQ, 1, + DCBD, 1, // Bluetooth On + DCWL, 1, // Wireless Lan On + DCWW, 1, // Wireless Wan On + HB1I, 1, + Offset(0x3B), // [Peripheral control 1] + , 1, // Speaker Mute + KBLT, 1, // Keyboard Light + BTPW, 1, + FNKC, 1, + HUBS, 1, + BDPW, 1, // Bluetooth power? + BDDT, 1, // Bluetooth detach? + HUBB, 1, + Offset(0x3C), // [Resume reason (Read only)] + Offset(0x3D), // [Password Control byte] + Offset(0x3E), // [Password data (8 byte)~ offset:45h] + Offset (0x46), // [sense status 0] + , 1, + BTWK, 1, + HPLD, 1, // LID open + , 1, + HPAC, 1, // External power (AC status) + BTST, 1, + PSST, 1, + Offset (0x47), // [sense status 1] + HPBU, 1, // Bay Unlock + , 1, + HBID, 1, + , 3, + HBCS, 1, + HPNF, 1, + Offset(0x48), // [sense status 2] + , 1, + GSTS, 1, // Global Wan Enable Switch + , 2, + HLBU, 1, + DOCD, 1, + HCBL, 1, + Offset (0x49), // [sense status 3] + SLUL, 1, + , 1, + ACAT, 1, + , 4, + ELNK, 1, + Offset (0x4C), // [MSB of Event Timer] + HTMH, 8, + HTML, 8, + HWAK, 16, + HMPR, 8, + , 7, + HMDN, 1, + Offset (0x78), // [Temperature of thermal sensor 0 (centigrade)] + TMP0, 8, // 78 : Temperature of thermal sensor 0 + Offset (0x80), // [Attention control byte] + Offset (0x81), // [Battery information ID for 0xA0-0xAF] + HIID, 8, // (this byte is depend on the interface, 62&66 and 1600&1604) + Offset (0x83), // [Fn Dual function ID] + HFNI, 8, // 0: none + // 1-3: Reserved + // 4: ACPI Power + // 5: ACPI Sleep + // 6: ACPI Wake + // 7: Left Ctrl key + Offset(0x84), // [Fan Speed] + HSPD, 16, // + // (I/F Offset 3Bh bit5 => 0:Main Fan , 1:Second Fan) + Offset (0x88), // [Thermal Status of Level 0 (low)] + TSL0, 7, + TSR0, 1, + Offset (0x89), // [Thermal Status of Level 1 (middle)] + TSL1, 7, + TSR1, 1, + Offset (0x8A), // [Thermal Status of Level 2 (middle high)] + TSL2, 7, + TSR2, 1, + Offset (0x8B), // [Thermal Status of Level 3 (high)] + TSL3, 7, + TSR3, 1, + GPUT, 1, + Offset(0x8D), // [Interval of polling Always-on cards in half minute] + HDAA, 3, // Warning Delay Period + HDAB, 3, // Stolen Delay Period + HDAC, 2, // Sensitivity + Offset (0xB0), + HDEN, 32, + HDEP, 32, + HDEM, 8, + HDES, 8, + Offset (0xC4), + SDKL, 1, + Offset (0xC5), + Offset (0xC8), // [Adaptive Thermal Management (ATM)] + ATMX, 8, // bit 7-4 - Thermal Table & bit 3-0 - Fan Speed Table + Offset(0xC9), // [Wattage of AC/DC] + HWAT, 8, // + Offset (0xCC), // + PWMH, 8, // CC : AC Power Consumption (MSB) + PWML, 8, // CD : AC Power Consumption (LSB) - unit: 100mW + Offset (0xCF), + , 6, + ESLP, 1, + Offset (0xD0), + Offset (0xED), + , 4, + HDDD, 1 + } + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_EC", 0) +{ + Scope (\) + { + /* + * Status from two EC fields + */ + Method (B1B2, 2, NotSerialized) + { + Local0 = (Arg1 << 0x08) + Local0 |= Arg0 + Return (Local0) + } + + /* + * Status from four EC fields + */ + Method (B1B4, 4, NotSerialized) + { + Local0 = Arg3 + Local0 = (Arg2 | (Local0 << 0x08)) + Local0 = (Arg1 | (Local0 << 0x08)) + Local0 = (Arg0 | (Local0 << 0x08)) + Return (Local0) + } + } + + /* + * Methods to EC read / write access in case you don't have battery patch + * Taken from Rehabmman's guide: https://www.tonymacx86.com/threads/guide-how-to-patch-dsdt-for-working-battery-status.116102/ + */ + + External (_SB_.PCI0.LPCB.EC, DeviceObj) // EC path + + Scope (_SB.PCI0.LPCB.EC) + { + /* + * Called from RECB, grabs a single byte from EC + * Arg0 - offset in bytes from zero-based EC + */ + Method (RE1B, 1, Serialized) + { + OperationRegion (ERAM, EmbeddedControl, Arg0, One) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + BYTE, 8 + } + + Return (BYTE) + } + + /* + * Grabs specified number of bytes from EC + * Arg0 - offset in bytes from zero-based EC + * Arg1 - size of buffer in bits + */ + Method (RECB, 2, Serialized) + { + Arg1 = ((Arg1 + 0x07) >> 0x03) + Name (TEMP, Buffer (Arg1) {}) + Arg1 += Arg0 + Local0 = Zero + While ((Arg0 < Arg1)) + { + TEMP [Local0] = RE1B (Arg0) + Arg0++ + Local0++ + } + + Return (TEMP) + } + + Method (WE1B, 2, Serialized) + { + OperationRegion (ERAM, EmbeddedControl, Arg0, One) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + BYTE, 8 + } + + BYTE = Arg1 + } + + Method (WECB, 3, Serialized) + { + Arg1 = ((Arg1 + 0x07) >> 0x03) + Name (TEMP, Buffer (Arg1) {}) + TEMP = Arg2 + Arg1 += Arg0 + Local0 = Zero + While ((Arg0 < Arg1)) + { + WE1B (Arg0, DerefOf (TEMP [Local0])) + Arg0++ + Local0++ + } + } + } + + /* + Sample SSDT for ThinkSMC sensor access + Double check name of FieldUnit for collision + Registers return 0x00 for non-implemented, + and return 0x80 when not available. + */ + + External (_SB.PCI0.LPCB.EC.HKEY, DeviceObj) // HKEY path + External (_SB.PCI0.LPCB.EC.HFSP, FieldUnitObj) // Fan control register + External (_SB.PCI0.LPCB.EC.HFNI, FieldUnitObj) // Fan control register + External (_SB.PCI0.LPCB.EC.VRST, FieldUnitObj) // Second fan switch register + External (_SI._SST, MethodObj) // Indicator + + /* + * Optional: Route to customized LED pattern or origin _SI._SST if differ from built in pattern. + */ + Scope (\_SB.PCI0.LPCB.EC.HKEY) + { + // Used as a proxy-method to interface with \_SI._SST in YogaSMC + Method (CSSI, 1, NotSerialized) + { + \_SI._SST (Arg0) + } + } + + /* + * Optional: Sensor access + * + * Double check name of FieldUnit for collision + * Registers return 0x00 for non-implemented, + * and return 0x80 when not available. + */ + + Scope (_SB.PCI0.LPCB.EC) + { + OperationRegion (ESEN, EmbeddedControl, Zero, 0x0100) + Field (ESEN, ByteAcc, Lock, Preserve) + { + // TP_EC_THERMAL_TMP0 + Offset (0x78), + EST0, 8, // CPU + EST1, 8, + EST2, 8, + EST3, 8, // GPU ? + EST4, 8, // Battery ? + EST5, 8, // Battery ? + EST6, 8, // Battery ? + EST7, 8, // Battery ? + + // TP_EC_THERMAL_TMP8 + Offset (0xC0), + EST8, 8, + EST9, 8, + ESTA, 8, + ESTB, 8, + ESTC, 8, + ESTD, 8, + ESTE, 8, + ESTF, 8 + } + } + + /* + * Optional: Write access to fan control register + */ + Scope (\_SB.PCI0.LPCB.EC.HKEY) + { + Method (CFSP, 1, NotSerialized) + { + \_SB.PCI0.LPCB.EC.HFSP = Arg0 + } + + Method (CFNI, 1, NotSerialized) + { + \_SB.PCI0.LPCB.EC.HFNI = Arg0 + } + + Method (CRST, 1, NotSerialized) + { + \_SB.PCI0.LPCB.EC.VRST = Arg0 + } + } +} \ No newline at end of file diff --git a/patches/SSDT-EXT1-FixShutdown.dsl b/patches/SSDT-EXT1-FixShutdown.dsl deleted file mode 100644 index 8246e65..0000000 --- a/patches/SSDT-EXT1-FixShutdown.dsl +++ /dev/null @@ -1,14 +0,0 @@ -// Fix "restart after shutdown" -// Credit RehabMan (Laptop-DSDT-Patch) -DefinitionBlock("", "SSDT", 2, "tyler", "EXT1", 0) -{ - External (_SB_.PCI0.XHC_.PMEE, FieldUnitObj) - - Method (EXT1, 1, NotSerialized) - { - If ((5 == Arg0) && CondRefOf (\_SB.PCI0.XHC.PMEE)) { - \_SB.PCI0.XHC.PMEE = 0 - } - } -} -//EOF diff --git a/patches/SSDT-EXT4-WakeScreen.dsl b/patches/SSDT-EXT4-WakeScreen.dsl deleted file mode 100755 index fbaa8de..0000000 --- a/patches/SSDT-EXT4-WakeScreen.dsl +++ /dev/null @@ -1,33 +0,0 @@ -// -DefinitionBlock("", "SSDT", 2, "tyler", "EXT4", 0) -{ - External(_SB.LID, DeviceObj) - External(_SB.LID0, DeviceObj) - External(_SB.PCI0.LPCB.LID, DeviceObj) - External(_SB.PCI0.LPCB.LID0, DeviceObj) - - Method (EXT4, 1, NotSerialized) - { - If (3 == Arg0) - { - If (CondRefOf (\_SB.LID)) - { - Notify (\_SB.LID, 0x80) - } - If (CondRefOf (\_SB.LID0)) - { - Notify (\_SB.LID0, 0x80) - } - // - If (CondRefOf (\_SB.PCI0.LPCB.LID)) - { - Notify (\_SB.PCI0.LPCB.LID, 0x80) - } - If (CondRefOf (\_SB.PCI0.LPCB.LID0)) - { - Notify (\_SB.PCI0.LPCB.LID0, 0x80) - } - } - } -} -//EOF diff --git a/patches/SSDT-HPET.dsl b/patches/SSDT-HPET.dsl deleted file mode 100644 index c7d927a..0000000 --- a/patches/SSDT-HPET.dsl +++ /dev/null @@ -1,18 +0,0 @@ -// -// Supplementary HPET _CRS from Goldfish64 -// Requires the HPET's _CRS to XCRS rename -// -DefinitionBlock ("", "SSDT", 2, "tyler", "HPET", 0x00000000) -{ - External (_SB.PCI0.LPCB, DeviceObj) // (from opcode) - External (_SB.PCI0.LPCB.HPET, DeviceObj) // (from opcode) - Name (\_SB.PCI0.LPCB.HPET._CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IRQNoFlags () - {0,8,11} - Memory32Fixed (ReadWrite, - 0xFED00000, // Address Base - 0x00000400, // Address Length - ) - }) -} diff --git a/patches/SSDT-HWAC.dsl b/patches/SSDT-HWAC.dsl new file mode 100644 index 0000000..96bb97f --- /dev/null +++ b/patches/SSDT-HWAC.dsl @@ -0,0 +1,67 @@ +/* + * On many modern hackintoshed thinkpads there are ofthen accesses to the 16-bit EC-field `HWAC`, which are mostly + * not handled by battery-patches (f.e. those currated by @daliansky). Those accesses are (mostly) located in the _OWAK() + * and/or _L17-ACPI-methods of the original DSDT. + * + * The ACPI-method OWAK() gets called by _WAK() on wake and crashes there on access of the HWAC-field, leaving the + * machine in an undefined/unknown hw-state as the regular ACPI-wakeup-method, which re-setups the hardware after S3-sleep, + * can't run to its end. + * + * Especially this bug is often not clearly visible as the kernel-ringbuffer (msgbuf) is, by default, only 4kb in size and flooded on wake + * with many messages. This can be mitigated (up to 16kb) via `msgbuf`-boot-arg or patched by `DebugEnhancer.kext` by @acidanthera. + * You can check the size of your msgbuf with `sysctl -a kern.msgbuf`. + * + * This SSDT is a simple solution for that problem and should be stable accross different Thinkpad models which suffer from this problem + * as it fixes all accesses to the EC.HWAC-field at once. + * + * It repleaces all reads to HWAC with a call to XWAC(), returning a newly stitched 16-bit-field out of the + * two overlayed 8-bit-fields `WAC0` & `WAC1`. + * + * + * Background: + * `Later releases of AppleACPIPlatform are unable to correctly access fields within the EC (embedded controller). + * [...] DSDT must be changed to comply with the limitations of Apple's AppleACPIPlatform. + * + * In particular, any fields in the EC larger than 8-bit, must be changed to be accessed 8-bits at one time. + * This includes 16, 32, 64, and larger fields.` + * - @Rehabman, https://www.tonymacx86.com/threads/guide-how-to-patch-dsdt-for-working-battery-status.116102/ + * + * Depends on /patches/OpenCore Patches/ HWAC.plist + */ + + +DefinitionBlock ("", "SSDT", 2, "tyler", "_HWAC", 0x00001000) +{ + External (_SB.PCI0.LPCB.EC, DeviceObj) + External (_SB.PCI0.LPCB.EC.HWAC, FieldUnitObj) + + Scope (\_SB.PCI0.LPCB.EC) + { + // + // EC region overlay. + // + OperationRegion (ERAM, EmbeddedControl, 0x00, 0x0100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x36), + WAC0, 8, WAC1, 8, + } + + // Method used for replacing reads to HWAC in _L17() & OWAK(). + Method (XWAC, 0, NotSerialized) + { + If (_OSI ("Darwin")) + { + Local0 = (WAC1 << 0x08) + Local0 |= WAC0 + + Return (Local0) + } + Else + { + Return (HWAC) + } + } + } +} +// EOF diff --git a/patches/SSDT-INIT.dsl b/patches/SSDT-INIT.dsl new file mode 100644 index 0000000..4f02663 --- /dev/null +++ b/patches/SSDT-INIT.dsl @@ -0,0 +1,85 @@ +/* + Source: https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl + // + // Miscellaneous Dynamic Registers: + // + Offset(0), OSYS, 16, // Offset(0), Operating System + Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SMI via I/O Trap) + Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value + Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode = 1) + // + // Thermal Policy Registers: + // + Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable + Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call + // + // CPU Identification Registers: + // + Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC Enabled = 1) + Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads + // + // PCIe Hot Plug + // + Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control + Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value + [...] + Offset(65), RTD3, 8, // Offset(65), Runtime D3 support. + Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable + Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify Sleep State Change + Offset(68), PSCP, 8, // Offset(68), P-state Capping + Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable + Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enable + // + // Driver Mode + // + Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ + Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering CS + Offset(76), PLVL, 16, // Offset(76), PL1 limit value + Offset(78), PB1E, 8, // Offset(78), 10sec Power button support + Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr + Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support + Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug + Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port selector + Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port selector + Offset(84), BDID, 8, // Offset(84), Board ID +*/ +// Credits @benbender + +DefinitionBlock ("", "SSDT", 2, "tyler", "_INIT", 0x00001000) +{ + External (OSDW, MethodObj) // 0 Arguments + + External (HPTE, FieldUnitObj) // HPET enabled? + External (WNTF, FieldUnitObj) // DYTC enabled? + External (DPTF, FieldUnitObj) // DPTF enabled? + External (GPEN, FieldUnitObj) // GPIO enabled? + External (SADE, FieldUnitObj) // B0D4 enabled? + External (ACC0, FieldUnitObj) // TPM enabled? + + External (SDS8, FieldUnitObj) + External (SMD8, FieldUnitObj) + + If (OSDW ()) + { + Debug = "Set Variables..." + + // Disable HPET. It shouldn't be needed on modern systems anyway and is also disabled in genuine OSX + HPTE = Zero + + // Enables DYTC, Lenovos thermal solution. Can be controlled by YogaSMC + WNTF = One + + // Disable DPTF, we use DYTC! + DPTF = Zero + + // Enable broadcom BLTH-uart + SDS8 = 0x02 + SMD8 = 0x02 + + // Disable GPIO + // GPEN = Zero + + // Disable B0D4 + // SADE = Zero + } +} \ No newline at end of file diff --git a/patches/SSDT-Keyboard-Legacy.dsl b/patches/SSDT-Keyboard-Legacy.dsl new file mode 100644 index 0000000..d68cfa7 --- /dev/null +++ b/patches/SSDT-Keyboard-Legacy.dsl @@ -0,0 +1,327 @@ +/* + * For use with ThinkpadAssistant (would need ACPI renames: /patches/OpenCore Patches/ Keyboard-Legacy.plist) + * https://github.com/MSzturc/ThinkpadAssistant + * + */ + +DefinitionBlock("", "SSDT", 2, "tyler", "_KBD", 0) +{ + External (OSDW, MethodObj) + External (_SB.PCI0.LPCB.KBD, DeviceObj) + External (_SB.PCI0.LPCB.EC, DeviceObj) + External (_SB.PCI0.LPCB.EC.XQ74, MethodObj) // FnLock + External (_SB.PCI0.LPCB.EC.XQ6A, MethodObj) // F4 - Mic Mute + External (_SB.PCI0.LPCB.EC.XQ15, MethodObj) // F5 + External (_SB.PCI0.LPCB.EC.XQ14, MethodObj) // F6 + External (_SB.PCI0.LPCB.EC.XQ16, MethodObj) // F7 + External (_SB.PCI0.LPCB.EC.XQ64, MethodObj) // F8 + External (_SB.PCI0.LPCB.EC.XQ66, MethodObj) // F9 + External (_SB.PCI0.LPCB.EC.XQ60, MethodObj) // F10 + External (_SB.PCI0.LPCB.EC.XQ61, MethodObj) // F11 + External (_SB.PCI0.LPCB.EC.XQ62, MethodObj) // F12 + External (_SB.PCI0.LPCB.EC.XQ1F, MethodObj) // Keyboard Backlight (Fn+Space) + External (_SB.PCI0.LPCB.EC.HKEY.MHKQ, MethodObj) // FnLock LED + External (_SB.PCI0.LPCB.EC.HKEY.MMTS, MethodObj) // F4 - Mic Mute LED + External (_SB.PCI0.LPCB.EC.HKEY.MLCS, MethodObj) // Keyboard Backlight LED + + Scope (_SB.PCI0.LPCB.EC) + { + Name (FUNL, Zero) // FnLock LED + Method (_Q74, 0, NotSerialized) // FnLock (Fn + Esc) + { + If (OSDW ()) + { + FUNL = (FUNL + 1) % 2 + Switch (FUNL) + { + Case (One) + { + // Right Shift + F18 + Notify (KBD, 0x012A) + Notify (KBD, 0x0369) + Notify (KBD, 0x01aa) + + // Enable LED + \_SB.PCI0.LPCB.EC.HKEY.MHKQ (0x02) + } + Case (Zero) + { + // Left Shift + F18 + Notify (KBD, 0x0136) + Notify (KBD, 0x0369) + Notify (KBD, 0x01b6) + + // Disable LED + \_SB.PCI0.LPCB.EC.HKEY.MHKQ (Zero) + } + } + } + Else + { + // Call original _Q74 method. + XQ74() + } + } + + Name (MICL, Zero) // F4 - Mic Mute LED + Method (_Q6A, 0, NotSerialized) // F4 - Microphone Mute = F20 + { + If (OSDW ()) + { + MICL = (MICL + 1) % 2 + Switch (MICL) + { + Case (One) + { + // Right Shift + F20 + Notify (KBD, 0x0136) + Notify (KBD, 0x036B) + Notify (KBD, 0x01b6) + + // Enable LED + \_SB.PCI0.LPCB.EC.HKEY.MMTS (0x02) + } + Case (Zero) + { + // Left Shift + F20 + Notify (KBD, 0x012A) + Notify (KBD, 0x036B) + Notify (KBD, 0x01aa) + + // Disable LED + \_SB.PCI0.LPCB.EC.HKEY.MMTS (Zero) + } + } + } + Else + { + // Call original _Q6A method. + XQ6A() + } + } + + Method (_Q15, 0, NotSerialized) // F5 - Brightness Down = F14 + { + If (OSDW ()) + { + Notify(KBD, 0x0405) + Notify(KBD, 0x20) // Reserved + } + Else + { + // Call original _Q15 method. + XQ15() + } + } + + Method (_Q14, 0, NotSerialized) // F6 - Brightness Up = F15 + { + If (OSDW ()) + { + Notify(KBD, 0x0406) + Notify(KBD, 0x10) // Reserved + } + Else + { + // Call original _Q14 method. + XQ14() + } + } + + Method (_Q16, 0, NotSerialized) // F7 - Dual Display = F16 + { + If (OSDW ()) + { + Notify(KBD, 0x0367) + } + Else + { + // Call original _Q16 method. + XQ16() + } + } + + Method (_Q64, 0, NotSerialized) // F8 - Network = F17 + { + If (OSDW ()) + { + Notify(KBD, 0x0368) + } + Else + { + // Call original _Q64 method. + XQ64() + } + } + + Method (_Q66, 0, NotSerialized) // F9 - Settings = F18 + { + If (OSDW ()) + { + Notify(KBD, 0x0369) + } + Else + { + // Call original _Q66 method. + XQ66() + } + } + + Method (_Q60, 0, NotSerialized) // F10 - Bluetooth + { + + If (OSDW ()) + { + // Left Shift + F17 + Notify (KBD, 0x012A) + Notify (KBD, 0x0368) + Notify (KBD, 0x01AA) + } + Else + { + // Call original _Q60 method. + XQ60() + } + } + + Method (_Q61, 0, NotSerialized) // F11 - Keyboard + { + If (OSDW ()) + { + // Send a down event for the Control key (scancode 1d), then a one-shot event (down then up) for + // the up arrow key (scancode 0e 48), and finally an up event for the Control key (break scancode 9d). + // This is picked up by VoodooPS2 and sent to macOS as the Control+Up key combo. + Notify (KBD, 0x011D) + Notify (KBD, 0x0448) + Notify (KBD, 0x019D) + } + Else + { + // Call original _Q61 method. + XQ61() + } + } + + Method (_Q62, 0, NotSerialized) // F12 - Star = F19 + { + If (OSDW ()) + { + Notify(KBD, 0x036A) + } + Else + { + // Call original _Q62 method. + XQ62() + } + } + + Name (KEYL, Zero) // Keyboard Backlight LED (Fn+Space) + Method (_Q1F, 0, NotSerialized) // cycle keyboard backlight + { + If (OSDW ()) + { + KEYL = (KEYL + 1) % 3 + Switch (KEYL) + { + Case (Zero) + { + // Left Shift + F16. + Notify (KBD, 0x012a) + Notify (KBD, 0x0367) + Notify (KBD, 0x01aa) + + // Bright --> Off + \_SB.PCI0.LPCB.EC.HKEY.MLCS (Zero) + } + Case (One) + { + // Right Shift + F16. + Notify (KBD, 0x0136) + Notify (KBD, 0x0367) + Notify (KBD, 0x01b6) + + // Off --> Dim + \_SB.PCI0.LPCB.EC.HKEY.MLCS (One) + } + Case (0x02) + { + // Left Shift + F19. + Notify (KBD, 0x012a) + Notify (KBD, 0x036a) + Notify (KBD, 0x01aa) + + // Dim --> Bright + \_SB.PCI0.LPCB.EC.HKEY.MLCS (0x02) + } + } + } + Else + { + // Call original _Q1F method. + XQ1F() + } + } + + } + + Scope (_SB.PCI0.LPCB.KBD) + { + Method(_DSM, 4) + { + If (!Arg2) { Return (Buffer() { 0x03 } ) } + Return (Package() + { + "RM,oem-id", "LENOVO", + "RM,oem-table-id", "Thinkpad_ClickPad", + }) + } + + // Overrides (the example data here is default in the Info.plist) + Name(RMCF, Package() + { + "Synaptics TouchPad", Package() + { + "BogusDeltaThreshX", 800, + "BogusDeltaThreshY", 800, + "Clicking", ">y", + "DragLockTempMask", 0x40004, + "DynamicEWMode", ">n", + "FakeMiddleButton", ">n", + "HWResetOnStart", ">y", + //"ForcePassThrough", ">y", + //"SkipPassThrough", ">y", + "PalmNoAction When Typing", ">y", + "ScrollResolution", 800, + "SmoothInput", ">y", + "UnsmoothInput", ">y", + "Thinkpad", ">y", + "EdgeBottom", 0, + "FingerZ", 30, + "MaxTapTime", 100000000, + "MouseMultiplierX", 2, + "MouseMultiplierY", 2, + "MouseScrollMultiplierX", 2, + "MouseScrollMultiplierY", 2, + //"TrackpointScrollYMultiplier", 1, //Change this value to 0xFFFF in order to inverse the vertical scroll direction of the Trackpoint when holding the middle mouse button. + //"TrackpointScrollXMultiplier", 1, //Change this value to 0xFFFF in order to inverse the horizontal scroll direction of the Trackpoint when holding the middle mouse button. + }, + + "Keyboard", Package() + { + "Custom PS2 Map", Package() + { + Package() { }, + "e037=64", // PrtSc = F13 + "46=80", // Fn + K = Deadkey + "e045=80", // Fn + P = Deadkey + "38=e05b", // Left Alt (mismapped to Left GUI by default) = Left Alt + "e038=e05c", // Right Alt (mismapped to Right GUI by default) = Right Alt + "e05b=38", // Windows (mismapped to Left Alt by default) = Left GUI + // "1d=80", // Fn + B = Deadkey + // "54=80", // Fn + S = Deadkey + }, + }, + }) + } +} +//EOF \ No newline at end of file diff --git a/patches/SSDT-Keyboard.dsl b/patches/SSDT-Keyboard.dsl index 9d98857..8340190 100644 --- a/patches/SSDT-Keyboard.dsl +++ b/patches/SSDT-Keyboard.dsl @@ -1,265 +1,12 @@ /* -LED1 is F4 - Mic Mute -LED2 is Keyboard Backlight -LED3 is FnLock LED -*/ -DefinitionBlock("", "SSDT", 2, "tyler", "x1input", 0) + * For use with BrightnessKeys.kext and YogaSMC + * https://github.com/zhen-zen/YogaSMC + * + */ + +DefinitionBlock("", "SSDT", 2, "tyler", "_KBD", 0) { - External(_SB.PCI0.LPCB.KBD, DeviceObj) - External(_SB.PCI0.LPCB.EC, DeviceObj) - External(_SB.PCI0.LPCB.EC.XQ74, MethodObj) // FnLock - External(_SB.PCI0.LPCB.EC.XQ6A, MethodObj) // F4 - Mic Mute - External(_SB.PCI0.LPCB.EC.XQ15, MethodObj) // F5 - External(_SB.PCI0.LPCB.EC.XQ14, MethodObj) // F6 - External(_SB.PCI0.LPCB.EC.XQ16, MethodObj) // F7 - External(_SB.PCI0.LPCB.EC.XQ64, MethodObj) // F8 - External(_SB.PCI0.LPCB.EC.XQ66, MethodObj) // F9 - External(_SB.PCI0.LPCB.EC.XQ60, MethodObj) // F10 - External(_SB.PCI0.LPCB.EC.XQ61, MethodObj) // F11 - External(_SB.PCI0.LPCB.EC.XQ62, MethodObj) // F12 - External(_SB.PCI0.LPCB.EC.XQ1F, MethodObj) // Keyboard Backlight (Fn+Space) - External(_SB.PCI0.LPCB.EC.HKEY.MHKQ, MethodObj) // FnLock LED - External(_SB.PCI0.LPCB.EC.HKEY.MMTS, MethodObj) // F4 - Mic Mute LED - External(_SB.PCI0.LPCB.EC.HKEY.MLCS, MethodObj) // Keyboard Backlight LED - - Scope (_SB.PCI0.LPCB.EC) - { - Name (LED3, Zero) - Method (_Q74, 0, NotSerialized) // FnLock (Fn + Esc) - { - If (_OSI ("Darwin")) - { - // Toggle FnLock LED - If ((LED3 == Zero)) - { - // Right Shift + F18 - Notify (\_SB.PCI0.LPCB.KBD, 0x012A) - Notify (\_SB.PCI0.LPCB.KBD, 0x0369) - Notify (\_SB.PCI0.LPCB.KBD, 0x01aa) - - // 0x02 = Enable LED - \_SB.PCI0.LPCB.EC.HKEY.MHKQ (0x02) - LED3 = One - } - Else - { - // Left Shift + F18 - Notify (\_SB.PCI0.LPCB.KBD, 0x0136) - Notify (\_SB.PCI0.LPCB.KBD, 0x0369) - Notify (\_SB.PCI0.LPCB.KBD, 0x01b6) - - // 0x00 = Disable LED - \_SB.PCI0.LPCB.EC.HKEY.MHKQ (Zero) - LED3 = Zero - } - - } - Else - { - // Call original _Q74 method. - \_SB.PCI0.LPCB.EC.XQ74() - } - } - - Name (LED1, Zero) - // _Q6A - Microphone Mute - Method (_Q6A, 0, NotSerialized) // F4 - Microphone Mute = F20 - { - If (_OSI ("Darwin")) - { - // Toggle Mute Microphone LED - If ((LED1 == Zero)) - { - // Right Shift + F20 - Notify (\_SB.PCI0.LPCB.KBD, 0x0136) - Notify (\_SB.PCI0.LPCB.KBD, 0x036B) - Notify (\_SB.PCI0.LPCB.KBD, 0x01b6) - - // 0x02 = Enable LED - \_SB.PCI0.LPCB.EC.HKEY.MMTS (0x02) - LED1 = One - } - Else - { - // Left Shift + F20 - Notify (\_SB.PCI0.LPCB.KBD, 0x012A) - Notify (\_SB.PCI0.LPCB.KBD, 0x036B) - Notify (\_SB.PCI0.LPCB.KBD, 0x01aa) - - // 0x00 = Disable LED - \_SB.PCI0.LPCB.EC.HKEY.MMTS (Zero) - LED1 = Zero - } - } - Else - { - // Call original _Q6A method. - \_SB.PCI0.LPCB.EC.XQ6A() - } - } - - Method (_Q15, 0, NotSerialized) // F5 - Brightness Down = F14 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x0405) - Notify(\_SB.PCI0.LPCB.KBD, 0x20) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ15() - } - } - - Method (_Q14, 0, NotSerialized) // F6 - Brightness Up = F15 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x0406) - Notify(\_SB.PCI0.LPCB.KBD, 0x10) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ14() - } - } - - Method (_Q16, 0, NotSerialized) // F7 - Dual Display = F16 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x0367) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ16() - } - } - - Method (_Q64, 0, NotSerialized) // F8 - Network = F17 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x0368) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ64() - } - } - - Method (_Q66, 0, NotSerialized) // F9 - Settings = F18 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x0369) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ66() - } - } - - Method (_Q60, 0, NotSerialized) // F10 - Bluetooth - { - - If (_OSI ("Darwin")) - { - // Left Shift + F17 - Notify (\_SB.PCI0.LPCB.KBD, 0x012A) - Notify (\_SB.PCI0.LPCB.KBD, 0x0368) - Notify (\_SB.PCI0.LPCB.KBD, 0x01AA) - } - Else - { - // Call original _Q60 method. - \_SB.PCI0.LPCB.EC.XQ60() - } - } - - Method (_Q61, 0, NotSerialized) // F11 - Keyboard - { - If (_OSI ("Darwin")) - { - // Send a down event for the Control key (scancode 1d), then a one-shot event (down then up) for - // the up arrow key (scancode 0e 48), and finally an up event for the Control key (break scancode 9d). - // This is picked up by VoodooPS2 and sent to macOS as the Control+Up key combo. - Notify (\_SB.PCI0.LPCB.KBD, 0x011D) - Notify (\_SB.PCI0.LPCB.KBD, 0x0448) - Notify (\_SB.PCI0.LPCB.KBD, 0x019D) - } - Else - { - // Call original _Q61 method. - \_SB.PCI0.LPCB.EC.XQ61() - } - } - - Method (_Q62, 0, NotSerialized) // F12 - Star = F19 - { - If (_OSI ("Darwin")) - { - Notify(\_SB.PCI0.LPCB.KBD, 0x036A) - } - Else - { - \_SB.PCI0.LPCB.EC.XQ62() - } - } - - Name (LED2, Zero) - - // _Q1F - (Fn+Space) Toggle Keyboard Backlight. - Method (_Q1F, 0, NotSerialized) // cycle keyboard backlight - { - If (_OSI ("Darwin")) - { - // Cycle keyboard backlight states - If ((LED2 == Zero)) - { - // Right Shift + F16. - Notify (\_SB.PCI0.LPCB.KBD, 0x0136) - Notify (\_SB.PCI0.LPCB.KBD, 0x0367) - Notify (\_SB.PCI0.LPCB.KBD, 0x01b6) - // Off to dim - \_SB.PCI0.LPCB.EC.HKEY.MLCS (One) - LED2 = One - } - Else - { - If ((LED2 == One)) - { - // Left Shift + F19. - Notify (\_SB.PCI0.LPCB.KBD, 0x012a) - Notify (\_SB.PCI0.LPCB.KBD, 0x036a) - Notify (\_SB.PCI0.LPCB.KBD, 0x01aa) - // dim to bright - \_SB.PCI0.LPCB.EC.HKEY.MLCS (0x02) - LED2 = 2 - } - Else - { - If ((LED2 == 2)) - { - // Left Shift + F16. - Notify (\_SB.PCI0.LPCB.KBD, 0x012a) - Notify (\_SB.PCI0.LPCB.KBD, 0x0367) - Notify (\_SB.PCI0.LPCB.KBD, 0x01aa) - // bright to off - \_SB.PCI0.LPCB.EC.HKEY.MLCS (Zero) - LED2 = Zero - } - Else - { - // Call original _Q6A method. - \_SB.PCI0.LPCB.EC.XQ1F () - } - } - } - } - } - - } + External (_SB.PCI0.LPCB.KBD, DeviceObj) Scope (_SB.PCI0.LPCB.KBD) { diff --git a/patches/SSDT-LED.dsl b/patches/SSDT-LED.dsl deleted file mode 100644 index c5e46c0..0000000 --- a/patches/SSDT-LED.dsl +++ /dev/null @@ -1,32 +0,0 @@ -// _TTS Method (TransitionToState) to fix LED issues like: -// Power Button LED and Red LED blinking after Wake from Sleep -// Save Microphone Mute F4 toggle LED State after Wake from Sleep -// Credits: @junaedahmed (Mic Mute LED) @Sniki (Power LED) - -DefinitionBlock ("", "SSDT", 1, "tyler", "LED", 0) -{ - External (_SB.PCI0.LPCB.EC.HKEY.MMTS, MethodObj) - External (_SB.PCI0.LPCB.EC.LED1, IntObj) - External (_SI._SST, MethodObj) - - Method (_TTS, 1, NotSerialized) - { - If (_OSI ("Darwin")) - { - // Arg0 contains the system state of transition - // for wake state it is Zero. - If (CondRefOf (\_SB.PCI0.LPCB.EC.LED1)) - { - If (Arg0 == Zero & \_SB.PCI0.LPCB.EC.LED1 == One) - { - \_SB.PCI0.LPCB.EC.HKEY.MMTS (0x02) - } - } - - If (Arg0 == Zero) - { - \_SI._SST(One) - } - } - } -} diff --git a/patches/SSDT-OCBAT0-TP_tx80_x1c6th.dsl b/patches/SSDT-OCBAT0-TP_tx80_x1c6th.dsl deleted file mode 100644 index 5bfca6c..0000000 --- a/patches/SSDT-OCBAT0-TP_tx80_x1c6th.dsl +++ /dev/null @@ -1,480 +0,0 @@ -// battery -DefinitionBlock ("", "SSDT", 2, "tyler", "BATT", 0) -{ - External (_SB.PCI0.LPCB.EC, DeviceObj) - External (_SB.PCI0.LPCB.EC.AC._PSR, MethodObj) - External (_SB.PCI0.LPCB.EC.B0I0, IntObj) - External (_SB.PCI0.LPCB.EC.B0I1, IntObj) - External (_SB.PCI0.LPCB.EC.B0I2, IntObj) - External (_SB.PCI0.LPCB.EC.B0I3, IntObj) - External (_SB.PCI0.LPCB.EC.B1I0, IntObj) - External (_SB.PCI0.LPCB.EC.B1I1, IntObj) - External (_SB.PCI0.LPCB.EC.B1I2, IntObj) - External (_SB.PCI0.LPCB.EC.B1I3, IntObj) - External (_SB.PCI0.LPCB.EC.BATM, MutexObj) - External (_SB.PCI0.LPCB.EC.BATW, MethodObj) - External (_SB.PCI0.LPCB.EC.BSWA, IntObj) - External (_SB.PCI0.LPCB.EC.BSWR, IntObj) - External (_SB.PCI0.LPCB.EC.HB0S, FieldUnitObj) - External (_SB.PCI0.LPCB.EC.HB1S, FieldUnitObj) - External (_SB.PCI0.LPCB.EC.HIID, FieldUnitObj) - // - External(_SB.PCI0.LPCB.EC.XBIF, MethodObj) - External(_SB.PCI0.LPCB.EC.XBIX, MethodObj) - External(_SB.PCI0.LPCB.EC.XBST, MethodObj) - External(_SB.PCI0.LPCB.EC.XJTP, MethodObj) - - Method (B1B2, 2, NotSerialized) - { - Local0 = (Arg1 << 0x08) - Local0 |= Arg0 - Return (Local0) - } - - Method (B1B4, 4, NotSerialized) - { - Local0 = Arg3 - Local0 = (Arg2 | (Local0 << 0x08)) - Local0 = (Arg1 | (Local0 << 0x08)) - Local0 = (Arg0 | (Local0 << 0x08)) - Return (Local0) - } - - Scope (\_SB.PCI0.LPCB.EC) - { - Method (RE1B, 1, NotSerialized) - { - OperationRegion (ECOR, EmbeddedControl, Arg0, One) - Field (ECOR, ByteAcc, NoLock, Preserve) - { - BYTE, 8 - } - - Return (BYTE) - } - - Method (RECB, 2, Serialized) - { - Arg1 >>= 0x03 - Name (TEMP, Buffer (Arg1){}) - Arg1 += Arg0 - Local0 = Zero - While ((Arg0 < Arg1)) - { - TEMP [Local0] = RE1B (Arg0) - Arg0++ - Local0++ - } - - Return (TEMP) - } - - OperationRegion (BRAM, EmbeddedControl, Zero, 0x0100) - Field (BRAM, ByteAcc, NoLock, Preserve) - { - Offset (0xA0), - RC00, 8, RC01, 8, //SBRC, 16, - FC00, 8, FC01, 8, //SBFC, 16, - , 16, - , 16, - AC00, 8, AC01, 8, //SBAC, 16, - BV00, 8, BV01, 8, //SBVO, 16, - , 16, - , 16 - } - - Field (BRAM, ByteAcc, NoLock, Preserve) - { - Offset (0xA0), - SB00, 8, SB01, 8, //SBBM, 16, - , 16, - CC00, 8, CC01, 8, //SBCC, 16 //E470,T470S - } - - Field (BRAM, ByteAcc, NoLock, Preserve) - { - Offset (0xA0), - DC00, 8, DC01, 8, //SBDC, 16, - DV00, 8, DV01, 8, //SBDV, 16, - , 16, - , 16, - , 16, - SN00, 8, SN01, 8 //SBSN, 16 - } - - Field (BRAM, ByteAcc, NoLock, Preserve) - { - Offset (0xA0), - CH00, 8, CH01, 8, CH02, 8, CH03, 8 //SBCH, 32 - } - - Method (GBIF, 3, NotSerialized) - { - If (_OSI ("Darwin")) - { - Acquire (BATM, 0xFFFF) - If (Arg2) - { - HIID = (Arg0 | One) - Local7 = B1B2 (SB00, SB01) - Local7 >>= 0x0F - Arg1 [Zero] = (Local7 ^ One) - HIID = Arg0 - If (Local7) - { - Local1 = (B1B2 (FC00, FC01) * 0x0A) - } - Else - { - Local1 = B1B2 (FC00, FC01) - } - - Arg1 [0x02] = Local1 - HIID = (Arg0 | 0x02) - If (Local7) - { - Local0 = (B1B2 (DC00, DC01) * 0x0A) - } - Else - { - Local0 = B1B2 (DC00, DC01) - } - - Arg1 [One] = Local0 - Divide (Local1, 0x14, Local2, Arg1 [0x05]) - If (Local7) - { - Arg1 [0x06] = 0xC8 - } - ElseIf (B1B2 (DV00, DV01)) - { - Divide (0x00030D40, B1B2 (DV00, DV01), Local2, Arg1 [0x06]) - } - Else - { - Arg1 [0x06] = Zero - } - - Arg1 [0x04] = B1B2 (DV00, DV01) - Local0 = B1B2 (SN00, SN01) - Name (SERN, Buffer (0x06) - { - " " - }) - Local2 = 0x04 - While (Local0) - { - Divide (Local0, 0x0A, Local1, Local0) - SERN [Local2] = (Local1 + 0x30) - Local2-- - } - - Arg1 [0x0A] = SERN - HIID = (Arg0 | 0x06) - Arg1 [0x09] = RECB (0xA0, 0x80) - HIID = (Arg0 | 0x04) - Name (BTYP, Buffer (0x05) - { - 0x00, 0x00, 0x00, 0x00, 0x00 - }) - BTYP = B1B4 (CH00, CH01, CH02, CH03) - Arg1 [0x0B] = BTYP - HIID = (Arg0 | 0x05) - Arg1 [0x0C] = RECB (0xA0, 0x80) - } - Else - { - Arg1 [One] = 0xFFFFFFFF - Arg1 [0x05] = Zero - Arg1 [0x06] = Zero - Arg1 [0x02] = 0xFFFFFFFF - } - - Release (BATM) - Return (Arg1) - } - Else - { - Return (\_SB.PCI0.LPCB.EC.XBIF(Arg0, Arg1, Arg2)) - } - } - - Method (GBIX, 3, NotSerialized) - { - If (_OSI ("Darwin")) - { - Acquire (BATM, 0xFFFF) - If (Arg2) - { - HIID = (Arg0 | One) - Local7 = B1B2 (CC00, CC01) - Arg1 [0x08] = Local7 - Local7 = B1B2 (SB00, SB01) - Local7 >>= 0x0F - Arg1 [One] = (Local7 ^ One) - HIID = Arg0 - If (Local7) - { - Local1 = (B1B2 (FC00, FC01) * 0x0A) - } - Else - { - Local1 = B1B2 (FC00, FC01) - } - - Arg1 [0x03] = Local1 - HIID = (Arg0 | 0x02) - If (Local7) - { - Local0 = (B1B2 (DC00, DC01) * 0x0A) - } - Else - { - Local0 = B1B2 (DC00, DC01) - } - - Arg1 [0x02] = Local0 - Divide (Local1, 0x14, Local2, Arg1 [0x06]) - If (Local7) - { - Arg1 [0x07] = 0xC8 - } - ElseIf (B1B2 (DV00, DV01)) - { - Divide (0x00030D40, B1B2 (DV00, DV01), Local2, Arg1 [0x07]) - } - Else - { - Arg1 [0x07] = Zero - } - - Arg1 [0x05] = B1B2 (DV00, DV01) - Local0 = B1B2 (SN00, SN01) - Name (SERN, Buffer (0x06) - { - " " - }) - Local2 = 0x04 - While (Local0) - { - Divide (Local0, 0x0A, Local1, Local0) - SERN [Local2] = (Local1 + 0x30) - Local2-- - } - - Arg1 [0x11] = SERN - HIID = (Arg0 | 0x06) - Arg1 [0x10] = RECB (0xA0, 0x80) - HIID = (Arg0 | 0x04) - Name (BTYP, Buffer (0x05) - { - 0x00, 0x00, 0x00, 0x00, 0x00 - }) - BTYP = B1B4 (CH00, CH01, CH02, CH03) - Arg1 [0x12] = BTYP - HIID = (Arg0 | 0x05) - Arg1 [0x13] = RECB (0xA0, 0x80) - } - Else - { - Arg1 [0x02] = 0xFFFFFFFF - Arg1 [0x06] = Zero - Arg1 [0x07] = Zero - Arg1 [0x03] = 0xFFFFFFFF - } - - Release (BATM) - Return (Arg1) - } - Else - { - Return (\_SB.PCI0.LPCB.EC.XBIX(Arg0, Arg1, Arg2)) - } - - } - - Method (GBST, 4, NotSerialized) - { - If (_OSI ("Darwin")) - { - Acquire (BATM, 0xFFFF) - If ((Arg1 & 0x20)) - { - Local0 = 0x02 - } - ElseIf ((Arg1 & 0x40)) - { - Local0 = One - } - Else - { - Local0 = Zero - } - - If ((Arg1 & 0x07)){} - Else - { - Local0 |= 0x04 - } - - If (((Arg1 & 0x07) == 0x07)) - { - Local0 = 0x04 - Local1 = Zero - Local2 = Zero - Local3 = Zero - } - Else - { - HIID = Arg0 - Local3 = B1B2 (BV00, BV01) - If (Arg2) - { - Local2 = (B1B2 (RC00, RC01) * 0x0A) - } - Else - { - Local2 = B1B2 (RC00, RC01) - } - - Local1 = B1B2 (AC00, AC01) - If ((Local1 >= 0x8000)) - { - If ((Local0 & One)) - { - Local1 = (0x00010000 - Local1) - } - Else - { - Local1 = Zero - } - } - ElseIf (!(Local0 & 0x02)) - { - Local1 = Zero - } - - If (Arg2) - { - Local1 *= Local3 - Divide (Local1, 0x03E8, Local7, Local1) - } - } - - Local5 = (One << (Arg0 >> 0x04)) - BSWA |= BSWR - If (((BSWA & Local5) == Zero)) - { - Arg3 [Zero] = Local0 - Arg3 [One] = Local1 - Arg3 [0x02] = Local2 - Arg3 [0x03] = Local3 - If ((Arg0 == Zero)) - { - B0I0 = Local0 - B0I1 = Local1 - B0I2 = Local2 - B0I3 = Local3 - } - Else - { - B1I0 = Local0 - B1I1 = Local1 - B1I2 = Local2 - B1I3 = Local3 - } - } - Else - { - If (\_SB.PCI0.LPCB.EC.AC._PSR ()) - { - If ((Arg0 == Zero)) - { - Arg3 [Zero] = B0I0 - Arg3 [One] = B0I1 - Arg3 [0x02] = B0I2 - Arg3 [0x03] = B0I3 - } - Else - { - Arg3 [Zero] = B1I0 - Arg3 [One] = B1I1 - Arg3 [0x02] = B1I2 - Arg3 [0x03] = B1I3 - } - } - Else - { - Arg3 [Zero] = Local0 - Arg3 [One] = Local1 - Arg3 [0x02] = Local2 - Arg3 [0x03] = Local3 - } - - If ((((Local0 & 0x04) == Zero) && ((Local2 > Zero) && - (Local3 > Zero)))) - { - BSWA &= ~Local5 - Arg3 [Zero] = Local0 - Arg3 [One] = Local1 - Arg3 [0x02] = Local2 - Arg3 [0x03] = Local3 - } - } - - Release (BATM) - Return (Arg3) - } - Else - { - Return (\_SB.PCI0.LPCB.EC.XBST(Arg0, Arg1, Arg2, Arg3)) - } - } - - Method (AJTP, 3, NotSerialized) - { - If (_OSI ("Darwin")) - { - Local0 = Arg1 - Acquire (BATM, 0xFFFF) - HIID = Arg0 - Local1 = B1B2 (RC00, RC01) - Release (BATM) - If ((Arg0 == Zero)) - { - Local2 = HB0S - } - Else - { - Local2 = HB1S - } - - If ((Local2 & 0x20)) - { - If ((Arg2 > Zero)) - { - Local0 += One - } - - If ((Local0 <= Local1)) - { - Local0 = (Local1 + One) - } - } - ElseIf ((Local2 & 0x40)) - { - If ((Local0 >= Local1)) - { - Local0 = (Local1 - One) - } - } - - Return (Local0) - } - Else - { - Return (\_SB.PCI0.LPCB.EC.XJTP(Arg0, Arg1, Arg2)) - } - } - } -} diff --git a/patches/SSDT-PLUG-_PR.PR00.dsl b/patches/SSDT-PLUG-_PR.PR00.dsl deleted file mode 100644 index 9839886..0000000 --- a/patches/SSDT-PLUG-_PR.PR00.dsl +++ /dev/null @@ -1,51 +0,0 @@ -/* - * XCPM power management compatibility table. - */ -DefinitionBlock ("", "SSDT", 2, "tyler", "CpuPlug", 0x00003000) -{ - External (_PR.PR00, ProcessorObj) - - Scope (_PR.PR00) - { - Method (DTGP, 5, NotSerialized) - { - If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b"))) - { - If ((Arg1 == One)) - { - If ((Arg2 == Zero)) - { - Arg4 = Buffer (One) - { - 0x03 - } - Return (One) - } - - If ((Arg2 == One)) - { - Return (One) - } - } - } - - Arg4 = Buffer (One) - { - 0x00 - } - Return (Zero) - } - - Method (_DSM, 4, NotSerialized) - { - Local0 = Package (0x02) - { - "plugin-type", - One - } - DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) - Return (Local0) - } - } -} - diff --git a/patches/SSDT-PLUG.dsl b/patches/SSDT-PLUG.dsl new file mode 100644 index 0000000..704d412 --- /dev/null +++ b/patches/SSDT-PLUG.dsl @@ -0,0 +1,32 @@ +/* + * XCPM power management compatibility table. + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_PLUG", 0x00001000) +{ + External(_PR.PR00, ProcessorObj) + + If (CondRefOf (\PR.PR00)) + { + Scope (\_PR.PR00) + { + Method (_DSM, 4, NotSerialized) + { + If (LEqual (Arg2, Zero)) + { + Return (Buffer (One) + { + 0x03 + }) + } + + Return (Package (0x02) + { + // Inject plugin-type = 0x01 + "plugin-type", + One + }) + } + } + } +} \ No newline at end of file diff --git a/patches/SSDT-PMCR.dsl b/patches/SSDT-PMCR.dsl index 30bc84c..de38afc 100755 --- a/patches/SSDT-PMCR.dsl +++ b/patches/SSDT-PMCR.dsl @@ -1,11 +1,15 @@ -//Add PMCR -DefinitionBlock ("", "SSDT", 2, "tyler", "PMCR", 0) +// Add PMCR + +DefinitionBlock ("", "SSDT", 2, "tyler", "_PMCR", 0) { + External (OSDW, MethodObj) External(_SB.PCI0.LPCB, DeviceObj) + Scope (_SB.PCI0.LPCB) { Device (PMCR) { + // Name (_ADR, 0x001F0002) // _ADR: Address Name (_HID, EisaId ("APP9876")) Name (_CRS, ResourceTemplate () { @@ -17,7 +21,7 @@ DefinitionBlock ("", "SSDT", 2, "tyler", "PMCR", 0) }) Method (_STA, 0, NotSerialized) { - If (_OSI ("Darwin")) + If (OSDW ()) { Return (0x0B) } diff --git a/patches/SSDT-PNLF-SKL_KBL.dsl b/patches/SSDT-PNLF-SKL_KBL.dsl deleted file mode 100644 index 445e73d..0000000 --- a/patches/SSDT-PNLF-SKL_KBL.dsl +++ /dev/null @@ -1,27 +0,0 @@ -// -DefinitionBlock("", "SSDT", 2, "tyler", "PNLF", 0) -{ - Scope(_SB) - { - Device(PNLF) - { - Name(_ADR, Zero) - Name(_HID, EisaId ("APP0002")) - Name(_CID, "backlight") - //Skylake/KabyLake/KabyLake-R - Name(_UID, 16) - Method (_STA, 0, NotSerialized) - { - If (_OSI ("Darwin")) - { - Return (0x0B) - } - Else - { - Return (Zero) - } - } - } - } -} -//EOF \ No newline at end of file diff --git a/patches/SSDT-PNLF.dsl b/patches/SSDT-PNLF.dsl new file mode 100644 index 0000000..e86f8b8 --- /dev/null +++ b/patches/SSDT-PNLF.dsl @@ -0,0 +1,98 @@ +/* + * Add PNLF device + * For use with AppleBacklightSmoother.kext + * + * Credits @hieplpvip + */ + +DefinitionBlock("", "SSDT", 2, "tyler", "_PNLF", 0) +{ + External(_SB.PCI0.GFX0, DeviceObj) + Scope(_SB.PCI0.GFX0) + { + OperationRegion(RMP1, PCI_Config, 2, 2) + } + + // For backlight control + Device(_SB.PCI0.GFX0.PNLF) + { + Name(_ADR, Zero) + Name(_HID, EisaId("APP0002")) + Name(_CID, "backlight") + // _UID is set depending on device ID to match profiles in WhateverGreen + // 14: Arrandale/Sandy/Ivy + // 15: Haswell/Broadwell + // 16: Skylake/KabyLake + // 17: custom LMAX=0x7a1 + // 18: custom LMAX=0x1499 + // 19: CoffeeLake 0xffff + Name(_UID, 0) + Name(_STA, 0x0B) + + Field(RMP1, AnyAcc, NoLock, Preserve) + { + GDID, 16 + } + + Method(_INI) + { + Local0 = ^GDID + + // check Arrandale/Sandy/Ivy + If (Ones != Match(Package() + { + // Arrandale + 0x0042, 0x0046, 0x004a, + // Sandy HD3000 + 0x0102, 0x0106, 0x010a, 0x010b, 0x010e, + 0x0112, 0x0116, 0x0122, 0x0126, + // Ivy + 0x0152, 0x0156, 0x015a, 0x015e, 0x0162, + 0x0166, 0x016a, 0x0172, 0x0176, + }, MEQ, Local0, MTR, 0, 0)) + { + _UID = 14 + } + + // check Haswell/Broadwell + ElseIf (Ones != Match(Package() + { + // Haswell + 0x0402, 0x0406, 0x040a, 0x0412, 0x0416, + 0x041a, 0x041e, 0x0a06, 0x0a16, 0x0a1e, + 0x0a22, 0x0a26, 0x0a2a, 0x0a2b, 0x0a2e, + 0x0d12, 0x0d16, 0x0d22, 0x0d26, 0x0d2a, + 0x0d36, + // Broadwell + 0x1612, 0x1616, 0x161e, 0x1622, 0x1626, + 0x162a, 0x162b, 0x162d, + }, MEQ, Local0, MTR, 0, 0)) + { + _UID = 15 + } + + // check Skylake/Kaby Lake + ElseIf (Ones != Match(Package() + { + // Skylake + 0x1902, 0x1906, 0x190b, 0x1912, 0x1916, + 0x191b, 0x191d, 0x191e, 0x1921, 0x1923, + 0x1926, 0x1927, 0x192b, 0x192d, 0x1932, + 0x193a, 0x193b, + // Kaby Lake + 0x5902, 0x5912, 0x5916, 0x5917, 0x591b, + 0x591c, 0x591d, 0x591e, 0x5923, 0x5926, + 0x5927, 0x87c0 + }, MEQ, Local0, MTR, 0, 0)) + { + _UID = 16 + } + + // assume Coffee Lake and newer + Else + { + _UID = 19 + } + } + } +} diff --git a/patches/SSDT-PTSWAK.dsl b/patches/SSDT-PTSWAK.dsl deleted file mode 100644 index 811a76b..0000000 --- a/patches/SSDT-PTSWAK.dsl +++ /dev/null @@ -1,113 +0,0 @@ -// Overriding _PTS and _WAK -// In config ACPI, _PTS to ZPTS(1,N) -// Find: 5F50545301 -// Replace: 5A50545301 -// or -// In config ACPI, _PTS to ZPTS(1,S) -// Find: 5F50545309 -// Replace: 5A50545309 -// -// In config ACPI, _WAK to ZWAK(1,N) -// Find: 5F57414B01 -// Replace: 5A57414B01 -// or -// In config ACPI, _WAK to ZWAK(1,S) -// Find: 5F57414B09 -// Replace: 5A57414B09 -// -DefinitionBlock("", "SSDT", 2, "tyler", "PTSWAK", 0) -{ - External(ZPTS, MethodObj) - External(ZWAK, MethodObj) - External(EXT1, MethodObj) - External(EXT2, MethodObj) - External(EXT3, MethodObj) - External(EXT4, MethodObj) - External(DGPU._ON, MethodObj) - External(DGPU._OFF, MethodObj) - - Scope (_SB) - { - Device (PCI9) - { - Name (_ADR, Zero) - Name (FNOK, Zero) - Name (MODE, Zero) - // - Name (TPTS, Zero) - Name (TWAK, Zero) - Method (_STA, 0, NotSerialized) - { - If (_OSI ("Darwin")) - { - Return (0x0F) - } - Else - { - Return (Zero) - } - } - } - } - - Method (_PTS, 1, NotSerialized) //Method (_PTS, 1, Serialized) - { - If (_OSI ("Darwin")) - { - \_SB.PCI9.TPTS = Arg0 - - if(\_SB.PCI9.FNOK ==1) - { - Arg0 = 3 - } - - If (CondRefOf (\DGPU._ON)) - { - \DGPU._ON () - } - - If (CondRefOf(EXT1)) - { - EXT1(Arg0) - } - If (CondRefOf(EXT2)) - { - EXT2(Arg0) - } - } - - ZPTS(Arg0) - } - - Method (_WAK, 1, NotSerialized) //Method (_WAK, 1, Serialized) - { - If (_OSI ("Darwin")) - { - \_SB.PCI9.TWAK = Arg0 - - if(\_SB.PCI9.FNOK ==1) - { - \_SB.PCI9.FNOK =0 - Arg0 = 3 - } - - If (CondRefOf (\DGPU._OFF)) - { - \DGPU._OFF () - } - - If (CondRefOf(EXT3)) - { - EXT3(Arg0) - } - If (CondRefOf(EXT4)) - { - EXT4(Arg0) - } - } - - Local0 = ZWAK(Arg0) - Return (Local0) - } -} -//EOF diff --git a/patches/SSDT-Sleep.dsl b/patches/SSDT-Sleep.dsl new file mode 100644 index 0000000..d584f17 --- /dev/null +++ b/patches/SSDT-Sleep.dsl @@ -0,0 +1,392 @@ +/* + * # Comprehensive Sleep-patches for modern thinkpads. + * + * ## Abstract + * + * This SSDT tries to be a comprehensive solution for sleep/wake-problems on most modern thinkpads. + * It was developed on an X1C6 with a T480 in mind. + * It immitates the behaviour of a macbookpro14,1 which is perfectly adequate for modern, kabylake-based Thinkpads. + * + * For X1C6 its perfectly possible to set SleepType=Windows in BIOS while getting perfect S3-Standby in OSX. + * + * With this SSDT it is perfectly possible to have ACPI-sleepstates S0 (DeepIde), S3 (Standby) & S4 (Hibernation) working. + * So generally hibernatemode 0, 3 & 25 in OSX' terms are possible. There might be smaller bugs and hickups though. + * F.e. S0-DeepIdle has a much higher power draw on sleep as S3 atm. There are also reports about such behaviour on + * native OSX & native Windows. Bugs are not infrequently rooted in poor ACPI-implementations or OSX-bugs and not + * directly rooted in hackintoshing. + * + * No special setup via pmset per se needed, but may be needed anyways depending f.e. on your bluetooth implementation. + * If you have played with `pmset` and want to restore the defaults to have a clean state, use `sudo pmset -a restoredefaults`. + * + * Bottom line: We are near a relative native pm-/sleep-setup with this. + * + * + * ## Background: + * + * Sleep on hackintoshes is a complicated topic. More complicated as mostly percieved. The problem is + * that many functions of power management, sleep & wake are handled by the Macbook's embedded controller (EC) + * / SMC and therefor many functions and devices are simply missing on Hackintoshes (f.e. the topcase-device). + * What we do have are our own, vendor-specific ECs and a myriade of different names for different sleep-methods. + * + * On top of this, most parts of the config have to be configured properly to accomplish working, non (or at least less) + * power-loosing sleep-states. Many of the (partly) solutions out there don't try to replicate the sleep-behaviour + * of a genuine macbook, but try to hide shortcomings and bugs with "ons-size-fits-all"-patches. + * + * With this reasoning in mind, this SSDT tries to match the sleep-behaviour of a macbookpro14,1 as closely as possible. + * + * + * # Notice: + * + * Please remove every GPRW-, Name6x-, PTSWAK-, FixShutdown-, WakeScren-Patches or similar prior using. + * If you adapt this patches to other models, check the occurence of the used variables and methods on your own DSDT beforehand. + * + * Depends on /patches/OpenCore Patches/ Sleep.plist + */ + +DefinitionBlock ("", "SSDT", 1, "tyler", "_Sleep", 0x00002000) +{ + // Common utils from SSDT-Darwin.dsl + External (DTGP, MethodObj) // 5 Arguments + External (OSDW, MethodObj) // 0 Arguments + + + // Sleep-config from BIOS + External (S0ID, FieldUnitObj) // S0 enabled + External (STY0, FieldUnitObj) // S3 Enabled? + External (LWCP, FieldUnitObj) // LID control power + + // Package to signal to OS S3-capability. We'll add it if missing. + External (SS3, FieldUnitObj) // S3 Enabled? + + If (OSDW ()) + { + Debug = "Enabling comprehensive S3-patching..." + + // Enable S3 + // 0x00 enables S3 + // 0x02 disables S3 + STY0 = Zero + + // Disable S0 for now + S0ID = Zero + + // Enable LID control power + LWCP = One + + // This adds S3 for OSX, even when sleep=windows in bios. + If (STY0 == Zero && !CondRefOf (\_S3)) + { + Name (\_S3, Package (0x04) // _S3_: S3 System State + { + 0x05, + 0x05, + 0x00, + 0x00 + }) + + SS3 = One + } + } + + + Scope (_GPE) + { + // This tells xnu to evaluate _GPE.Lxx methods on resume + Method (LXEN, 0, NotSerialized) + { + Debug = "LXEN()" + + Return (One) + } + } + + + External (_SB.PCI0.LPCB.EC.AC._PSR, MethodObj) // 0 Arguments + External (_SB.PCI0.LPCB.EC._Q2A, MethodObj) // 0 Arguments + External (_SB.LID._LID, MethodObj) // 0 Arguments + External (ZPRW, MethodObj) // 2 ARguments + External (ZWAK, MethodObj) // 1 Arguments + + External (_SB.PCI0.LPCB.EC.HPLD, FieldUnitObj) + External (_SB.PCI0.GFX0.CLID, FieldUnitObj) + External (LIDS, FieldUnitObj) + External (PWRS, FieldUnitObj) + + // SLTP named on OSX but already taken on X1C6. Therefor named XLTP. + Name (XLTP, Zero) + + // Save sleep-state in SLTP on transition. Like a genuine Mac. + Method (_TTS, 1, NotSerialized) // _TTS: Transition To State + { + Debug = "_TTS() called with Arg0:" + Debug = Arg0 + + XLTP = Arg0 + } + + Scope (\) + { + // Patch _PRW-returns to match the original as closely as possible + // and remove instant wakeups and similar sleep-probs + Method (GPRW, 2, NotSerialized) + { + If (OSDW ()) + { + Local0 = Package (0x02) + { + Zero, + Zero + } + + Local0[Zero] = Arg0 + + If (Arg1 > 0x04) + { + Local0[One] = 0x04 + } + + Return (Local0) + } + Else + { + Return (ZPRW (Arg0, Arg1)) + } + } + + // Patch _WAK to fire missing LID-Open event and update AC-state + Method (_WAK, 1, Serialized) + { + Debug = "_WAK start: Arg0" + Debug = Arg0 + + // Save old lid-state + Local1 = \LIDS + + Debug = "_WAK - old lid state LIDS: " + Debug = \LIDS + + Local0 = ZWAK(Arg0) + + If (OSDW ()) + { + // Update lid-state + \LIDS = \_SB.PCI0.LPCB.EC.HPLD + \_SB.PCI0.GFX0.CLID = LIDS + + Debug = "_WAK - new lid state LIDS: " + Debug = \LIDS + + // Fire missing lid-open event if lid was closed before. + // Also notifies LID-device and sets LEDs to the right state on wake. + If (Local1 == Zero) + { + Debug = "_WAK - fire lid open-event " + + // Lid-open Event + \_SB.PCI0.LPCB.EC._Q2A () + } + + // Update ac-state + \PWRS = \_SB.PCI0.LPCB.EC.AC._PSR () + } + + Debug = "_WAK end - return Local0: " + Debug = Local0 + + If (OSDW ()) + { + Return (Package (0x02) + { + Zero, + Zero + }) + } + Else + { + Return (Local0) + } + } + } + + Scope (_SB) + { + // Sync S0-state between BIOS and OS + Method (LPS0, 0, NotSerialized) + { + Debug = "LPS0 - S0ID: " + Debug = S0ID + + // If S0ID is enabled, enable deep-sleep in OSX. Can be set above. + Return (S0ID) + } + + // Adds ACPI power-button-device + // https://github.com/daliansky/OC-little/blob/master/06-%E6%B7%BB%E5%8A%A0%E7%BC%BA%E5%A4%B1%E7%9A%84%E9%83%A8%E4%BB%B6/SSDT-PWRB.dsl + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (Zero) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (0x0B) + } + + Return (Zero) + } + } + } + + + External (_SB.PCI0.LPCB, DeviceObj) + External (_SB.PCI0.LPCB.EC.LID, DeviceObj) + External (_SB.PCI0.LPCB.EC.LED, MethodObj) // 2 Arguments + External (_SB.PCI0.LPCB.EC._Q2A, MethodObj) // 0 Arguments + External (_SB.PCI0.LPCB.EC._Q2B, MethodObj) // 0 Arguments + + + // Scope (_SB.PCI0.LPCB.EC.LID) + // { + // Name (AOAC, Zero) + // } + + Scope (_SB.PCI0.LPCB) + { + Method (_PS0, 0, Serialized) + { + If (OSDW () && S0ID == One) + { + Debug = "LPCB:_PS0" + Debug = "LPCB:_PS0 - old lid state LIDS: " + Debug = \LIDS + + Debug = "LPCB:_PS0 - hw lid state LIDS: " + Debug = \_SB.PCI0.LPCB.EC.HPLD + + Local1 = \LIDS + + \_SB.PCI0.LPCB.EC.LED (0x00, 0x80) + \_SB.PCI0.LPCB.EC.LED (0x0A, 0x80) + \_SB.PCI0.LPCB.EC.LED (0x07, 0x80) + + // Update lid-state + \LIDS = \_SB.PCI0.LPCB.EC.HPLD + \_SB.PCI0.GFX0.CLID = LIDS + + Debug = "LPCB:_PS0 - new lid state LIDS: " + Debug = \LIDS + + // Fire missing lid-open event if lid was closed before. + // Also notifies LID-device and sets LEDs to the right state on wake. + If (Local1 == Zero) + { + Debug = "LPCB:_PS0 - fire lid open-event " + + // Lid-open Event + \_SB.PCI0.LPCB.EC._Q2A () + } + + Sleep (200) /* Delay 200 */ + + // Update ac-state + \PWRS = \_SB.PCI0.LPCB.EC.AC._PSR () + + // Notify (\_SB.PWRB, 0x80) + } + + } + + Method (_PS3, 0, Serialized) + { + If (OSDW () && S0ID == One) + { + Debug = "LPCB:_PS3" + + \_SB.PCI0.LPCB.EC.LED (0x07, 0xA0) + \_SB.PCI0.LPCB.EC.LED (0x00, 0xA0) + \_SB.PCI0.LPCB.EC.LED (0x0A, 0xA0) + + // Update lid-state + \LIDS = \_SB.PCI0.LPCB.EC.HPLD + \_SB.PCI0.GFX0.CLID = LIDS + + Debug = "LPCB:_PS3 - lid state LIDS: " + Debug = \LIDS + + If (\LIDS == Zero) + { + Debug = "LPCB:_PS3 - fire lid close-event " + + // Lid-open Event + \_SB.PCI0.LPCB.EC._Q2B () + + // \_SB.PCI0.LPCB.EC.LED (0x00, 0xA0) + } + } + } + } + + + External (_SB.PCI0.LPCB.EC, DeviceObj) + + Scope (\_SB.PCI0.LPCB.EC) + { + Name (EWAI, Zero) + Name (EWAR, Zero) + } + + + External (_SB.PCI0.LPCB.EC.AC, DeviceObj) + + // Patching AC-Device so that AppleACPIACAdapter-driver loads. + // Device named ADP1 on Mac + // See https://github.com/khronokernel/DarwinDumped/blob/b6d91cf4a5bdf1d4860add87cf6464839b92d5bb/MacBookPro/MacBookPro14%2C1/ACPI%20Tables/DSL/DSDT.dsl#L7965 + Scope (\_SB.PCI0.LPCB.EC.AC) + { + Name (WK00, One) + + Method (SWAK, 1, NotSerialized) + { + Debug = "AC:SWAK()" + + WK00 = (Arg0 & 0x03) + + If (!WK00) + { + Debug = "AC:SWAK() - WK00 = One" + WK00 = One + } + } + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + // Lid-wake control power + Debug = "AC:_PRW() - LWCP = " + Debug = LWCP + + If (OSDW () || \LWCP) + { + Return (Package (0x02) + { + 0x17, + 0x04 + }) + } + Else + { + Return (Package (0x02) + { + 0x17, + 0x03 + }) + } + } + } +} +//EOF diff --git a/patches/SSDT-TB3.dsl b/patches/SSDT-TB3.dsl new file mode 100644 index 0000000..9f2ab95 --- /dev/null +++ b/patches/SSDT-TB3.dsl @@ -0,0 +1,6366 @@ +/** + * Thunderbolt For Alpine Ridge on X1C6 + * + * Large parts (link training and enumeration) + * taken from decompiled Mac AML. + * + * Implements mostly of the ACPI-part for handling Thunderbolt 3 on an Lenovo X1C6. Does power management and force power management for TB & USB 3.1. + * WIP but should be complete now. And full of bugs. Its largely untested. Intended to give a mostly complete and as native as possible experience. + * Pair with SSDT-XHC1.dsl (native USB 2.0/3.0), SSDT-XHC2.dsl (USB 3.1) & SSDT-PTS.dsl (handling sleep). + * See config.plist for details. + * + * Copyright (c) 2019 osy86 + * Copyleft (c) 2020 benben + * + * Debugging & Bug-reports: + * sudo dmesg|egrep -i "PMRD|ACPI Debug|Thunderbolt|usb"|less + * + * Platform-reference: https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/AcpiTables + * osy86-implementation: https://github.com/osy86/HaC-Mini/blob/master/ACPI/SSDT-TbtOnPCH.asl + */ +DefinitionBlock ("", "SSDT", 2, "tyler", "_TB3", 0x00001000) +{ + /* Support methods */ + External (DTGP, MethodObj) // 5 Arguments + // OS Is Darwin? + External (OSDW, MethodObj) // 0 Arguments + + /* Patching existing devices */ + External (\_SB.PCI0.RP09, DeviceObj) + External (\_SB.PCI0.RP09.LEDM, FieldUnitObj) + External (\_SB.PCI0.RP09.L23E, FieldUnitObj) + External (\_SB.PCI0.RP09.L23R, FieldUnitObj) + External (\_SB.PCI0.RP09.LDIS, FieldUnitObj) + External (\_SB.PCI0.RP09.PXSX, DeviceObj) + External (\_SB.PCI0.RP09.PXSX.TBDU, DeviceObj) + External (\_SB.PCI0.XHC1, DeviceObj) + + External (\_SB.PCI0.RP09.XINI, MethodObj) // original _INI patched by OC + External (\_SB.PCI0.RP09.XPS0, MethodObj) // original _PS0 patched by OC + External (\_SB.PCI0.RP09.XPS3, MethodObj) // original _PS3 patched by OC + + External (_SB.PCI0.RP09.UPSB.DSB2.XHC2, DeviceObj) + External (_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND, FieldUnitObj) + + // get PCI MMIO base + External (_SB.PCI0.GPCB, MethodObj) + // Get GPI Input Value + External (_SB_.GGII, MethodObj) // 1 Arguments + // Set GPI Input Value + External (_SB_.SGII, MethodObj) // 2 Arguments + // Get GPO Output Value + External (_SB_.GGOV, MethodObj) // 1 Arguments + // Set GPO Output Value + External (_SB_.SGOV, MethodObj) // 2 Arguments + // Get GPIO group index for GpioPad + External (GGRP, MethodObj) // 1 Arguments + // Get GPIO pin number for GpioPad + External (GNMB, MethodObj) // 1 Arguments + // Get GPIO register address + // This is internal library function + External (GADR, MethodObj) // 2 Arguments + // Memory mapped root port + External (MMRP, MethodObj) // 1 Arguments + // Memory mapped TB port + External (MMTB, MethodObj) // 1 Arguments + + External (TBSE, FieldUnitObj) // TB root port number + External (TBTS, FieldUnitObj) // TB enabled? + External (SLTP, IntObj) + + External (_GPE.XTFY, MethodObj) // 1 Arguments + + Scope (\_GPE) + { + Method (NTFY, 1, Serialized) + { + If (OSDW ()) + { + Debug = "TB:_GPE:NTFY()" + + \_SB.PCI0.RP09.UPSB.AMPE () + } + Else + { + XTFY(Arg0) + } + } + } + + Scope (\_SB) + { + Method (SGDI, 1, Serialized) + { + Local0 = GGRP (Arg0) + Local1 = GNMB (Arg0) + Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + OperationRegion (PDW0, SystemMemory, Local2, 0x04) + Field (PDW0, AnyAcc, NoLock, Preserve) + { + Offset (0x01), + TEMP, 2, + Offset (0x04) + } + + TEMP = One + } + + Method (SGDO, 1, Serialized) + { + Local0 = GGRP (Arg0) + Local1 = GNMB (Arg0) + Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + OperationRegion (PDW0, SystemMemory, Local2, 0x04) + Field (PDW0, AnyAcc, NoLock, Preserve) + { + Offset (0x01), + TEMP, 2, + Offset (0x04) + } + + TEMP = 0x02 + } + + Method (GGDV, 1, Serialized) + { + Local0 = GGRP (Arg0) + Local1 = GNMB (Arg0) + Local2 = (GADR (Local0, 0x02) + (Local1 * 0x08)) + OperationRegion (PDW0, SystemMemory, Local2, 0x04) + Field (PDW0, AnyAcc, NoLock, Preserve) + { + Offset (0x01), + TEMP, 2, + Offset (0x04) + } + + If (TEMP == One) + { + Return (One) + } + ElseIf (TEMP == 0x02) + { + Return (Zero) + } + Else + { + Return (One) + } + } + + } + + Scope (\_SB.PCI0.RP09) + { + Name (EICM, Zero) + Name (R020, Zero) // RP base/limit from UEFI + Name (R024, Zero) // RP prefetch base/limit from UEFI + Name (R028, Zero) + Name (R02C, Zero) + + Name (R118, Zero) // UPSB Pri Bus = RP Sec Bus (UEFI) + Name (R119, Zero) // UPSB Sec Bus = RP Sec Bus + 1 + Name (R11A, Zero) // UPSB Sub Bus = RP Sub Bus (UEFI) + Name (R11C, Zero) // UPSB IO base/limit = RP IO base/limit (UEFI) + Name (R120, Zero) // UPSB mem base/limit = RP mem base/limit (UEFI) + Name (R124, Zero) // UPSB pre base/limit = RP pre base/limit (UEFI) + Name (R128, Zero) + Name (R12C, Zero) + + Name (R218, Zero) // DSB0 Pri Bus = UPSB Sec Bus + Name (R219, Zero) // DSB0 Sec Bus = UPSB Sec Bus + 1 + Name (R21A, Zero) // DSB0 Sub Bus = UPSB Sub Bus + Name (R21C, Zero) // DSB0 IO base/limit = UPSB IO base/limit + Name (R220, Zero) // DSB0 mem base/limit = UPSB mem base/limit + Name (R224, Zero) // DSB0 pre base/limit = UPSB pre base/limit + Name (R228, Zero) + Name (R22C, Zero) + + Name (R318, Zero) // DSB1 Pri Bus = UPSB Sec Bus + Name (R319, Zero) // DSB1 Sec Bus = UPSB Sec Bus + 2 + Name (R31A, Zero) // DSB1 Sub Bus = no children + Name (R31C, Zero) // DSB1 disable IO + Name (R320, Zero) // DSB1 disable mem + Name (R324, Zero) // DSB1 disable prefetch + Name (R328, Zero) + Name (R32C, Zero) + + Name (R418, Zero) // DSB2 Pri Bus = UPSB Sec Bus + Name (R419, Zero) // DSB2 Sec Bus = UPSB Sec Bus + 3 + Name (R41A, Zero) // DSB2 Sub Bus = no children + Name (R41C, Zero) // DSB2 disable IO + Name (R420, Zero) // DSB2 disable mem + Name (R424, Zero) // DSB2 disable prefetch + Name (R428, Zero) + Name (R42C, Zero) + + Name (RVES, Zero) // DSB2 offset 0x564, unknown + Name (R518, Zero) // DSB4 Pri Bus = UPSB Sec Bus + Name (R519, Zero) // DSB4 Sec Bus = UPSB Sec Bus + 4 + Name (R51A, Zero) // DSB4 Sub Bus = no children + Name (R51C, Zero) // DSB4 disable IO + Name (R520, Zero) // DSB4 disable mem + Name (R524, Zero) // DSB4 disable prefetch + Name (R528, Zero) + Name (R52C, Zero) + + Name (R618, Zero) + Name (R619, Zero) + Name (R61A, Zero) + Name (R61C, Zero) + Name (R620, Zero) + Name (R624, Zero) + Name (R628, Zero) + Name (R62C, Zero) + + Name (RH10, Zero) // NHI0 BAR0 = DSB0 mem base + Name (RH14, Zero) // NHI0 BAR1 unused + Name (POC0, Zero) + + Name (TBH1, Zero) + Name (BICM, Zero) // Boot windows? + + /** + * Get PCI base address + * Arg0 = bus, Arg1 = device, Arg2 = function + */ + Method (MMIO, 3, NotSerialized) + { + Local0 = \_SB.PCI0.GPCB () // base address + Local0 += (Arg0 << 20) + Local0 += (Arg1 << 15) + Local0 += (Arg2 << 12) + Return (Local0) + } + + // OperationRegion (RSTR, SystemMemory, NHI1, 0x0100) + OperationRegion (RSTR, SystemMemory, NH10 + 0x39858, 0x0100) + Field (RSTR, DWordAcc, NoLock, Preserve) + { + CIOR, 32, + Offset (0xB8), + ISTA, 32, + Offset (0xF0), + ICME, 32 + } + + // OperationRegion (T2PM, SystemMemory, T2P1, 0x08) + // Field (T2PM, DWordAcc, NoLock, Preserve) + // { + // T2PR, 32, + // P2TR, 32 + // } + + // OperationRegion (RPSM, SystemMemory, 0xE00E4000, 0x54) + // Root port configuration base + OperationRegion (RPSM, SystemMemory, MMRP (TBSE), 0x54) + Field (RPSM, DWordAcc, NoLock, Preserve) + { + RPVD, 32, + RPR4, 8, + Offset (0x18), + RP18, 8, + RP19, 8, + RP1A, 8, + Offset (0x1C), + RP1C, 16, + Offset (0x20), + R_20, 32, + R_24, 32, + R_28, 32, + R_2C, 32, + Offset (0x52), + , 11, + RPLT, 1, + Offset (0x54) + } + + // OperationRegion (UPSM, SystemMemory, TUP1, 0x0548) + // UPSB (up stream port) configuration base + OperationRegion (UPSM, SystemMemory, MMTB (TBSE), 0x0550) + Field (UPSM, DWordAcc, NoLock, Preserve) + { + UPVD, 32, + UP04, 8, + Offset (0x08), + CLRD, 32, + Offset (0x18), + UP18, 8, + UP19, 8, + UP1A, 8, + Offset (0x1C), + UP1C, 16, + Offset (0x20), + UP20, 32, + UP24, 32, + UP28, 32, + UP2C, 32, + Offset (0xD2), + , 11, + UPLT, 1, + Offset (0xD4), + Offset (0x544), + UPMB, 1, + Offset (0x548), + T2PR, 32, + P2TR, 32 + } + + // OperationRegion (DNSM, SystemMemory, TDB1, 0xD4) + // DSB0 configuration base + OperationRegion (DNSM, SystemMemory, MMIO (UP19, 0, 0), 0xD4) + Field (DNSM, DWordAcc, NoLock, Preserve) + { + DPVD, 32, + DP04, 8, + Offset (0x18), + DP18, 8, + DP19, 8, + DP1A, 8, + Offset (0x1C), + DP1C, 16, + Offset (0x20), + DP20, 32, + DP24, 32, + DP28, 32, + DP2C, 32, + Offset (0xD2), + , 11, + DPLT, 1, + Offset (0xD4) + } + + // OperationRegion (DS3M, SystemMemory, TD11, 0x40) + // DSB1 configuration base + OperationRegion (DS3M, SystemMemory, MMIO (UP19, 1, 0), 0x40) + Field (DS3M, DWordAcc, NoLock, Preserve) + { + D3VD, 32, + D304, 8, + Offset (0x18), + D318, 8, + D319, 8, + D31A, 8, + Offset (0x1C), + D31C, 16, + Offset (0x20), + D320, 32, + D324, 32, + D328, 32, + D32C, 32 + } + + // OperationRegion (DS4M, SystemMemory, TD21, 0x0568) + // DSB2 configuration base + OperationRegion (DS4M, SystemMemory, MMIO (UP19, 2, 0), 0x0568) + Field (DS4M, DWordAcc, NoLock, Preserve) + { + D4VD, 32, + D404, 8, + Offset (0x18), + D418, 8, + D419, 8, + D41A, 8, + Offset (0x1C), + D41C, 16, + Offset (0x20), + D420, 32, + D424, 32, + D428, 32, + D42C, 32, + Offset (0x564), + DVES, 32 + } + + // OperationRegion (DS5M, SystemMemory, TD41, 0x40) + // DSB4 configuration base + OperationRegion (DS5M, SystemMemory, MMIO (UP19, 4, 0), 0x40) + Field (DS5M, DWordAcc, NoLock, Preserve) + { + D5VD, 32, + D504, 8, + Offset (0x18), + D518, 8, + D519, 8, + D51A, 8, + Offset (0x1C), + D51C, 16, + Offset (0x20), + D520, 32, + D524, 32, + D528, 32, + D52C, 32 + } + + // OperationRegion (NHIM, SystemMemory, TNH1, 0x40) + OperationRegion (NHIM, SystemMemory, MMIO (DP19, 0, 0), 0x40) + Field (NHIM, DWordAcc, NoLock, Preserve) + { + NH00, 32, + NH04, 8, + Offset (0x10), + NH10, 32, + NH14, 32 + } + + Method (_INI, 0, NotSerialized) // _INI: Initialize + { + Debug = "TB:_INI" + + \_SB.PCI0.RP09.XINI() + + If (!OSDW ()) + { + TBH1 = One + BICM = One + + Debug = "TB:_INI - Save Ridge Config on Boot ICM" + + R020 = R_20 /* \_SB_.PCI0.RP09.R_20 */ + R024 = R_24 /* \_SB_.PCI0.RP09.R_24 */ + R028 = R_28 /* \_SB_.PCI0.RP09.R_28 */ + R02C = R_2C /* \_SB_.PCI0.RP09.R_2C */ + R118 = UP18 /* \_SB_.PCI0.RP09.UP18 */ + R119 = UP19 /* \_SB_.PCI0.RP09.UP19 */ + R11A = UP1A /* \_SB_.PCI0.RP09.UP1A */ + R11C = UP1C /* \_SB_.PCI0.RP09.UP1C */ + R120 = UP20 /* \_SB_.PCI0.RP09.UP20 */ + R124 = UP24 /* \_SB_.PCI0.RP09.UP24 */ + R128 = UP28 /* \_SB_.PCI0.RP09.UP28 */ + R12C = UP2C /* \_SB_.PCI0.RP09.UP2C */ + R218 = DP18 /* \_SB_.PCI0.RP09.DP18 */ + R219 = DP19 /* \_SB_.PCI0.RP09.DP19 */ + R21A = DP1A /* \_SB_.PCI0.RP09.DP1A */ + R21C = DP1C /* \_SB_.PCI0.RP09.DP1C */ + R220 = DP20 /* \_SB_.PCI0.RP09.DP20 */ + R224 = DP24 /* \_SB_.PCI0.RP09.DP24 */ + R228 = DP28 /* \_SB_.PCI0.RP09.DP28 */ + R228 = DP28 /* \_SB_.PCI0.RP09.DP28 */ + R318 = D318 /* \_SB_.PCI0.RP09.D318 */ + R319 = D319 /* \_SB_.PCI0.RP09.D319 */ + R31A = D31A /* \_SB_.PCI0.RP09.D31A */ + R31C = D31C /* \_SB_.PCI0.RP09.D31C */ + R320 = D320 /* \_SB_.PCI0.RP09.D320 */ + R324 = D324 /* \_SB_.PCI0.RP09.D324 */ + R328 = D328 /* \_SB_.PCI0.RP09.D328 */ + R32C = D32C /* \_SB_.PCI0.RP09.D32C */ + R418 = D418 /* \_SB_.PCI0.RP09.D418 */ + R419 = D419 /* \_SB_.PCI0.RP09.D419 */ + R41A = D41A /* \_SB_.PCI0.RP09.D41A */ + R41C = D41C /* \_SB_.PCI0.RP09.D41C */ + R420 = D420 /* \_SB_.PCI0.RP09.D420 */ + R424 = D424 /* \_SB_.PCI0.RP09.D424 */ + R428 = D428 /* \_SB_.PCI0.RP09.D428 */ + R42C = D42C /* \_SB_.PCI0.RP09.D42C */ + RVES = DVES /* \_SB_.PCI0.RP09.DVES */ + R518 = D518 /* \_SB_.PCI0.RP09.D518 */ + R519 = D519 /* \_SB_.PCI0.RP09.D519 */ + R51A = D51A /* \_SB_.PCI0.RP09.D51A */ + R51C = D51C /* \_SB_.PCI0.RP09.D51C */ + R520 = D520 /* \_SB_.PCI0.RP09.D520 */ + R524 = D524 /* \_SB_.PCI0.RP09.D524 */ + R528 = D528 /* \_SB_.PCI0.RP09.D528 */ + R52C = D52C /* \_SB_.PCI0.RP09.D52C */ + RH10 = NH10 /* \_SB_.PCI0.RP09.NH10 */ + RH14 = NH14 /* \_SB_.PCI0.RP09.NH14 */ + + Debug = "TB:_INI - Store Complete" + Debug = "TB:_INI - ICM ready" + + Sleep (One) + ICMS () + } + } + + /** + * Boot ICM + */ + Method (ICMB, 0, NotSerialized) + { + If (BICM == One) + { + Debug = "TB:ICMB" + + If (!OSDW ()) + { + ICMS () + Debug = "TB:ICMB - Enable ICM on Boot, Complete" + SGOV (0x02060001, Zero) + SGDO (0x02060001) + Debug = "TB:ICMB - Enable ICM on Boot, Complete" + } + } + } + + // ICM Start ??? + Method (ICMS, 0, NotSerialized) + { + POC0 = One + + Debug = "TB:ICMS - ICME" + Debug = \_SB.PCI0.RP09.ICME + + If (\_SB.PCI0.RP09.ICME != 0x800001A6 && \_SB.PCI0.RP09.ICME != 0x800000A6) + { + If (\_SB.PCI0.RP09.CNHI ()) + { + Debug = "TB:ICMS - ICME" + Debug = \_SB.PCI0.RP09.ICME + + If (\_SB.PCI0.RP09.ICME != 0xFFFFFFFF) + { + SGDI (0x01070004) + \_SB.PCI0.RP09.WTLT () + + Debug = "TB:ICMS - ICME" + Debug = \_SB.PCI0.RP09.ICME + + If (!Local0 = (\_SB.PCI0.RP09.ICME & 0x80000000)) // NVM started means we need reset + { + \_SB.PCI0.RP09.ICME |= 0x06 // invert EN | enable CPU + Local0 = 1000 + While ((Local1 = (\_SB.PCI0.RP09.ICME & 0x80000000)) == Zero) + { + Local0-- + If (Local0 == Zero) + { + Break + } + + Sleep (One) + } + + Debug = "TB:ICMS - TB:ICME" + Debug = \_SB.PCI0.RP09.ICME + \_SB.SGOV (0x01070004, Zero) + \_SB.SGDO (0x01070004) + } + } + } + } + + \_SB.PCI0.RP09.POC0 = Zero + + // disable USB force power + SGOV (0x01070007, Zero) + SGDO (0x01070007) + } + + /** + * Send TBT command + */ + Method (TBTC, 1, Serialized) + { + Debug = "TB:TBTC - Send TBT command" + + P2TR = Arg0 + + Local0 = 0x64 + Local1 = T2PR /* \_SB_.PCI0.RP09.T2PR */ + + While ((Local2 = (Local1 & One)) == Zero) + { + If (Local1 == 0xFFFFFFFF) + { + Return (Zero) + } + + Local0-- + If (Local0 == Zero) + { + Break + } + + Local1 = T2PR /* \_SB_.PCI0.RP09.T2PR */ + Sleep (0x32) + } + + P2TR = Zero + + Return (Zero) + } + + /** + * Plug detection for Windows + */ + Method (CMPE, 0, Serialized) + { + Debug = "TB:CMPE - Plug detection for Windows" + + Notify (\_SB.PCI0.RP09, Zero) // Bus Check + } + + /** + * Configure NHI device + */ + Method (CNHI, 0, Serialized) + { + // Configure root port + Debug = "TB:CNHI - Configure NHI root" + + Local0 = 10 + + While (Local0) + { + R_20 = R020 // Memory Base/Limit + R_24 = R024 // Prefetch Base/Limit + R_28 = R028 /* \_SB_.PCI0.RP09.R028 */ + R_2C = R02C /* \_SB_.PCI0.RP09.R02C */ + + RPR4 = 0x07 // Command + + If (R020 == R_20) + { + Break + } + + Sleep (One) + + Local0-- + } + + If (R020 != R_20) // configure failed + { + Debug = "TB:CNHI - Configure NHI failed" + + Return (Zero) + } + + // Configure UPSB + Debug = "TB:CNHI - Configure UPSB" + + Local0 = 10 + + While (Local0) + { + UP18 = R118 // UPSB Pri Bus + UP19 = R119 // UPSB Sec Bus + UP1A = R11A // UPSB Sub Bus + UP1C = R11C // UPSB IO Base/Limit + UP20 = R120 // UPSB Memory Base/Limit + UP24 = R124 // UPSB Prefetch Base/Limit + UP28 = R128 /* \_SB_.PCI0.RP09.R128 */ + UP2C = R12C /* \_SB_.PCI0.RP09.R12C */ + UP04 = 0x07 // UPSB Command + + If (R119 == UP19) // read back check + { + Break + } + + Sleep (One) + + Local0-- + } + + If (R119 != UP19) // configure failed + { + Debug = "TB:CNHI - Configure UPSB failed" + + Return (Zero) + } + + Debug = "TB:CNHI - Wait for link training" + + If (WTLT () != One) + { + Debug = "TB:CNHI - Wait for link training failed" + + Return (Zero) + } + + // Configure DSB0 + Debug = "TB:CNHI - Configure DSB" + + Local0 = 10 + + While (Local0) + { + DP18 = R218 // Pri Bus + DP19 = R219 // Sec Bus + DP1A = R21A // Sub Bus + DP1C = R21C // IO Base/Limit + DP20 = R220 // Memory Base/Limit + DP24 = R224 // Prefetch Base/Limit + DP28 = R228 /* \_SB_.PCI0.RP09.R228 */ + DP2C = R22C /* \_SB_.PCI0.RP09.R22C */ + DP04 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 0 done" + + D318 = R318 // Pri Bus + D319 = R319 // Sec Bus + D31A = R31A // Sub Bus + D31C = R31C // IO Base/Limit + D320 = R320 // Memory Base/Limit + D324 = R324 // Prefetch Base/Limit + D328 = R328 /* \_SB_.PCI0.RP09.R328 */ + D32C = R32C /* \_SB_.PCI0.RP09.R32C */ + D304 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 3 done" + + D418 = R418 // Pri Bus + D419 = R419 // Sec Bus + D41A = R41A // Sub Bus + D41C = R41C // IO Base/Limit + D420 = R420 // Memory Base/Limit + D424 = R424 // Prefetch Base/Limit + D428 = R428 /* \_SB_.PCI0.RP09.R428 */ + D42C = R42C /* \_SB_.PCI0.RP09.R42C */ + DVES = RVES // DSB2 0x564 + D404 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 4 done" + + D518 = R518 // Pri Bus + D519 = R519 // Sec Bus + D51A = R51A // Sub Bus + D51C = R51C // IO Base/Limit + D520 = R520 // Memory Base/Limit + D524 = R524 // Prefetch Base/Limit + D528 = R528 /* \_SB_.PCI0.RP09.R528 */ + D52C = R52C /* \_SB_.PCI0.RP09.R52C */ + D504 = 0x07 // Command + Debug = "TB:CNHI - Configure NHI Dp 5 done" + + If (R219 == DP19) // read back check + { + Break + } + + Sleep (One) + Local0-- + } + + If (R219 != DP19) // configure failed + { + Debug = "TB:CNHI - Configure DSB failed" + + Return (Zero) + } + + Debug = "TB:CNHI - Wait for down link" + + If (WTDL () == One) + { + Debug = "TB:CNHI - Configure NHI DPs done" + } + Else + { + Return (Zero) + } + + // Configure NHI + Debug = "TB:CNHI - Configure NHI" + + Local0 = 100 + + While (Local0) + { + NH10 = RH10 // NHI BAR 0 + NH14 = RH14 // NHI BAR 1 + NH04 = 0x07 // NHI Command + + If (RH10 == NH10) // read back check + { + Break + } + + Sleep (One) + Local0-- + } + + // Debug = "TB:CNHI NHI BAR" + // Debug = NH10 + + If (RH10 != NH10) // configure failed + { + Return (Zero) + } + + Debug = "TB:CNHI - CNHI done" + + Return (One) + } + + /** + * Uplink check + */ + Method (UPCK, 0, Serialized) + { + Debug = "TB:UBCK - Uplink check - Upstream VID/DID =" + Debug = UPVD /* \_SB_.PCI0.RP09.UPVD */ + + // accepts every intel chip + If ((UPVD & 0xFFFF) == 0x8086) + { + Return (One) + } + + Return (Zero) + } + + /** + * Uplink training check + */ + Method (ULTC, 0, Serialized) + { + Debug = "TB:ULTC - Uplink training check" + + If (RPLT == Zero) + { + If (UPLT == Zero) + { + Return (One) + } + } + + Return (Zero) + } + + /** + * Wait for link training + */ + Method (WTLT, 0, Serialized) + { + Debug = "TB:WTLT - Wait for link training" + + Local0 = 2000 + Local1 = Zero + + While (Local0) + { + If (RPR4 == 0x07) + { + If (ULTC ()) + { + If (UPCK ()) + { + Local1 = One + Break + } + } + } + + Sleep (One) + Local0-- + } + + // Debug = "TB:WTLT LOOP=" + // Debug = Local0 + + Return (Local1) + } + + /** + * Downlink training check + */ + Method (DLTC, 0, Serialized) + { + Debug = "TB:DLTC - Downlink training check" + + If (RPLT == Zero) + { + If (UPLT == Zero) + { + If (DPLT == Zero) + { + Return (One) + } + } + } + + Return (Zero) + } + + /** + * Wait for downlink training + */ + Method (WTDL, 0, Serialized) + { + Debug = "TB:WTDL - Wait for downlink training" + + Local0 = 2000 + Local1 = Zero + + While (Local0) + { + If (RPR4 == 0x07) + { + If (DLTC ()) + { + If (UPCK ()) + { + Local1 = One + Break + } + } + } + + Sleep (One) + Local0-- + } + + // Debug = "TB:WTDL LOOP=" + // Debug = Local0 + + Return (Local1) + } + + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + /** + * Bring up PCI link + * Train downstream link + */ + Method (PCEU, 0, Serialized) + { + Debug = "TB:PCEU - Bring up PCI link" + + \_SB.PCI0.RP09.PRSR = Zero + + // Debug = "TB:PCEU - Put upstream bridge back into D0 " + If (\_SB.PCI0.RP09.PSTX != Zero) + { + // Debug = "TB:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.PSTX = Zero + } + + If (\_SB.PCI0.RP09.LDXX == One) + { + // Debug = "TB:PCEU - Clear link disable on upstream bridge" + // Debug = "TB:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.LDXX = Zero + } + + If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRTE != Zero) + { + // Debug = "TB:PCEU - XRST changed, restored = true" + \_SB.PCI0.RP09.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.NHI0.XRST (Zero) + } + } + + /** + * Bring down PCI link + */ + Method (PCDA, 0, Serialized) + { + Debug = "TB:PCDA - Bring down PCI link" + + If (\_SB.PCI0.RP09.POFX () != Zero) + { + \_SB.PCI0.RP09.PCIA = Zero + + // Debug = "TB:PCDA - Put upstream bridge into D3" + \_SB.PCI0.RP09.PSTX = 0x03 + + // Debug = "TB:PCDA - Set link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = One + + Local5 = (Timer + 0x00989680) + + While (Timer <= Local5) + { + // Debug = "TB:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.LACR == One) + { + If (\_SB.PCI0.RP09.LACT == Zero) + { + // Debug = "TB:PCDA - No link activity" + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) + { + // Debug = "TB:PCDA - VID/DID is -1" + Break + } + + Sleep (0x0A) + } + + // Debug = "TB:PCDA - disable GPIO" + \_SB.PCI0.RP09.GPCI = Zero + \_SB.PCI0.RP09.UGIO () + } + Else + { + Debug = "TB:PCDA - Not disabling" + } + + \_SB.PCI0.RP09.IIP3 = One + } + + /** + * Returns true if both TB and TB-USB are idle + */ + Method (POFX, 0, Serialized) + { + If (!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB) + { + Debug = "TB:POFX - TB & USB are both idle" + } + ElseIf (!\_SB.PCI0.RP09.RTBT) + { + Debug = "TB:POFX - USB active, TB idle" + } + ElseIf (!\_SB.PCI0.RP09.RUSB) + { + Debug = "TB:POFX - USB idle, TB active" + } + Else + { + Debug = "TB:POFX - WE SHOULDNT SEE THIS CASE, IF YOU DO, ITS A BUG :)" + } + + + Return ((!\_SB.PCI0.RP09.RTBT && !\_SB.PCI0.RP09.RUSB)) + } + + Name (GPCI, One) + Name (GNHI, One) + Name (GXCI, One) + Name (RTBT, One) + Name (RUSB, One) + Name (CTPD, Zero) + + /** + * Send power down ack to CP + */ + Method (CTBT, 0, Serialized) + { + Debug = "TB:CTBT - Send power down ack to CP" + + If ((GGDV (0x02060000) == One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + // If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + // Debug = "TB:CTBT - TBT domain is enabled" + Local2 = \_SB.PCI0.RP09.UPSB.CRMW (0x3C, Zero, 0x02, 0x04000000, 0x04000000) + + If (Local2 == Zero) + { + // Debug = "TB:CTBT - Set CP_ACK_POWERDOWN_OVERRIDE" + \_SB.PCI0.RP09.CTPD = One + } + } + } + + /** + * Toggle controller power + * Power controllers either up or down depending on the request. + * On Macs, there's two GPIO signals for controlling TB and XHC + * separately. If such signals exist, we need to find it. Otherwise + * we lose the power saving capabilities. + * Returns if controller is powered up + */ + Method (UGIO, 0, Serialized) + { + // Which controller is requested to be on? + Local0 = (\_SB.PCI0.RP09.GNHI || \_SB.PCI0.RP09.RTBT) // TBT + Local1 = (\_SB.PCI0.RP09.GXCI || \_SB.PCI0.RP09.RUSB) // USB + + // Debug = "TB:UGIO - TBT-state:" + // Debug = Local0 + // Debug = "TB:UGIO - usb-state:" + // Debug = Local1 + + If (\_SB.PCI0.RP09.GPCI == Zero) + { + Debug = "TB:UGIO - PCI wants off (GPCI = Zero)" + } + Else + { + Debug = "TB:UGIO - PCI wants on (GPCI = One)" + } + + If (\_SB.PCI0.RP09.GNHI == Zero) + { + Debug = "TB:UGIO - NHI wants off (GNHI = Zero)" + } + Else + { + Debug = "TB:UGIO - NHI wants on (GNHI = One)" + } + + If (\_SB.PCI0.RP09.GXCI == Zero) + { + Debug = "TB:UGIO - XHCI wants off (GXCI = Zero)" + } + Else + { + Debug = "TB:UGIO - XHCI wants on (GXCI = One)" + } + + If (\_SB.PCI0.RP09.RTBT == Zero) + { + Debug = "TB:UGIO - TBT allows off (RTBT = Zero)" + } + Else + { + Debug = "TB:UGIO - TBT forced on (RTBT = One)" + } + + If (\_SB.PCI0.RP09.RUSB == Zero) + { + Debug = "TB:UGIO - USB allows off (RUSB = Zero)" + } + Else + { + Debug = "TB:UGIO - USB forced on (RUSB = One)" + } + + // NHI controller wants to be on + If (\_SB.PCI0.RP09.GPCI != Zero) + { + // if neither are requested to be on but the NHI controller + // needs to be up, then we go ahead and power it on anyways + If ((Local0 == Zero) && (Local1 == Zero)) + { + Local0 = One + Local1 = One + } + } + + // If (Local0 == Zero) + // { + // Debug = "TB:UGIO - TBT GPIO should be off" + // } + // Else + // { + // Debug = "TB:UGIO - TBT GPIO should be on" + // } + + // If (Local1 == Zero) + // { + // Debug = "TB:UGIO - USB GPIO should be off" + // } + // Else + // { + // Debug = "TB:UGIO - USB GPIO should be on" + // } + + Local2 = Zero + + If (Local0 != Zero) + { + // Debug = "TB:UGIO - Make sure TBT is on" + If (GGDV (0x02060000) == Zero) + { + // Debug = "TB:UGIO - Turn on TBT GPIO" + SGDI (0x02060000) + Local2 = One + \_SB.PCI0.RP09.CTPD = Zero + + Debug = "TB:UGIO - Enable TB" + } + } + + If (Local1 != Zero) + { + // Debug = "TB:UGIO - Make sure USB is on" + If (GGDV (0x02060001) == Zero) + { + // Debug = "TB:UGIO - Turn on USB GPIO" + SGDI (0x02060001) + Local2 = One + + Debug = "TB:UGIO - Enable USB" + } + } + + If (Local2 != Zero) + { + Sleep (0x01F4) + } + + Local3 = Zero + + If (Local0 == Zero) + { + // Debug = "TB:UGIO - Make sure TBT is off" + + If (GGDV (0x02060000) == One) + { + \_SB.PCI0.RP09.CTBT () + + If (\_SB.PCI0.RP09.CTPD != Zero) + { + // Debug = "TB:UGIO - Turn off TBT GPIO" + SGOV (0x02060000, Zero) + SGDO (0x02060000) + Local3 = One + + Debug = "TB:UGIO - Disable TB" + } + Else + { + // Debug = "TB:UGIO - CP_ACK_POWERDOWN_OVERRIDE not configured, cannot turn off TBT GPIO" + } + } + } + + If (Local1 == Zero) + { + // Debug = "TB:UGIO - Make sure USB is off" + If (GGDV (0x02060001) == One) + { + // Debug = "TB:UGIO - Turn off USB GPIO" + SGOV (0x02060001, Zero) + SGDO (0x02060001) + Local3 = One + + Debug = "TB:UGIO - Disable USB" + } + } + + If (Local3 != Zero) + { + Sleep (0x64) + } + + If (Local2 != Zero) + { + // Debug = "TB:UGIO - Either TB or USB powerstate changed" + } + + // One if status of TB or USB changed to on + Return (Local2) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:_PS0" + + \_SB.PCI0.RP09.XPS0() + + If (OSDW ()) + { + PCEU () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:_PS3" + + If (OSDW ()) + { + If (\_SB.PCI0.RP09.POFX () != Zero) + { + \_SB.PCI0.RP09.CTBT () + } + + PCDA () + } + + \_SB.PCI0.RP09.XPS3() + } + + Method (TGPE, 0, Serialized) + { + Debug = "TB:TGPE" + + Notify (\_SB.PCI0.RP09, 0x02) // Device Wake + } + + Method (UTLK, 2, Serialized) + { + Debug = "TB:UTLK" + + Local0 = Zero + + // if CIO force power is zero + If ((GGOV (0x02060000) == Zero) && (GGDV (0x02060000) == Zero)) + // If (Zero) + { + \_SB.PCI0.RP09.PSTX = Zero + While (One) + { + If (\_SB.PCI0.RP09.LDXX == One) + { + \_SB.PCI0.RP09.LDXX = Zero + } + + // here, we force CIO power on + SGDI (0x02060000) + Local1 = Zero + Local2 = (Timer + 0x00989680) + + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Break + } + + Sleep (0x0A) + } + + Sleep (Arg1) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Local1 = One + Break + } + + Sleep (0x0A) + } + + If (Local1 == One) + { + \_SB.PCI0.RP09.MABT = One + Break + } + + If (Local0 == 0x04) + { + Break + } + + Local0++ + // CIO force power back to 0 + SGOV (0x02060000, Zero) + SGDO (0x02060000) + Sleep (0x03E8) + } + } + + Debug = "UTLK: Up Stream VID/DID =" + Debug = \_SB.PCI0.RP09.UPSB.AVND + Debug = "UTLK: Root Port VID/DID =" + Debug = \_SB.PCI0.RP09.AVND + // Debug = "UTLK: Root Port PRIB =" + // Debug = \_SB.PCI0.RP09.PRIB + // Debug = "UTLK: Root Port SECB =" + // Debug = \_SB.PCI0.RP09.SECB + // Debug = "UTLK: Root Port SUBB =" + // Debug = \_SB.PCI0.RP09.SUBB + } + + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (HD94, PCI_Config, 0x0D94, 0x08) + Field (HD94, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + PLEQ, 1, + Offset (0x08) + } + + OperationRegion (A1E1, PCI_Config, 0x40, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDXX, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0xA0, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTX, 2 + } + + // OperationRegion (OE2H, PCI_Config, 0xE2, One) + // Field (OE2H, ByteAcc, NoLock, Preserve) + // { + // , 2, + // L23E, 1, + // L23D, 1 + // } + + // OperationRegion (DMIH, PCI_Config, 0x0324, One) + // Field (DMIH, ByteAcc, NoLock, Preserve) + // { + // , 3, + // LEDM, 1 + // } + + OperationRegion (A1E3, PCI_Config, 0x0200, 0x20) + Field (A1E3, ByteAcc, NoLock, Preserve) + { + Offset (0x14), + Offset (0x16), + PSTS, 4 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + /** + * PXSX replaced by UPSB + */ + Scope (PXSX) + { + Method (_STA, 0, NotSerialized) + { + Return (Zero) // hidden + } + } + + Device (UPSB) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (TBTS != One) + { + Return (Zero) + } + + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + /** + * Enable downstream link + */ + Method (PCED, 0, Serialized) + { + Debug = "TB:UPSB:PCED - Enable downstream link" + // Debug = "TB:UPSB:PCED - enable GPIO" + \_SB.PCI0.RP09.GPCI = One + + // power up the controller + If (\_SB.PCI0.RP09.UGIO () != Zero) + { + // Debug = "TB:UPSB:PCED - GPIOs changed, restored = true" + \_SB.PCI0.RP09.PRSR = One + } + + Local0 = Zero + Local1 = Zero + + If (Local1 == Zero) + { + If (\_SB.PCI0.RP09.IIP3 != Zero) + { + \_SB.PCI0.RP09.PRSR = One + Local0 = One + + // Debug = "TB:UPSB:PCED - Set link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = One + } + } + + Local5 = (Timer + 0x00989680) + + // Debug = "TB:UPSB:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" + // Debug = \_SB.PCI0.RP09.PRSR + + If (\_SB.PCI0.RP09.PRSR != Zero) + { + // Debug = "TB:UPSB:PCED - Wait for power up" + Sleep (0x1E) + + If ((Local0 != Zero) || (Local1 != Zero)) + { + \_SB.PCI0.RP09.TSPD = One + + If (Local1 != Zero) {} + ElseIf (Local0 != Zero) + { + // Debug = "TB:UPSB:PCED - Clear link disable on upstream bridge" + \_SB.PCI0.RP09.LDXX = Zero + } + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + // Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + // Debug = "TB:UPSB:PCED - GENSTEP WA - Link training cleared and link is active" + Break + } + + Sleep (0x0A) + } + + Sleep (0x78) + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:PCED - PEG WA - Wait for config space..." + + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + // Debug = "TB:UPSB:PCED - PEG WA - Read VID/DID - _SB.PCI0.RP09.UPSB.AVND:" + Debug = \_SB.PCI0.RP09.UPSB.AVND + + Break + } + + Sleep (0x0A) + } + + \_SB.PCI0.RP09.TSPD = 0x03 + \_SB.PCI0.RP09.LRTN = One + } + + // Debug = "TB:UPSB:PCED - Wait for downstream bridge to appear" + Local5 = (Timer + 0x00989680) + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:PCED - Wait for link training..." + + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + // Debug = "TB:UPSB:PCED - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + // Debug = "TB:UPSB:PCED - Link training cleared and link is active" + Break + } + + Sleep (0x0A) + } + + Sleep (0xFA) + } + + \_SB.PCI0.RP09.PRSR = Zero + While (Timer <= Local5) + { + // Debug = "TB:UPSB:PCED - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + // Debug = "TB:UPSB:PCED - Read VID/DID" + Break + } + + Sleep (0x0A) + } + + If (\_SB.PCI0.RP09.CSPD != 0x03) + { + If (\_SB.PCI0.RP09.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.TSPD != 0x03) + { + \_SB.PCI0.RP09.TSPD = 0x03 + } + + If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) + { + \_SB.PCI0.RP09.UPSB.TSPD = 0x03 + } + + \_SB.PCI0.RP09.LRTN = One + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + \_SB.PCI0.RP09.PCIA = One + Local1 = One + Break + } + } + ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && + (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + \_SB.PCI0.RP09.PCIA = One + Local1 = One + Break + } + + Sleep (0x0A) + } + } + Else + { + \_SB.PCI0.RP09.PCIA = One + } + } + Else + { + \_SB.PCI0.RP09.PCIA = One + } + } + Else + { + \_SB.PCI0.RP09.PCIA = One + } + + \_SB.PCI0.RP09.IIP3 = Zero + } + + /** + * Hotplug notify - Called by ACPI + */ + Method (AMPE, 0, Serialized) + { + Debug = "TB:UPSB:AMPE - Hotplug notify called by ACPI" + + Notify (\_SB.PCI0.RP09.UPSB.DSB0.NHI0, Zero) // Bus Check + } + + /** + * Hotplug notify + * + * MUST called by NHI driver indicating cable plug-in + * This passes the message to the XHC driver + */ + Method (UMPE, 0, Serialized) + { + Debug = "TB:UPSB:UMPE - Hotplug notify on cable called by NHI" + + If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2)) + { + Debug = "TB:UPSB:UMPE - Notified XHC2" + Notify (\_SB.PCI0.RP09.UPSB.DSB2.XHC2, Zero) // Bus Check + } + + If (CondRefOf (\_SB.PCI0.XHC1)) + { + Debug = "TB:UPSB:UMPE - Notified XHC1" + Notify (\_SB.PCI0.XHC1, Zero) // Bus Check + } + } + + Name (MDUV, One) // plug status + + /** + * Cable status callback + * Called from NHI driver on hotplug + */ + Method (MUST, 1, Serialized) + { + // Debug = "TB:UPSB:MUST - Cable status callback from NHI" + // Debug = "TB:UPSB:MUST - Plug status Arg0: " + // Debug = Arg0 + // Debug = "TB:UPSB:MUST - Plug status MDUV: " + // Debug = MDUV + + If (OSDW ()) + { + If (MDUV != Arg0) + { + If (Arg0 == One) + { + Debug = "TB:UPSB:MUST - Cable status callback from NHI - status changed - plugged (MDUV = One)" + } + Else + { + Debug = "TB:UPSB:MUST - Cable status callback from NHI - status changed - unplugged (MDUV = Zero)" + } + + MDUV = Arg0 + UMPE () + } + Else + { + Debug = "TB:UPSB:MUST - Cable status callback from NHI - status unchanged" + } + } + + Return (Zero) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:UPSB:_PS0" + + If (OSDW ()) + { + PCED () // enable downlink + + // some magical commands to CIO + \_SB.PCI0.RP09.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200) + \_SB.PCI0.RP09.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200) + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:UPSB:_PS3" + + If (!OSDW ()) + { + If (\_SB.PCI0.RP09.UPCK () == Zero) + { + // Debug = "TB:UPSB:_PS3 calling UTLK _PS3" + \_SB.PCI0.RP09.UTLK (One, 0x03E8) + } + Else + { + // Debug = "TB:UPSB:_PS3 - UTLK OK" + } + + \_SB.PCI0.RP09.TBTC (0x05) + } + } + + OperationRegion (H548, PCI_Config, 0x0548, 0x20) + Field (H548, DWordAcc, Lock, Preserve) + { + T2PC, 32, + PC2T, 32 + } + + OperationRegion (H530, PCI_Config, 0x0530, 0x0C) + Field (H530, DWordAcc, Lock, Preserve) + { + DWIX, 13, + PORT, 6, + SPCE, 2, + CMD0, 1, + CMD1, 1, + CMD2, 1, + , 6, + PROG, 1, + TMOT, 1, + WDAT, 32, + RDAT, 32 + } + + /** + * CIO write + */ + Method (CIOW, 4, Serialized) + { + // Debug = "TB:UPSB:CIOW" + + WDAT = Arg3 + // Debug = "TB:UPSB:CIOW - WDAT" + // Debug = WDAT /* \_SB_.PCI0.RP09.UPSB.WDAT */ + + DWIX = Arg0 + PORT = Arg1 + SPCE = Arg2 + CMD0 = One + CMD1 = Zero + CMD2 = Zero + TMOT = Zero + PROG = One + + Local1 = One + Local0 = 0x2710 + + While (Zero < Local0) + { + If (PROG == Zero) + { + Local1 = Zero + Break + } + + Stall (0x19) + Local0-- + } + + If (Local1 == Zero) + { + Local1 = TMOT /* \_SB_.PCI0.RP09.UPSB.TMOT */ + } + + If (Local1 != Zero) + { + Debug = "TB:UPSB:CIOW - Error" + Debug = Local1 + } + + Return (Local1) + } + + /** + * CIO read + */ + Method (CIOR, 3, Serialized) + { + // Debug = "TB:UPSB:CIOR" + + RDAT = Zero + DWIX = Arg0 + PORT = Arg1 + SPCE = Arg2 + CMD0 = Zero + CMD1 = Zero + CMD2 = Zero + TMOT = Zero + PROG = One + + Local1 = One + Local0 = 0x2710 + + While (Zero < Local0) + { + If (PROG == Zero) + { + Local1 = Zero + Break + } + + Stall (0x19) + Local0-- + } + + If (Local1 == Zero) + { + Local1 = TMOT /* \_SB_.PCI0.RP09.UPSB.TMOT */ + } + + If (Local1) + { + Debug = "TB:UPSB:CIOR - Error" + Debug = Local1 + } + + // Debug = "TB:UPSB:CIOR - RDAT" + // Debug = RDAT /* \_SB_.PCI0.RP09.UPSB.RDAT */ + + If (Local1 == Zero) + { + Return (Package (0x02) + { + Zero, + RDAT + }) + } + Else + { + Return (Package (0x02) + { + One, + RDAT + }) + } + } + + /** + * CIO Read Modify Write + */ + Method (CRMW, 5, Serialized) + { + // Debug = "TB:UPSB:CRMW" + + // Debug = "TB:UPSB:CRMW - AVND:" + // Debug = \_SB.PCI0.RP09.UPSB.AVND + + // Debug = "TB:UPSB:CRMW - GGDV (0x02060000):" + // Debug = GGDV (0x02060000) + + // Debug = "TB:UPSB:CRMW - GGDV (0x02060001):" + // Debug = GGDV (0x02060001) + + + Local1 = One + If (((GGDV (0x02060000) == One) || (GGDV (0x02060001) == One)) && + (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + // If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + // Debug = "TB:UPSB:CRMW - TBT domain is enabled" + Local3 = Zero + + While (Local3 <= 0x04) + { + Local2 = CIOR (Arg0, Arg1, Arg2) + If (DerefOf (Local2 [Zero]) == Zero) + { + Local2 = DerefOf (Local2 [One]) + // Debug = "TB:UPSB:CRMW - Read Value" + // Debug = Local2 + + Local2 &= ~Arg4 + Local2 |= Arg3 + // Debug = "TB:UPSB:CRMW - Write Value" + // Debug = Local2 + + Local2 = CIOW (Arg0, Arg1, Arg2, Local2) + + If (Local2 == Zero) + { + Local2 = CIOR (Arg0, Arg1, Arg2) + + If (DerefOf (Local2 [Zero]) == Zero) + { + Local2 = DerefOf (Local2 [One]) + // Debug = "TB:UPSB:CRMW - Read Value 2" + // Debug = Local2 + + Local2 &= Arg4 + + If (Local2 == Arg3) + { + // Debug = "TB:UPSB:CRMW - Success" + + Local1 = Zero + + Break + } + } + } + } + + Local3++ + Sleep (0x64) + } + } + + If (Local1 != Zero) + { + Debug = "TB:UPSB:CRMW - Error value" + Debug = Local1 + } + + Return (Local1) + } + + /** + * Used in PTS/WAK + */ + Method (LSTX, 2, Serialized) + { + Debug = "TB:UPSB:LSTX" + + If (T2PC != 0xFFFFFFFF) + { + Local0 = Zero + If ((T2PC & One) && One) + { + Local0 = One + } + + If (Local0 == Zero) + { + Local1 = 0x2710 + While (Zero < Local1) + { + If (T2PC == Zero) + { + Break + } + + Stall (0x19) + Local1-- + } + + If (Zero == Local1) + { + Local0 = One + } + } + + If (Local0 == Zero) + { + Local1 = One + Local1 |= 0x14 + Local1 |= (Arg0 << 0x08) + Local1 |= (Arg1 << 0x0C) + Local1 |= 0x00400000 + PC2T = Local1 + } + + If (Local0 == Zero) + { + Local1 = 0x2710 + + While (Zero < Local1) + { + If (T2PC == 0x15) + { + Break + } + + Stall (0x19) + Local1-- + } + + If (Zero == Local1) + { + Local0 = One + } + } + + Sleep (0x0A) + PC2T = Zero + } + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + /** + * Enable Upstream link + */ + Method (PCEU, 0, Serialized) + { + Debug = "TB:UPSB:DSB0:PCEU - Enable Upstream link" + + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero + + // Debug = "TB:UPSB:DSB0:PCEU - Put upstream bridge back into D0 " + If (\_SB.PCI0.RP09.UPSB.DSB0.PSTA != Zero) + { + // Debug = "TB:UPSB:DSB0:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.PSTA = Zero + } + + If (\_SB.PCI0.RP09.UPSB.DSB0.LDIS == One) + { + // Debug = "TB:UPSB:DSB0:PCEU - Clear link disable on upstream bridge" + // Debug = "TB:UPSB:DSB0:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB0.LDIS = Zero + } + } + + /** + * Bring down PCI link + */ + Method (PCDA, 0, Serialized) + { + Debug = "TB:UPSB:DSB0:PCDA - Bring down PCI link" + + If (\_SB.PCI0.RP09.UPSB.DSB0.POFX () != Zero) + { + \_SB.PCI0.RP09.UPSB.DSB0.PCIA = Zero + + // Debug = "TB:UPSB:DSB0:PCDA - Put upstream bridge into D3" + \_SB.PCI0.RP09.UPSB.DSB0.PSTA = 0x03 + + // Debug = "TB:UPSB:DSB0:PCDA - Set link disable on upstream bridge" + \_SB.PCI0.RP09.UPSB.DSB0.LDIS = One + + Local5 = (Timer + 0x00989680) + While (Timer <= Local5) + { + // Debug = "TB:UPSB:DSB0:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == One) + { + If (\_SB.PCI0.RP09.UPSB.DSB0.LACT == Zero) + { + // Debug = "TB:UPSB:DSB0:PCDA - No link activity" + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND == 0xFFFFFFFF) + { + // Debug = "TB:UPSB:DSB0:PCDA - VID/DID is -1" + Break + } + + Sleep (0x0A) + } + + // Debug = "TB:UPSB:DSB0:PCDA - disable GPIO & run UGIO()" + \_SB.PCI0.RP09.GNHI = Zero + \_SB.PCI0.RP09.UGIO () + } + Else + { + // Debug = "TB:UPSB:DSB0:PCDA - Not disabling" + } + + \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = One + } + + /** + * Check if TB is idle + */ + Method (POFX, 0, Serialized) + { + If (!\_SB.PCI0.RP09.RTBT) + { + Debug = "TB:UPSB:DSB0:POFX - TB is idle (RTBT = Zero)" + } + Else + { + Debug = "TB:UPSB:DSB0:POFX - TB is active (RTBT != Zero)" + } + + Return (!\_SB.PCI0.RP09.RTBT) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:UPSB:DSB0:_PS0" + + If (OSDW ()) + { + PCEU () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:UPSB:DSB0:_PS3" + + If (OSDW ()) + { + PCDA () + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (OSDW ()) + { + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package (0x02) + { + "PCIHotplugCapable", + Zero + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Return (Zero) + } + + /** + * Thunderbolt NHI controller + */ + Device (NHI0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String + + /** + * Enable downstream link + */ + Method (PCED, 0, Serialized) + { + Debug = "TB:UPSB:NHI0:PCED - Enable downstream link" + + // Debug = "TB:UPSB:NHI0:PCED - enable GPIO" + \_SB.PCI0.RP09.GNHI = One + + // we should not need to force power since + // UPSX init should already have done so! + If (\_SB.PCI0.RP09.UGIO () != Zero) + { + // Debug = "TB:UPSB:NHI0:PCED - GPIOs changed, restored = true" + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = One + } + + Local0 = Zero + Local1 = Zero + Local5 = (Timer + 0x00989680) + + // Debug = "TB:UPSB:NHI0:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" + Debug = \_SB.PCI0.RP09.UPSB.DSB0.PRSR + + If (\_SB.PCI0.RP09.UPSB.DSB0.PRSR != Zero) + { + // Debug = "TB:UPSB:NHI0:PCED - Wait for power up" + // Debug = "TB:UPSB:NHI0:PCED - Wait for downstream bridge to appear" + Local5 = (Timer + 0x00989680) + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:NHI0:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.UPSB.DSB0.LACR == Zero) + { + If (\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) + { + // Debug = "TB:UPSB:NHI0:PCED - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.UPSB.DSB0.LTRN != One) && (\_SB.PCI0.RP09.UPSB.DSB0.LACT == One)) + { + // Debug = "TB:UPSB:NHI0:PCED - Link training cleared and link is active" + Break + } + + Sleep (0x0A) + } + + Sleep (0x96) + } + + \_SB.PCI0.RP09.UPSB.DSB0.PRSR = Zero + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:NHI0:PCED - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.DSB0.NHI0.AVND != 0xFFFFFFFF) + { + // Debug = "TB:UPSB:NHI0:PCED - Read VID/DID" + \_SB.PCI0.RP09.UPSB.DSB0.PCIA = One + Break + } + + Sleep (0x0A) + } + + \_SB.PCI0.RP09.UPSB.DSB0.IIP3 = Zero + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + /** + * Run Time Power Check + * Called by NHI driver when link is idle. + * Once both XHC and NHI idle, we can power down. + */ + Method (RTPC, 1, Serialized) + { + If (OSDW ()) + { + If (Arg0 <= One) + { + If (Arg0 == One) + { + Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - Running" + } + + If (Arg0 == Zero) + { + Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - Idle" + } + + \_SB.PCI0.RP09.RTBT = Arg0 + } + Else + { + Debug = "TB:UPSB:NHI0:RTPC - TB Run Time Power Check - ??? - Arg0: " + Debug = Arg0 + } + } + + Return (Zero) + } + + /** + * Cable detection callback + * Called by NHI driver on hotplug + */ + Method (MUST, 1, Serialized) + { + Debug = "TB:UPSB:NHI0:MUST - Cable detection callback" + + Return (\_SB.PCI0.RP09.UPSB.MUST (Arg0)) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:UPSB:NHI0:_PS0" + + If (OSDW ()) + { + PCED () + \_SB.PCI0.RP09.CTBT () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:UPSB:NHI0:_PS3" + } + + Method (TRPE, 2, Serialized) + { + Debug = "TB:UPSB:NHI0:TRPE - args:" + Debug = Arg0 + Debug = Arg1 + + If (OSDW ()) + { + If (Arg0 <= One) + { + If (Arg0 == Zero) + { + \_SB.PCI0.RP09.PSTX = 0x03 + \_SB.PCI0.RP09.LDXX = One + + Local0 = (Timer + 0x00989680) + + While (Timer <= Local0) + { + If (\_SB.PCI0.RP09.LACR == One) + { + If (\_SB.PCI0.RP09.LACT == Zero) + { + Break + } + } + ElseIf (\_SB.PCI0.RP09.UPSB.AVND == 0xFFFFFFFF) + { + Break + } + + Sleep (0x0A) + } + + SGOV (0x02060000, Zero) + SGDO (0x02060000) + } + Else + { + Local0 = Zero + + // Debug = "TB:UPSB:NHI0:TRPE GGOV (0x02060000):" + // Debug = GGOV (0x02060000) + + // Debug = "TB:UPSB:NHI0:TRPE GGOV (0x02060000):" + // Debug = GGDV (0x02060000) + + If ((GGOV (0x02060000) == Zero) && (GGDV (0x02060000) == Zero)) + // If (Zero) + { + \_SB.PCI0.RP09.PSTX = Zero + + While (One) + { + If (\_SB.PCI0.RP09.LDXX == One) + { + \_SB.PCI0.RP09.LDXX = Zero + } + + SGDI (0x02060000) + + Local1 = Zero + Local2 = (Timer + 0x00989680) + + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If (\_SB.PCI0.RP09.LTRN != One) + { + Break + } + } + ElseIf ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) + { + Break + } + + Sleep (0x0A) + } + + Sleep (Arg1) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF) + { + Local1 = One + Break + } + + Sleep (0x0A) + } + + If (Local1 == One) + { + MABT = One + Break + } + + If (Local0 == 0x04) + { + Return (Zero) + } + + Local0++ + SGOV (0x02060000, Zero) + SGDO (0x02060000) + Sleep (0x03E8) + } + + If (\_SB.PCI0.RP09.CSPD != 0x03) + { + If (\_SB.PCI0.RP09.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.UPSB.SSPD == 0x03) + { + If (\_SB.PCI0.RP09.TSPD != 0x03) + { + \_SB.PCI0.RP09.TSPD = 0x03 + } + + If (\_SB.PCI0.RP09.UPSB.TSPD != 0x03) + { + \_SB.PCI0.RP09.UPSB.TSPD = 0x03 + } + + \_SB.PCI0.RP09.LRTN = One + Local2 = (Timer + 0x00989680) + While (Timer <= Local2) + { + If (\_SB.PCI0.RP09.LACR == Zero) + { + If ((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + Local1 = One + Break + } + } + ElseIf (((\_SB.PCI0.RP09.LTRN != One) && (\_SB.PCI0.RP09.LACT == One)) && + (\_SB.PCI0.RP09.UPSB.AVND != 0xFFFFFFFF)) + { + Local1 = One + Break + } + + Sleep (0x0A) + } + } + } + } + } + } + } + } + + Return (Zero) + } + + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + + Local0 = Package (0x05) + { + "ThunderboltDROM", + Buffer (0x6F) + { + /* 0x00 */ 0x61, // CRC8 checksum: 0x61 + /* 0x01 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x01, // Thunderbolt Bus 0, UID: 0x0109000000000000 + /* 0x09 */ 0x2b, 0xcc, 0xb9, 0xf7, // CRC32c checksum: 0xF7B9CC2B + /* 0x0D */ 0x01, // Device ROM Revision: 1 + /* 0x0E */ 0x62, 0x00, // Length: 98 (starting from previous byte) + /* 0x10 */ 0x09, 0x01, // Vendor ID: 0x109 + /* 0x12 */ 0x06, 0x17, // Device ID: 0x1706 + /* 0x14 */ 0x01, // Device Revision: 0x1 + /* 0x15 */ 0x2b, // EEPROM Revision: 43 + /* 0x16 1 */ 0x08, 0x81, 0x80, 0x02, 0x80, 0x00, 0x00, 0x00, + /* 0x1E 2 */ 0x08, 0x82, 0x90, 0x01, 0x80, 0x00, 0x00, 0x00, + /* 0x26 3 */ 0x08, 0x83, 0x80, 0x04, 0x80, 0x01, 0x00, 0x00, + /* 0x2E 4 */ 0x08, 0x84, 0x90, 0x03, 0x80, 0x01, 0x00, 0x00, + /* 0x36 5 */ 0x02, 0x85, + /* 0x38 6 */ 0x0b, 0x86, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0x43 7 */ 0x03, 0x87, 0x80, // PCIe xx:04.0 + /* 0x46 8 */ 0x05, 0x88, 0x50, 0x40, 0x00, + /* 0x4B 9 */ 0x05, 0x89, 0x50, 0x00, 0x00, + /* 0x50 A */ 0x05, 0x8a, 0x50, 0x00, 0x00, + /* 0x55 B */ 0x05, 0x8b, 0x50, 0x40, 0x00, + /* 0x5A 1 */ 0x09, 0x01, 0x4c, 0x65, 0x6e, 0x6f, 0x76, 0x6f, 0x00, // Vendor Name: "Lenovo" + /* 0x63 2 */ 0x0c, 0x02, 0x58, 0x31, 0x20, 0x43, 0x61, 0x72, 0x62, 0x6f, 0x6e, 0x00, // Device Name: "X1 Carbon" + }, + + "power-save", + One, + Buffer (One) + { + 0x00 // . + } + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + + /** + * Late sleep force power + * NHI driver sends a sleep cmd to TB controller + * But we might be sleeping at this time. So this will + * force the power on right before sleep. + */ + Method (SXFP, 1, Serialized) + { + Debug = "TB:UPSB:NHI0:SXFP - Late sleep force power - Arg0:" + Debug = Arg0 + + // Debug = "TB:UPSB:NHI0:SXFP - GGDV (0x02060001)" + // Debug = GGDV (0x02060001) + + If (Arg0 == Zero) + { + If (GGDV (0x02060001) == One) + { + SGOV (0x02060001, Zero) + SGDO (0x02060001) + Sleep (0x64) + } + + SGOV (0x02060000, Zero) + SGDO (0x02060000) + } + } + + Name (XRTE, Zero) + + Method (XRST, 1, Serialized) + { + Debug = "TB:UPSB:NHI0:XRST - Arg0:" + Debug = Arg0 + + If (Arg0 == Zero) + { + XRTE = Zero + If (SLTP == Zero) + { + // Debug = "TB:UPSB:NHI0:TRPE L23 Detect" + \_SB.PCI0.RP09.L23R = One + + Sleep (One) + + Local2 = Zero + + While (\_SB.PCI0.RP09.L23R) + { + If (Local2 > 0x04) + { + Break + } + + Sleep (One) + Local2++ + } + + // Debug = "TB:UPSB:NHI0:TRPE Clear LEDM" + \_SB.PCI0.RP09.LEDM = Zero + + SGDI (0x02060004) + } + } + ElseIf (Arg0 == One) + { + XRTE = One + If (SLTP == Zero) + { + \_SB.PCI0.RP09.PSTX = 0x03 + If (\_SB.PCI0.RP09.LACR == One) + { + If (\_SB.PCI0.RP09.LACT == Zero) + { + // Debug = "TB:UPSB:NHI0:XRST: Root Port LDIS - Skipping L23 Ready Request" + } + Else + { + // Debug = "TB:UPSB:NHI0:XRST Root Port Requesting L23 Ready" + \_SB.PCI0.RP09.L23E = One + + Sleep (One) + + Local2 = Zero + + While (\_SB.PCI0.RP09.L23E == One) + { + If (Local2 > 0x04) + { + Break + } + + Sleep (One) + Local2++ + } + + // Debug = "TB:UPSB:NHI0:XRST Root Port Set DMI L1 EN" + \_SB.PCI0.RP09.LEDM = One + } + } + + SGOV (0x02060004, Zero) + SGDO (0x02060004) + Sleep (0x4B) + } + } + } + } + } + + Device (DSB1) + { + Name (_ADR, 0x00010000) // _ADR: Address + Name (_SUN, One) // _SUN: Slot User Number + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB1.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB2) + { + Name (_ADR, 0x00020000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB2.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Name (IIP3, Zero) + Name (PRSR, Zero) + Name (PCIA, One) + + /** + * Enable upstream link + */ + Method (PCEU, 0, Serialized) + { + Debug = "TB:UPSB:DSB2:PCEU - Enable upstream link" + + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = Zero + + // Debug = "TB:UPSB:DSB2:PCEU - Put upstream bridge back into D0 " + If (\_SB.PCI0.RP09.UPSB.DSB2.PSTA != Zero) + { + // Debug = "TB:UPSB:DSB2:PCEU - exit D0, restored = true" + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB2.PSTA = Zero + } + + If (\_SB.PCI0.RP09.UPSB.DSB2.LDIS == One) + { + // Debug = "TB:UPSB:DSB2:PCEU - Clear link disable on upstream bridge" + // Debug = "TB:UPSB:DSB2:PCEU - clear link disable, restored = true" + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One + \_SB.PCI0.RP09.UPSB.DSB2.LDIS = Zero + } + } + + /** + * PCI disable link + */ + Method (PCDA, 0, Serialized) + { + Debug = "TB:UPSB:DSB2:PCDA - PCI disable link" + + If (\_SB.PCI0.RP09.UPSB.DSB2.POFX () != Zero) + { + \_SB.PCI0.RP09.UPSB.DSB2.PCIA = Zero + + // Debug = "TB:UPSB:DSB2:PCDA - Put upstream bridge into D3" + \_SB.PCI0.RP09.UPSB.DSB2.PSTA = 0x03 + + // Debug = "TB:UPSB:DSB2:PCDA - Set link disable on upstream bridge" + \_SB.PCI0.RP09.UPSB.DSB2.LDIS = One + + Local5 = (Timer + 0x00989680) + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:DSB2:PCDA - Wait for link to drop..." + If (\_SB.PCI0.RP09.UPSB.DSB2.LACR == One) + { + If (\_SB.PCI0.RP09.UPSB.DSB2.LACT == Zero) + { + // Debug = "TB:UPSB:DSB2:PCDA - No link activity" + Break + } + } + Else + { + If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND)) + { + If (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND == 0xFFFFFFFF) + { + Debug = "TB:UPSB:DSB2:PCDA - VID/DID is -1" + Break + } + } + Else + { + Debug = "TB:UPSB:DSB2:PCDA - XHC2 disabled? BUG?" + } + } + + Sleep (0x0A) + } + + // Debug = "PCDA - disable GPIO" + \_SB.PCI0.RP09.GXCI = Zero + \_SB.PCI0.RP09.UGIO () // power down if needed + } + Else + { + // Debug = "PCDA - Not disabling" + } + + \_SB.PCI0.RP09.UPSB.DSB2.IIP3 = One + } + + /** + * Is power saving requested? + */ + Method (POFX, 0, Serialized) + { + If (!\_SB.PCI0.RP09.RUSB) + { + Debug = "TB:UPSB:DSB2:POFX - USB is idle (RUSB = Zero)" + } + Else + { + Debug = "TB:UPSB:DSB2:POFX - USB is active (RUSB != Zero)" + } + + + Return (!\_SB.PCI0.RP09.RUSB) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:UPSB:DSB2:_PS0" + + If (OSDW ()) + { + PCEU () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:UPSB:DSB2:_PS3" + + If (OSDW ()) + { + PCDA () + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (OSDW ()) + { + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package (0x02) + { + "PCIHotplugCapable", + Zero + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Return (Zero) + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + Name (_SUN, 0x02) // _SUN: Slot User Number + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB3.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (UPS0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (ARE0, PCI_Config, Zero, 0x04) + Field (ARE0, ByteAcc, NoLock, Preserve) + { + AVND, 16 + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DSB0) + { + Name (_ADR, Zero) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1, + Offset (0x3E), + , 6, + SBRS, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB0.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB3) + { + Name (_ADR, 0x00030000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB3.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB4) + { + Name (_ADR, 0x00040000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB4.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + + Device (DEV0) + { + Name (_ADR, Zero) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB4.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB5) + { + Name (_ADR, 0x00050000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB5.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB5.UPS0.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + If (OSDW ()) + { + Return (One) + } + + Return (Zero) + } + } + } + } + + Device (DSB6) + { + Name (_ADR, 0x00060000) // _ADR: Address + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) + Field (A1E1, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + Offset (0x08), + Offset (0x0A), + , 5, + TPEN, 1, + Offset (0x0C), + SSPD, 4, + , 16, + LACR, 1, + Offset (0x10), + , 4, + LDIS, 1, + LRTN, 1, + Offset (0x12), + CSPD, 4, + CWDT, 6, + , 1, + LTRN, 1, + , 1, + LACT, 1, + Offset (0x14), + Offset (0x30), + TSPD, 4 + } + + OperationRegion (A1E2, PCI_Config, 0x80, 0x08) + Field (A1E2, ByteAcc, NoLock, Preserve) + { + Offset (0x01), + Offset (0x02), + Offset (0x04), + PSTA, 2 + } + + Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number + { + Return (SECB) /* \_SB_.PCI0.RP09.UPSB.DSB6.SECB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (OSDW ()) + { + If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) + { + Local0 = Package (0x02) + { + "PCI-Thunderbolt", + One + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Return (Zero) + } + } + } +} diff --git a/patches/SSDT-USBX.dsl b/patches/SSDT-USBX.dsl new file mode 100644 index 0000000..8426ac6 --- /dev/null +++ b/patches/SSDT-USBX.dsl @@ -0,0 +1,41 @@ +/* + * Fix USB Power + * https://dortania.github.io/OpenCore-Post-Install/usb/misc/power.html + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_USBX", 0x00001000) +{ + External (DTGP, MethodObj) // 4 Arguments + External (OSDW, MethodObj) // 0 Arguments + + Scope (\_SB) + { + Device (\_SB.USBX) + { + Name (_ADR, Zero) // _ADR: Address + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package () + { + "kUSBSleepPortCurrentLimit", 1500, + "kUSBSleepPowerSupply", 9600, + "kUSBWakePortCurrentLimit", 1500, + "kUSBWakePowerSupply", 9600, + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (0x0F) + } + + Return (Zero) + } + } + } +} diff --git a/patches/SSDT-XHC1.dsl b/patches/SSDT-XHC1.dsl new file mode 100644 index 0000000..266748d --- /dev/null +++ b/patches/SSDT-XHC1.dsl @@ -0,0 +1,959 @@ +/* + * USB 2.0/ 3.0 + * Reference: https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf + * + * Depends on /patches/OpenCore Patches/ XHC1.plist + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC1", 0x00001000) +{ + External (_SB_.PCI0, DeviceObj) + External (_SB_.PCI0.XHC, DeviceObj) + External (_SB_.PCI0.XHC._PS0, MethodObj) + External (_SB_.PCI0.XHC._PS3, MethodObj) + External (_SB_.PCI0.XHC._DSM, MethodObj) + External (_SB_.PCI0.XHC.RHUB._PS0, MethodObj) + External (_SB_.PCI0.XHC.RHUB._PS2, MethodObj) + External (_SB_.PCI0.XHC.RHUB._PS3, MethodObj) + External (_SB_.PCI0.XHC.XFLT, FieldUnitObj) + External (_SB_.PCI0.RP09.UPSB.DSB2.XHC2, DeviceObj) + External (_SB_.PCI0.RP09.UPSB.DSB2.XHC2.MODU, MethodObj) // 0 Arguments + + External (U2OP, IntObj) + + External (DTGP, MethodObj) // 5 Arguments + External (OSDW, MethodObj) // 0 Arguments + + Scope (\_SB.PCI0.XHC) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (Zero) + } + + Return (0x0F) + } + } + + Scope (\_SB.PCI0) + { + Device (XHC1) + { + Name (_ADR, 0x00140000) // _ADR: Address + Name (SDPC, Zero) + Name (_GPE, 0x6D) // _GPE: General Purpose Events + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + Return (Package (0x02) + { + 0x6D, + 0x03 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (OSDW ()) + { + Return (0x0F) + } + + Return (Zero) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + DEBUG = "XHC1:_DSM" + + \_SB_.PCI0.XHC._DSM (Arg0, Arg1, Arg2, Arg3) + + Local0 = Package (0x04) + { + "acpi-wake-type", + One, + "built-in", + Zero + } + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "XHC1:_PS0" + + \_SB_.PCI0.XHC._PS0 () + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "XHC1:_PS3" + + \_SB_.PCI0.XHC._PS3 () + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Debug = "XHC1:_S3D" + + Return (0x03) + } + + Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State + { + Debug = "XHC1:_S4D" + + Return (0x03) + } + + Method (_S3W, 0, NotSerialized) // _S3W: S3 Device Wake State + { + Debug = "XHC1:_S3W" + + Return (0x03) + } + + Method (_S4W, 0, NotSerialized) // _S4W: S4 Device Wake State + { + Debug = "XHC1:_S4W" + + Return (0x03) + } + + Method (_S0W, 0, NotSerialized) // _S0W: S0 Device Wake State + { + Debug = "XHC1:_S0W" + + If ((\_SB_.PCI0.XHC.XFLT == Zero)) + { + Return (0x00) + } + Else + { + Return (0x03) + } + } + + Method (USRA, 0, Serialized) + { + Debug = "XHC1:USRA" + + Return (0x0F) + } + + Method (SSPA, 0, Serialized) + { + Debug = "XHC1:SSPA" + + Return (0x0D) + } + + Method (CUID, 1, Serialized) + { + Debug = "XHC1:CUID" + + If ((Arg0 == ToUUID ("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) + { + Return (0x01) + } + + Return (0x00) + } + + Method (RTPC, 1, Serialized) + { + Debug = "XHC1:RTPC" + + Return (Zero) + } + + Method (MODU, 0, Serialized) + { + Debug = "XHC1:MODU" + + Local0 = One + + // TB-Controler enabled? + If (CondRefOf (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU)) + { + // If enabled, check if any device is plugged in + Local0 = \_SB.PCI0.RP09.UPSB.DSB2.XHC2.MODU () + } + + Local1 = Zero + + If ((Local0 == One) || (Local1 == One)) + { + Local0 = One + } + ElseIf ((Local0 == 0xFF) || (Local1 == 0xFF)) + { + Local0 = 0xFF + } + Else + { + Local0 = Zero + } + + Return (Local0) + } + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "XHC1:RHUB:_PS0" + + \_SB_.PCI0.XHC.RHUB._PS0 () + } + + Method (_PS2, 0, Serialized) // _PS0: Power State 2 + { + Debug = "XHC1:RHUB:_PS2" + + \_SB_.PCI0.XHC.RHUB._PS2 () + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "XHC1:RHUB:_PS3" + + \_SB_.PCI0.XHC.RHUB._PS3 () + } + + Device (HS01) + { + Name (_ADR, 0x01) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x02) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS02) + { + Name (_ADR, 0x02) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS03) + { + Name (_ADR, 0x03) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x08, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + }) + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) + { + Name (SSP, Package (0x02) + { + "XHC2", + 0x03 + }) + Name (SS, Package (0x02) + { + "XHC2", + 0x03 + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) + { + Local0 = Package (0x02) + { + "NoNumber", + Zero + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS04) + { + Name (_ADR, 0x04) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x08, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + }) + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) + { + Name (SSP, Package (0x02) + { + "XHC2", + 0x04 + }) + Name (SS, Package (0x02) + { + "XHC2", + 0x04 + }) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + + If (CondRefOf (\_SB_.PCI0.RP09.UPSB.DSB2.XHC2) && U2OP == One) + { + Local0 = Package (0x02) + { + "NoNumber", + Zero + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS05) + { + Name (_ADR, 0x05) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS06) + { + Name (_ADR, 0x06) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS07) + { + Name (_ADR, 0x07) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS08) + { + Name (_ADR, 0x08) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS09) + { + Name (_ADR, 0x09) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (HS10) + { + Name (_ADR, 0x0A) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (SS01) + { + Name (_ADR, 0x0D) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (SS02) + { + Name (_ADR, 0x0E) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x03, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + }) + + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (SS03) + { + Name (_ADR, 0x0F) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0xFF, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (SS04) + { + Name (_ADR, 0x10) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + Zero, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x0, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0) + + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Local0 = Package (0x00) {} + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + } + + Method (MBSD, 0, NotSerialized) + { + DEBUG = "XHC1:MBSD" + + Return (One) + } + } + } +} diff --git a/patches/SSDT-XHC2.dsl b/patches/SSDT-XHC2.dsl new file mode 100644 index 0000000..282d811 --- /dev/null +++ b/patches/SSDT-XHC2.dsl @@ -0,0 +1,482 @@ +/* + * USB 3.1 + */ + +DefinitionBlock ("", "SSDT", 2, "tyler", "_XHC2", 0x00001000) +{ + /* Support methods */ + External (DTGP, MethodObj) + External (OSDW, MethodObj) // OS Is Darwin? + + External (_SB.PCI0.RP09.RUSB, IntObj) + External (_SB.PCI0.RP09.GXCI, FieldUnitObj) + External (_SB.PCI0.RP09.UGIO, MethodObj) + External (_SB.PCI0.RP09.UPSB.DSB2, DeviceObj) + External (_SB.PCI0.RP09.UPSB.PCED, MethodObj) + External (_SB.PCI0.RP09.UPSB.MDUV, IntObj) + External (_SB.PCI0.RP09.UPSB.DSB2.PCIA, FieldUnitObj) + External (_SB.PCI0.RP09.UPSB.DSB2.IIP3, FieldUnitObj) + External (_SB.PCI0.RP09.UPSB.DSB2.PRSR, FieldUnitObj) + External (_SB.PCI0.RP09.UPSB.DSB2.LACR, FieldUnitObj) + External (_SB.PCI0.RP09.UPSB.DSB2.LACT, FieldUnitObj) + External (_SB.PCI0.RP09.UPSB.DSB2.LTRN, FieldUnitObj) + + External (_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD, MethodObj) + External (_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC, MethodObj) + + External (TBSE, IntObj) + External (TBTS, IntObj) + External (TBAS, IntObj) + External (UPT1, IntObj) + External (UPT2, IntObj) + External (USME, IntObj) + + Name (U2OP, One) // Companion controller present? + + Scope (_SB.PCI0.RP09.UPSB.DSB2) + { + Device (XHC2) + { + Name (_ADR, Zero) // _ADR: Address + Name (SDPC, Zero) + + OperationRegion (A1E0, PCI_Config, Zero, 0x40) + Field (A1E0, ByteAcc, NoLock, Preserve) + { + AVND, 32, + BMIE, 3, + Offset (0x18), + PRIB, 8, + SECB, 8, + SUBB, 8, + Offset (0x1E), + , 13, + MABT, 1 + } + + /** + * PCI Enable downstream + */ + Method (PCED, 0, Serialized) + { + Debug = "TB:UPSB:DSB2:XHC2:PCED - PCI Enable downstream" + // Debug = "TB:UPSB:DSB2:XHC2:PCED - enable GPIO" + + \_SB.PCI0.RP09.GXCI = One + + // this powers up both TBT and USB when needed + If (\_SB.PCI0.RP09.UGIO () != Zero) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - GPIOs changed, restored = true" + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = One + } + + // Do some link training + Local0 = Zero + Local1 = Zero + Local5 = (Timer + 10000000) + + // Debug = "TB:UPSB:DSB2:XHC2:PCED - restored flag, THUNDERBOLT_PCI_LINK_MGMT_DEVICE.PRSR" + // Debug = \_SB.PCI0.RP09.UPSB.DSB2.PRSR + + If (\_SB.PCI0.RP09.UPSB.DSB2.PRSR != Zero) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for power up" + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for downstream bridge to appear" + + Local5 = (Timer + 10000000) + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for link training..." + If (\_SB.PCI0.RP09.UPSB.DSB2.LACR == Zero) + { + If (\_SB.PCI0.RP09.UPSB.DSB2.LTRN != One) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Link training cleared" + Break + } + } + ElseIf ((\_SB.PCI0.RP09.UPSB.DSB2.LTRN != One) && (\_SB.PCI0.RP09.UPSB.DSB2.LACT == One)) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Link training cleared and link is active" + Break + } + + Sleep (10) + } + + Sleep (150) + } + + \_SB.PCI0.RP09.UPSB.DSB2.PRSR = Zero + + While (Timer <= Local5) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Wait for config space..." + If (\_SB.PCI0.RP09.UPSB.DSB2.XHC2.AVND != 0xFFFFFFFF) + { + // Debug = "TB:UPSB:DSB2:XHC2:PCED - Read VID/DID" + \_SB.PCI0.RP09.UPSB.DSB2.PCIA = One + Break + } + + Sleep (10) + } + + \_SB.PCI0.RP09.UPSB.DSB2.IIP3 = Zero + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (U2OP == One) + { + Local0 = Package (0x06) + { + "USBBusNumber", + Zero, + "AAPL,xhci-clock-id", + One, + "UsbCompanionControllerPresent", + One + } + } + Else + { + Local0 = Package (0x04) + { + "USBBusNumber", + Zero, + "AAPL,xhci-clock-id", + One + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + + Name (HS, Package (0x01) + { + "XHC1" + }) + Name (FS, Package (0x01) + { + "XHC1" + }) + Name (LS, Package (0x01) + { + "XHC1" + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + Return (Package (0x02) + { + 0x6D, + 0x03 + }) + } + + Method (_PS0, 0, Serialized) // _PS0: Power State 0 + { + Debug = "TB:UPSB:DSB2:XHC2:_PS0" + // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - USME: " // One + // Debug = USME + // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBTS: " // One + // Debug = TBTS + // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBSE: " // 0x09 + // Debug = TBSE + // Debug = "TB:UPSB:DSB2:XHC2:_PS0 - TBAS: " // Zero + // Debug = TBAS + + If (OSDW ()) + { + PCED () + } + } + + Method (_PS3, 0, Serialized) // _PS3: Power State 3 + { + Debug = "TB:UPSB:DSB2:XHC2:_PS3" + } + + /** + * Run Time Power Check + * Called by XHC driver when idle + */ + Method (RTPC, 1, Serialized) + { + If (OSDW ()) + { + If (Arg0 <= One) + { + If (Arg0 == One) + { + Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - Enabling" + } + + If (Arg0 == Zero) + { + Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - Disabling" + } + + \_SB.PCI0.RP09.RUSB = Arg0 + } + Else + { + Debug = "TB:UPSB:DSB2:XHC2:RTPC - USB3.2 Run Time Power Check - ??? - Arg0: " + Debug = Arg0 + } + } + + Return (Zero) + } + + /** + * USB cable check + * Called by XHC driver to check cable status + * Used as idle hint. + */ + Method (MODU, 0, Serialized) + { + If (\_SB.PCI0.RP09.UPSB.MDUV == Zero) + { + Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - unplugged (MDUV = Zero)" + } + ElseIf (\_SB.PCI0.RP09.UPSB.MDUV == One) + { + Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - plugged (MDUV = One)" + } + Else + { + Debug = "TB:UPSB:DSB2:XHC2:MODU - USB cable check - ??? - MDUV: " + Debug = \_SB.PCI0.RP09.UPSB.MDUV + } + + Return (\_SB.PCI0.RP09.UPSB.MDUV) + } + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + + Device (SSP1) + { + Name (_ADR, 0x03) // _ADR: Address + + // Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + // { + // If ((USME == Zero)) + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x09)) + // } + // Else + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x0A)) + // } + // } + + // Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + // { + // If ((USME == Zero)) + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, One)) + // } + // Else + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, UPT1)) + // } + // } + + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x09, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + }) + Name (HS, Package (0x02) + { + "XHC1", + 0x03 + }) + Name (FS, Package (0x02) + { + "XHC1", + 0x03 + }) + Name (LS, Package (0x02) + { + "XHC1", + 0x03 + }) + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (U2OP == One) + { + Local0 = Package (0x04) + { + "UsbCPortNumber", + 0x02, + "UsbCompanionPortPresent", + One + } + } + Else + { + Local0 = Package (0x02) + { + "UsbCPortNumber", + 0x02, + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + + Device (SSP2) + { + Name (_ADR, 0x04) // _ADR: Address + + // Method (_UPC, 0, NotSerialized) // _UPC: USB Port Capabilities + // { + // If ((USME == Zero)) + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x09)) + // } + // Else + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TUPC (One, 0x0A)) + // } + // } + + // Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + // { + // If ((USME == Zero)) + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, 0x02)) + // } + // Else + // { + // Return (\_SB.PCI0.RP09.PXSX.TBDU.XHC.RHUB.TPLD (One, UPT2)) + // } + // } + + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + 0x09, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "LOWER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + }) + + Name (HS, Package (0x02) + { + "XHC1", + 0x04 + }) + Name (FS, Package (0x02) + { + "XHC1", + 0x04 + }) + Name (LS, Package (0x02) + { + "XHC1", + 0x04 + }) + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (U2OP == One) + { + Local0 = Package (0x04) + { + "UsbCPortNumber", + One, + "UsbCompanionPortPresent", + One + } + } + Else + { + Local0 = Package (0x02) + { + "UsbCPortNumber", + One, + } + } + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } + } + } + } + } +} \ No newline at end of file diff --git a/patches/iasl b/patches/iasl new file mode 100644 index 0000000..b9a4130 Binary files /dev/null and b/patches/iasl differ diff --git a/patches/iasl-stable b/patches/iasl-stable new file mode 100644 index 0000000..34cb370 --- /dev/null +++ b/patches/iasl-stable @@ -0,0 +1 @@ +500: Internal Server Error \ No newline at end of file diff --git a/patches/update.sh b/patches/update.sh new file mode 100644 index 0000000..4007ddd --- /dev/null +++ b/patches/update.sh @@ -0,0 +1,58 @@ +#!/bin/bash +#set -x # for DEBUGGING + +# Created by stevezhengshiqi on 6 Jun, 2020 +# +# Build ACPI SSDTs for XiaoMi-Pro EFI +# +# Reference: +# https://github.com/williambj1/Hackintosh-EFI-Asus-Zephyrus-S-GX531/blob/master/Makefile.sh by @williambj1 + +# Colors +black=$(tput setaf 0) +red=$(tput setaf 1) +green=$(tput setaf 2) +yellow=$(tput setaf 3) +blue=$(tput setaf 4) +magenta=$(tput setaf 5) +cyan=$(tput setaf 6) +white=$(tput setaf 7) +reset=$(tput sgr0) +bold=$(tput bold) + + +# Exit on Compile Issue +function compileErr() { + echo "${yellow}[${reset}${red}${bold} ERROR ${reset}${yellow}]${reset}: Failed to compile dsl!" + find . -maxdepth 1 -name "*.aml" -exec rm -rf {} + >/dev/null 2>&1 + exit 1 +} + +function init() { + if [[ ${OSTYPE} != darwin* ]]; then + echo "This script can only run in macOS, aborting" + exit 1 + fi + + cd "$(dirname "$0")" || exit 1 +} + +function compile() { + chmod +x iasl* + echo "${green}[${reset}${magenta}${bold} Compiling ACPI Files ${reset}${green}]${reset}" + echo + find . -type f -maxdepth 1 -name "*.dsl" -print0 | xargs -0 -I{} ./iasl -x 10 {} || compileErr && find .. -iname '._*' -delete && rm -f ../EFI-OpenCore/EFI/OC/ACPI/*.aml && mv *.aml ../EFI-OpenCore/EFI/OC/ACPI +} + +function enjoy() { + echo "${red}[${reset}${blue}${bold} Done! Enjoy! ${reset}${red}]${reset}" + echo +} + +function main() { + init + compile + enjoy +} + +main