2020-11-14 10:19:55 -06:00
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/*
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* Partition and continuation of Thunderbolt 3 patch.
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* Depends on other TB-DSB* patches as well as /patches/OpenCore Patches/ Thunderbolt3.plist
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*
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* Credits @benbender
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*/
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DefinitionBlock ("", "SSDT", 2, "tyler", "_TBDSB6", 0x00001000)
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{
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// Common utils from SSDT-Darwin.dsl
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External (DTGP, MethodObj) // 5 Arguments
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External (OSDW, MethodObj) // 0 Arguments
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External (_SB.PCI0.RP09.PXSX, DeviceObj)
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External (TBSE, IntObj)
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External (TBTS, IntObj)
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If (((TBTS == One) && (TBSE == 0x09)))
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{
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Scope (\_SB.PCI0.RP09.PXSX)
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{
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Device (DSB6)
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{
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Name (_ADR, 0x00060000) // _ADR: Address
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OperationRegion (A1E0, PCI_Config, Zero, 0x40)
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Field (A1E0, ByteAcc, NoLock, Preserve)
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{
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AVND, 32,
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BMIE, 3,
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Offset (0x18),
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PRIB, 8,
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SECB, 8,
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SUBB, 8,
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Offset (0x1E),
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, 13,
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MABT, 1
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}
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OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
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Field (A1E1, ByteAcc, NoLock, Preserve)
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{
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Offset (0x01),
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Offset (0x02),
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Offset (0x04),
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Offset (0x08),
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Offset (0x0A),
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, 5,
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TPEN, 1,
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Offset (0x0C),
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SSPD, 4,
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, 16,
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LACR, 1,
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Offset (0x10),
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, 4,
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LDIS, 1,
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LRTN, 1,
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Offset (0x12),
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CSPD, 4,
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CWDT, 6,
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, 1,
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LTRN, 1,
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, 1,
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LACT, 1,
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Offset (0x14),
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Offset (0x30),
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TSPD, 4
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}
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OperationRegion (A1E2, PCI_Config, 0x80, 0x08)
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Field (A1E2, ByteAcc, NoLock, Preserve)
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{
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Offset (0x01),
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Offset (0x02),
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Offset (0x04),
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PSTA, 2
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}
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Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
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{
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2020-11-17 14:32:44 -06:00
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Return (SECB) /* \_SB_.PCI0.RP09.PXSX.DSB6.SECB */
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2020-11-14 10:19:55 -06:00
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}
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (OSDW ())
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{
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Return (0x0F)
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}
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Return (Zero)
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}
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Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
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{
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Return (Zero)
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}
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}
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}
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}
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}
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