2019-12-19 21:33:12 -06:00
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20190405 (64-bit version)
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* Copyright (c) 2000 - 2019 Intel Corporation
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*
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* Disassembling to non-symbolic legacy ASL operators
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*
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* Disassembly of SSDT-10-Wwan.aml, Tue Apr 30 02:38:48 2019
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*
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* Original Table Header:
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* Signature "SSDT"
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* Length 0x000002D1 (721)
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* Revision 0x02
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* Checksum 0x26
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* OEM ID "LENOVO"
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* OEM Table ID "Wwan"
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* OEM Revision 0x00000001 (1)
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* Compiler ID "INTL"
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* Compiler Version 0x20160527 (538314023)
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*/
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DefinitionBlock ("", "SSDT", 2, "LENOVO", "Wwan", 0x00000001)
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{
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External (_SB_.GPC0, MethodObj) // 1 Arguments
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External (_SB_.PCI0.GPCB, MethodObj) // 0 Arguments
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External (_SB_.PCI0.RP03, DeviceObj)
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External (_SB_.PCI0.RP03._ADR, MethodObj) // 0 Arguments
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External (_SB_.PCI0.RP03.PXSX, DeviceObj)
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External (_SB_.PCI0.RP03.PXSX._ADR, IntObj)
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External (_SB_.SPC0, MethodObj) // 2 Arguments
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External (NEXP, IntObj)
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External (WDC2, IntObj)
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External (WDCT, IntObj)
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External (WGUR, IntObj)
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External (WLCT, IntObj)
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External (WMNS, IntObj)
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External (WMXS, IntObj)
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Name (RSTP, Package (0x04)
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{
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Zero,
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Zero,
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Zero,
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Zero
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})
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Scope (\_SB.PCI0.RP03)
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{
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Method (M2PC, 1, Serialized)
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{
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Store (\_SB.PCI0.GPCB (), Local0)
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Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
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Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
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Return (Local0)
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}
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Method (GMIO, 1, Serialized)
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{
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OperationRegion (PXCS, SystemMemory, M2PC (\_SB.PCI0.RP03._ADR ()), 0x20)
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Field (PXCS, AnyAcc, NoLock, Preserve)
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{
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Offset (0x18),
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PBUS, 8,
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SBUS, 8
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}
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Store (\_SB.PCI0.GPCB (), Local0)
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Add (Local0, ShiftRight (And (Arg0, 0x001F0000), One), Local0)
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Add (Local0, ShiftLeft (And (Arg0, 0x07), 0x0C), Local0)
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Add (Local0, ShiftLeft (SBUS, 0x14), Local0)
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Return (Local0)
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}
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Scope (PXSX)
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{
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Method (_RST, 0, Serialized) // _RST: Device Reset
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{
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OperationRegion (PXCS, SystemMemory, GMIO (\_SB.PCI0.RP03.PXSX._ADR), 0x0480)
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Field (PXCS, AnyAcc, NoLock, Preserve)
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{
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VDID, 16,
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DVID, 16,
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Offset (0x78),
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DCTL, 16,
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DSTS, 16,
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Offset (0x80),
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LCTL, 16,
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LSTS, 16,
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Offset (0x98),
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DCT2, 16,
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Offset (0x148),
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Offset (0x14C),
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MXSL, 16,
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MNSL, 16
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}
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Store (\_SB.GPC0 (\WGUR), Local0)
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And (Local0, 0xFFFFFFFFFFFFFEFF, Local0)
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\_SB.SPC0 (\WGUR, Local0)
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Sleep (0xC8)
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Notify (\_SB.PCI0.RP03.PXSX, One) // Device Check
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Or (Local0, 0x0100, Local0)
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\_SB.SPC0 (\WGUR, Local0)
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Sleep (0xC8)
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If (LEqual (NEXP, Zero))
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{
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Store (\WDCT, DCTL) /* \_SB_.PCI0.RP03.PXSX._RST.DCTL */
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Store (\WLCT, LCTL) /* \_SB_.PCI0.RP03.PXSX._RST.LCTL */
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Store (\WDC2, DCT2) /* \_SB_.PCI0.RP03.PXSX._RST.DCT2 */
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Store (\WMXS, MXSL) /* \_SB_.PCI0.RP03.PXSX._RST.MXSL */
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Store (\WMNS, MNSL) /* \_SB_.PCI0.RP03.PXSX._RST.MNSL */
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}
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Notify (\_SB.PCI0.RP03.PXSX, One) // Device Check
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}
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}
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}
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}
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