2019-10-03 02:58:26 -05:00
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/*
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* Intel ACPI Component Architecture
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* AML/ASL+ Disassembler version 20190509 (64-bit version)
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* Copyright (c) 2000 - 2019 Intel Corporation
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*
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* Disassembling to non-symbolic legacy ASL operators
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*
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2019-12-19 21:33:12 -06:00
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* Disassembly of SSDT-x5_4-Cpu0Hwp.aml, Mon Dec 16 16:11:48 2019
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2019-10-03 02:58:26 -05:00
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*
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* Original Table Header:
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* Signature "SSDT"
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* Length 0x000000BA (186)
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* Revision 0x02
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* Checksum 0x7D
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* OEM ID "PmRef"
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* OEM Table ID "Cpu0Hwp"
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* OEM Revision 0x00003000 (12288)
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* Compiler ID "INTL"
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* Compiler Version 0x20160527 (538314023)
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*/
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DefinitionBlock ("", "SSDT", 2, "PmRef", "Cpu0Hwp", 0x00003000)
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{
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External (_PR_.CFGD, IntObj)
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External (_PR_.HWPA, FieldUnitObj)
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External (_PR_.HWPV, IntObj)
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External (_PR_.PR00, DeviceObj)
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External (_PR_.PR00.CPC2, PkgObj)
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External (_PR_.PR00.CPOC, PkgObj)
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External (CPC2, IntObj)
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External (CPOC, IntObj)
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External (TCNT, FieldUnitObj)
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Scope (\_PR.PR00)
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{
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Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
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{
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If (And (\_PR.CFGD, 0x01000000))
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{
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Return (CPOC) /* External reference */
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}
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Else
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{
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Return (CPC2) /* External reference */
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}
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}
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}
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}
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